![Page 1: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/1.jpg)
OPERATING
SYSTEMSMemory Management
![Page 2: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/2.jpg)
Topics
What is memory management
Source code to execution
Address binding
Logical and physical address spaces
Dynamic loading, dynamic linking, and overlays
![Page 3: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/3.jpg)
Memory Hierarchy
Very small, extremely fast, extremely expensive, and volatile CPU
registers
Small, very fast, expensive, and volatile cache
Hundreds of megabytes of medium-speed, medium-price, volatile
main memory
Hundreds of gigabytes of slow, cheap, and non-volatile secondary
storage
![Page 4: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/4.jpg)
Purpose of Memory Management
To ensure fair, secure, orderly, and efficient
use of memory
![Page 5: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/5.jpg)
Memory Management
Keeping track of used and free memory space
When, where, and how much memory to allocate and
deallocate
Swapping processes in and out of main memory
![Page 6: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/6.jpg)
Source to Execution
Compile/Assemble
↓
Link
↓
Load
↓
Execute
![Page 7: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/7.jpg)
![Page 8: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/8.jpg)
Binding instructions and data to memory addresses
Compile time
Load time
Execution time
Address Binding
![Page 9: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/9.jpg)
Compile time: If you know at compile time where the
process will reside in memory, the absolute code can
be generated. Process must reside in the same
memory region for it to execute correctly.
Address Binding
![Page 10: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/10.jpg)
Load time: If the location of a process in memory is not
known at compile time, then the compiler must generate
re-locatable code. In this case the final binding is
delayed until load time. Process can be loaded in different
memory regions.
Address Binding
![Page 11: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/11.jpg)
Address Binding
Execution time: If the process can be moved during
its execution from one memory region to another, then
binding must be delayed until run time. Special
hardware must be available for this to work.
![Page 12: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/12.jpg)
Logical and Physical Addresses
Logical address: An address generated by the
process/CPU; refers to an instruction or data in the process
Physical address: An address for a main memory location
where instruction or data resides
![Page 13: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/13.jpg)
Logical and Physical Address Spaces
The set of all logical addresses generated by a process
comprises its logical address space.
The set of physical addresses corresponding to these logical
addresses comprises the physical address space for the
process.
![Page 14: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/14.jpg)
Logical and Physical Address Spaces
The run-time mapping from logical to physical
addresses is done by a piece of the CPU hardware,
called the memory management unit (MMU).
![Page 15: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/15.jpg)
Example
The base register is called the relocation register.
The value in the relocation register is added to every
address generated by a user process at the time it is
sent to memory.
![Page 16: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/16.jpg)
Example
14000Process
![Page 17: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/17.jpg)
Example
In i8086, the logical address of the next instruction is
specified by the value of instruction pointer (IP). The
physical address for the instruction is computed by shifting
the code segment register (CS) left by four bits and
adding IP to it.
![Page 18: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/18.jpg)
Example
CPU
CS * 24
+
MMU
Logical
address
Physical
address
![Page 19: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/19.jpg)
Example
Logical address (16-bit)
IP = 0B10h
CS = D000h
Physical address (20-bit)
CS * 24
+ IP = D0B10h
Sizes of logical and physical address spaces?
![Page 20: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/20.jpg)
Dynamic Loading
With dynamic loading, a routine is not loaded into the
main memory until it is called.
All routines are kept on the disk in a re-locatable
format.
The main program is loaded into memory and is
executed
![Page 21: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/21.jpg)
Dynamic Loading
Advantages
Potentially less time needed to load a program
Potentially less memory space needed
Disadvantage
Run-time activity
![Page 22: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/22.jpg)
Dynamic Linking
In static linking, system language libraries are
linked at compile time and, like any other object
module, are combined by the loader into the
binary image
![Page 23: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/23.jpg)
Dynamic Linking
In dynamic linking, linking is postponed until run-
time.
A library call is replaced by a piece of code, called
stub, which is used to locate memory-resident library
routine
![Page 24: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/24.jpg)
Dynamic Linking
During execution of a process, stub is replaced by the
address of the relevant library code and the code is
executed
If library code is not in memory, it is loaded at this time
![Page 25: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/25.jpg)
Dynamic Linking
Advantages
Potentially less time needed to load a program
Potentially less memory space needed
Less disk space needed to store binaries
![Page 26: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/26.jpg)
Dynamic Linking Disadvantages
Time-consuming run-time activity, resulting in slower
program execution
gcc compiler
Dynamic linking by default
-static option allows static linking
![Page 27: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/27.jpg)
Topics
Dynamic linking
Overlays
Swapping
Contiguous storage allocation
MFT and MVT
![Page 28: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/28.jpg)
Overlays
Allow a process to be larger than the amount of
memory allocated to it
Keep in memory only those instructions and data that
are needed at any given time
![Page 29: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/29.jpg)
Overlays
When other instructions are needed, they are loaded into
the space occupied previously by instructions that are no
longer needed
Implemented by user
Programming design of overlay structure is complex and not
possible in all cases
![Page 30: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/30.jpg)
Overlays Example
2-Pass assembler/compiler
Available main memory: 150k
Code size: 200k
Pass 1 ……………….. 70k
Pass 2 ……………….. 80k
Common routines …... 30k
Symbol table ………… 20k
![Page 31: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/31.jpg)
Overlays Example
![Page 32: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/32.jpg)
Swapping
Swap out and swap in (or roll out and roll in)
Major part of swap time is transfer time; the total transfer time is directly proportional to the amount of memory swapped
Large context switch time
![Page 33: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/33.jpg)
Swapping
![Page 34: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/34.jpg)
Cost of Swapping
Process size = 1 MB
Transfer rate = 5 MB/sec
Swap out time = 1/5 sec
= 200 ms
Average latency = 8 ms
Net swap out time = 208 ms
Swap out + swap in = 416 ms
![Page 35: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/35.jpg)
Issues with Swapping
Quantum for RR scheduler
Pending I/O for swapped out process
User space used for I/O
Solutions
Don’t swap out processes with pending I/O
Do I/O using kernel space
![Page 36: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/36.jpg)
Contiguous Allocation
Kernel space, user space
A process is placed in a single contiguous area in memory
Base (re-location) and limit registers are used to point to
the smallest memory address of a process and its size,
respectively.
![Page 37: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/37.jpg)
Contiguous Allocation
Main
Memory
Process
![Page 38: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/38.jpg)
MFT
Multiprogramming with fixed tasks (MFT)
Memory is divided into several fixed-size partitions.
Each partition may contain exactly one process/task.
![Page 39: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/39.jpg)
MFT
Boundaries for partitions are set at boot time and are not
movable.
An input queue per partition
The degree of multiprogramming is bound by the number
of partitions.
![Page 40: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/40.jpg)
Partition 4
Partition 3
Partition 2
Partition 1
OS
MFT
100 K
300 K
200 K
150 K
Input
Queues
![Page 41: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/41.jpg)
Potential for wasted memory space—an empty
partition but no process in the associated queue
Load-time address binding
MFT With Multiple Input Queues
![Page 42: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/42.jpg)
Single queue for all partitions
Search the queue for a process when a partition
becomes empty
First-fit, best-fit, worst-fit space allocation algorithms
MFT With Single Input Queue
![Page 43: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/43.jpg)
Partition 4
Partition 3
Partition 2
Partition 1
OS
100 K
300 K
200 K
150 K
Input Queue
MFT With Single Input Queue
![Page 44: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/44.jpg)
Internal fragmentation—wasted space inside a fixed-
size memory region
No sharing between processes.
Load-time address binding with multiple input queues
MFT Issues
![Page 45: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/45.jpg)
Topics
MVT
Paging
Addressing and logical to physical address translation
Page table implementation
![Page 46: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/46.jpg)
Multiprogramming with variable tasks (MFT)
Both the number and size of partitions change with time
A process still resides in one region but can be of any
size up to the size of the user space and can change with
time.
MVT
![Page 47: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/47.jpg)
Jobs can move from one partition to another
Dynamic address binding
No internal fragmentation
Introduces external fragmentation
MVT
![Page 48: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/48.jpg)
MVT
200K
50K
![Page 49: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/49.jpg)
External Fragmentation
External Fragmentation refers to the state of memory
space when total amount of unused memory space
exists to satisfy a request but this memory space is
not contiguous.
![Page 50: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/50.jpg)
External Fragmentation
Compact main memory (shuffle processes around to
put free space in one contiguous area) May called
defragmentation
Slows down execution of currently running processes
![Page 51: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/51.jpg)
Paging
Divide physical memory into fixed-sized blocks, called
frames
Divide logical memory into blocks of the same size, called
pages
Size of a page is a power of 2
Typical page sizes: 1K – 16K
![Page 52: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/52.jpg)
Paging
Keep track of all free frames.
To run a program of size n pages, find n free frames and
load program pages into these frames.
Keep track of a program’s pages in the main memory by
using the page table.
![Page 53: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/53.jpg)
Paging
Process Address
Space
Physical Address Space
01234567
012
…
910
…
15
![Page 54: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/54.jpg)
Paging
Process Address
Space
Physical Address Space
3
9
11
…
1
Page Table
01234567
0123…
7
012
…
910
…
15
Page
![Page 55: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/55.jpg)
Paging
Process Address
Space
Physical Address Space
9
…
Page Table
01234567
0123…
7
012
…
910
…
15
![Page 56: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/56.jpg)
Paging
Logical address space of a process can be
noncontiguous; a process page is allocated a frame
whenever the latter is available.
Set up a page table to translate logical addresses to
physical addresses.
Internal fragmentation
![Page 57: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/57.jpg)
Addressing in Paging
Logical address: (p, d)
where, p is page number and d is offset within the page
p is used to index the process page table; page table
entry contains the frame number, f, where page p is
loaded
![Page 58: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/58.jpg)
Addressing in Paging
Physical address of the location referenced by (p,d) is
computed by appending d at the end of f, as shown
below:
f d
![Page 59: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/59.jpg)
Address Translation
f
![Page 60: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/60.jpg)
Addressing Example
![Page 61: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/61.jpg)
Paging Example
Page size = 4 bytes
Process address space =
4 pages
Physical address space =
8 frames
Logical address: (1,3)
= 0111
Physical address: (6,3)
= 11011
0
1
2
3
PageFrame
11011
0111
![Page 62: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/62.jpg)
Addressing in Paging
Logical address space of 16 pages of 1024 words
each, mapped into a physical memory of 32 frames.
Logical address size?
Physical address size?
Number of bits for p, f, and d?
![Page 63: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/63.jpg)
Topics
Addressing and logical to physical address translation
Examples: Intel P4 and PDP-11
Page table implementation
Performance of paging
Protection in paging
![Page 64: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/64.jpg)
Paging
Process Address
Space
Physical Address Space
01234567
012
…
910
…
15
![Page 65: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/65.jpg)
Paging
Process Address
Space
Physical Address Space
3
9
11
…
1
Page Table
01234567
0123…
7
012
…
910
…
15
Page
![Page 66: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/66.jpg)
Paging
Process Address
Space
Physical Address Space
9
…
Page Table
01234567
0123…
7
012
…
910
…
15
![Page 67: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/67.jpg)
Address Translation
f
![Page 68: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/68.jpg)
Paging Example
Page size = 4 bytes
Process address space =
4 pages
Physical address space =
8 frames
Logical address: (1,3)
= 0111
Physical address: (6,3)
= 11011
0
1
2
3
PageFrame
11011
0111
![Page 69: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/69.jpg)
Addressing in Paging
Logical address space of 16 pages of 1024 words
each, mapped into a physical memory of 32 frames.
Logical address size?
Physical address size?
Number of bits for p, f, and d?
![Page 70: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/70.jpg)
Addressing in Paging
No. of bits for p = ceiling [log2 16] bits
= 4 bits
No. of bits for f = ceiling [log2 32] bits
= 5 bits
No. of bits for d = ceiling [log2 2048] bits
= 11 bits
![Page 71: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/71.jpg)
Addressing in Paging
Logical address size = |p| + |d|
= 4+11
= 15 bits
Physical address size = |f| + |d|
= 5+11
= 16 bits
![Page 72: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/72.jpg)
Page Table Size
Page table size = NP * PTES
where NP is the number of pages in the process address
space and PTES is the page table entry size (equal to |f|
based on our discussion so far).
Page table size = 16 * 5 bits
= 16 bytes
![Page 73: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/73.jpg)
Paging in Intel P4
32-bit linear address
4K page size
Maximum pages in a process address space = 232
/ 4K
Number of bits for d = log2 4K
= 12
Number of bits for p = 32 - 12
![Page 74: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/74.jpg)
Paging in PDP-11
16-bit logical address
8K page size
Maximum pages in a process address space = 216
/
8K = 8
|d| = log2 8K = 13 bits
|p| = 16 – 13 = 3 bits
|f| = ? bits
![Page 75: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/75.jpg)
Another Example
Logical address = 32-bit
Process address space = 232
B
= 4 GB
Main memory = RAM = 512 MB
Page size = 4K
Maximum pages in a process address space = 232
/ 4K
= 1M
![Page 76: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/76.jpg)
Another Example
|d| = log2 4K = 12 bits
|p| = 32 – 12 = 20 bits
No. of frames = 512 M / 4 K
= 128 K
|f| = ceiling [log2 128 K] bits
= 17 bits ≈ 4 bytes
Physical address = 17+12 bits
![Page 77: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/77.jpg)
Implementation of Page Table
In CPU registers
OK for small process address spaces and large page
sizes
Effective memory access time (Teffective) is about the
same as memory access time (Tmem)
PDP-11
![Page 78: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/78.jpg)
Implementation of Page Table
Keep page table in the main memory
Page table base register (PTBR)
Teffective = 2Tmem
Teffective is not acceptable
![Page 79: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/79.jpg)
Implementation of Page Table
Use a special, small, fast lookup hardware, called
translation look-aside buffer (TLB)
Typically 64–1024 entries
An entry is (key, value)
Parallel search for key; on a hit, value is returned
![Page 80: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/80.jpg)
Implementation of Page Table
(key,value) is (p,f) for paging
For a logical address, (p,d), TLB is searched for p. If an
entry with a key p is found, we have a hit and f is used to
form the physical address. Else, page table in the main
memory is searched.
![Page 81: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/81.jpg)
TLB
Logical address: (p, d)
p
f
![Page 82: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/82.jpg)
Implementation of Page Table
The TLB is loaded with the (p,f) pair so that future
references to p are found in the TLB, resulting in
improved hit ratio.
On a context switch, the TLB is flushed and is loaded
with values for the scheduled process.
![Page 83: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/83.jpg)
Paging Hardware
![Page 84: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/84.jpg)
Performance of Paging
Teffective on a hit = Tmem + TTLB
Teffective on a miss = 2Tmem + TTLB
If HR is hit ratio and MR is miss ratio, then
Teffective = HR (TTLB + Tmem)
+ MR (TTLB + 2Tmem)
![Page 85: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/85.jpg)
Example
Tmem = 100 nsec
TTLB = 20 nsec
Hit ratio is 80%
Teffective = ?
Teffective = 0.8 (20 + 100)
+ 0.2 (20 + 2x100)
= 140 nanoseconds
![Page 86: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/86.jpg)
Example
Tmem = 100 nsec
TTLB = 20 nsec
Hit ratio is 98%
Teffective = ?
Teffective = 0.98 (20 + 100)
+ 0.02 (20 + 2x100)
= 122 nanoseconds
![Page 87: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/87.jpg)
Topics
Protection in paging
Structure of the page table
Multi-level paging
Hashed page tables
Inverted page table
Sharing in paging
![Page 88: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/88.jpg)
Example
Tmem = 100 nsec
TTLB = 20 nsec
Hit ratio is 98%
Teffective = ?
Teffective = 0.98 (20 + 100)
+ 0.02 (20 + 2x100)
= 122 nanoseconds
![Page 89: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/89.jpg)
Protection
Memory protection in paging is achieved by associating
protection bit with each page table entry
Valid/Invalid bit (v)—page in the process address space
or not
Read, write, and execute bits (r, w, x)
![Page 90: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/90.jpg)
Protection
![Page 91: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/91.jpg)
Structure of the Page Table
Hierarchical / Multilevel Paging
Hashed Page Table
Inverted Page Table
![Page 92: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/92.jpg)
Multilevel Paging
Logical address = 32-bit
Page size = 4K bytes (212
bytes)
Page table entry = 4 bytes
Maximum pages in a process address space = 232
/
4K = 1M
![Page 93: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/93.jpg)
Multilevel Paging
Maximum pages in a process address space = 232
/
4K = 1M
Page table size = 4M bytes
This page cannot fit in one page Page the page table
![Page 94: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/94.jpg)
Multilevel Paging
Page table needed for keeping track of pages of the
page table—called the outer page table or page
directory
No. of pages in the page table is 4M / 4K = 1K
Size of the outer page table is 1K * 4 bytes = 4K bytes
outer page will fit in one page
![Page 95: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/95.jpg)
Multilevel Paging 2-level paging
![Page 96: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/96.jpg)
Multilevel Paging Addressing and address translation
32-bit logical address: p1 used to index the outer page
table and p2 to index the inner page table
page number page offset
p1 p2 d
10 10 12
![Page 97: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/97.jpg)
Multilevel Paging
p1{
p2{
![Page 98: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/98.jpg)
Multilevel Paging
![Page 99: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/99.jpg)
DEC VAX
Logical address = 32 bits
Page size = 512 bytes = 29 bytes
Process address space divided into four equal sections
Pages per section = 230
/ 29
= 221
= 2M
Size of a page table entry = 4 bytes
![Page 100: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/100.jpg)
DEC VAX
Bits needed for page offset
= log2 512
= 9 bits
Bits to specify a section = log2 4
= 2 bits
Bits needed to index page table for a section= log2 221
= 21 bits
Size of a page table = 221
* 4
= 8 MB
![Page 101: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/101.jpg)
DEC VAX
8 MB page table is paged into 8MB / 512 = 2 K pages
Size of the outer page table (2K * 4 = 8 KB) is further paged,
resulting in 3-level paging per section
page number page offset
s p d
2 21 9
section
![Page 102: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/102.jpg)
More Examples
32-bit Sun SPARC supports 3-level paging
32-bit Motorola 68030 supports 4-level paging
64-bit Sun UltraSPARC supports 7-level paging – too
many memory references needed for address translation
![Page 103: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/103.jpg)
Hashed Page Table
A common approach to handle address spaces larger
then 32 bits
Usually open hashing is used
Each entry in the linked list has three fields: page
number, frame number for the page, and pointer to the
next element—(p, f, next)
![Page 104: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/104.jpg)
Hashed Page Table
![Page 105: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/105.jpg)
Inverted Page Table
One entry per real page in memory
Page table size is limited by the number of frames (i.e.,
the physical memory) and not process address space
Each entry in the page table contains (pid, p)
![Page 106: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/106.jpg)
Inverted Page Table
If a page ‘p’ for a process is loaded in frame ‘f’, its entry
is stored at index ‘f’ in the page table
We effectively index the page table with frame number;
hence the name inverted page table
Examples: 64-bit UltraSPARC and PowerPC
![Page 107: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/107.jpg)
Inverted Page Table
Frame Number
![Page 108: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/108.jpg)
Recap of Lecture
Structure of the page table
Multi-level paging
Hashed page tables
Inverted page table
![Page 109: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/109.jpg)
Topics
Sharing in paging
Segmentation
Logical to physical address translation
Hardware support needed
Protection and sharing
![Page 110: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/110.jpg)
Shared Pages
Reentrant (read-only) code pages of a process
address space can be shared
Shared code appears in the same logical address
space of all processes
Multiple invocations of pico or gcc
![Page 111: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/111.jpg)
Shared Pages
![Page 112: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/112.jpg)
Segmentation
A memory management scheme that supports programmer’s view of memory.
A segment is a logical unit such as: main program, procedure, function, method, object, global variables, stack, symbol table
A program is a collection of segments
![Page 113: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/113.jpg)
Segmentation
![Page 114: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/114.jpg)
Segmentation
1
3
2
4
logical memory physical memory
5
![Page 115: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/115.jpg)
Segmentation
1
3
2
4
1
4
2
3
logical memory physical memory
1
4
2
35
5
![Page 116: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/116.jpg)
Segmentation
1
3
2
4
1
4
2
3
logical memory physical memory
1
4
2
3
5
5
segment table
![Page 117: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/117.jpg)
Segmentation
Logical address consists of a two tuple: <segment-number, offset>
Segment table – maps two-dimensional logical addresses to physical addresses
![Page 118: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/118.jpg)
Segmentation
Each segment table entry has:base – contains the starting physical address where the segments reside in memory.
limit – specifies the length of the segment.
![Page 119: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/119.jpg)
Segmentation
Segment-table base register (STBR) points to the segment table’s location in memory.
Segment-table length register (STLR) indicates number of segments used by a program
Segment number s is legal if s < STLR
![Page 120: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/120.jpg)
Segmentation
CPU
![Page 121: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/121.jpg)
Segmentation Architecture
RelocationDynamicBy segment table
SharingShared segmentsSame segment number
![Page 122: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/122.jpg)
Segmentation Architecture
Dynamic Storage AllocationFirst fitBest fitWorst fitExternal fragmentation
![Page 123: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/123.jpg)
Segmentation Architecture
Protection: Bits are associated for this purpose with each entry in segment table:Validation bit = 0 illegal segment
Read, write, execute bits
![Page 124: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/124.jpg)
Example
![Page 125: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/125.jpg)
Address Translation
Logical and Physical Addresses
(2, 399) – PA: 4300+399 = 4699
(4, 0) – PA: 4700+0 = 4700
(4, 1000) trap
(3, 1300) trap
(6, 297) trap
![Page 126: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/126.jpg)
Sharing of Segments
Sharing at the segment level and not at the fixed-size
page level
Sharing at the code or data level
Segment table of multiple processes point to the same
segment
![Page 127: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/127.jpg)
Sharing of Segments
![Page 128: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/128.jpg)
Issues with Segmentation
External Fragmentation Total memory space exists to satisfy a space allocation request for a segment, but memory space is not contiguous.
![Page 129: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/129.jpg)
Reduce external fragmentation by compaction Shuffle segments to place free memory together in one block.
Compaction is possible only if relocation is dynamic, and is done at execution time.
Issues with Segmentation
![Page 130: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/130.jpg)
I/O problemLatch job in memory while it is involved in I/O.
Do I/O only into OS buffers
Very large segments page program segments—paged segmentation
Issues with Segmentation
![Page 131: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/131.jpg)
Topics
Paged segmentation
Examples of paged segmentation: MULTICS under
GE 345 and OS/2, Windows, and Linux under Intel
CPUs
![Page 132: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/132.jpg)
Shared Pages
![Page 133: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/133.jpg)
Segmentation
CPU
![Page 134: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/134.jpg)
Example
![Page 135: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/135.jpg)
Sharing of Segments
![Page 136: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/136.jpg)
Protection
Associate valid/invalid bit with each segment table
entry to indicate if the referenced segment is part of the
process address space or not
Read, write, and execute bits to define legal operations
on a segment
![Page 137: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/137.jpg)
Paged Segmentation
Divide every segment in a process into fixed size
pages
Need for a page table per segment
CPU’s memory management unit must support both
segmentation and paging
![Page 138: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/138.jpg)
Paged Segmentation
1
3
2
4
logical memory
5
physical memory
![Page 139: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/139.jpg)
Paged Segmentation
1
3
2
4
logical memory
5
physical memory
1
2
0
3
0
1
2
3
.
.
.
10
126
127
3
1
126
10
page
table
![Page 140: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/140.jpg)
Paged Segmentation
Logical address is still <s,d>, with s used to index the
segment table
Each segment table entry consist of the tuple
<segment-length, page-table-base>
The logical address is legal if d <
segment-length
![Page 141: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/141.jpg)
Paged Segmentation
Segment offset, d, is partitioned into two parts: p
and d’, where p is used to index the page table
associated with segment, s, and d’ is used as
offset within a page
![Page 142: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/142.jpg)
Paged Segmentation
p indexes the page table to retrieve frame, f, and
physical address (f,d’) is formed
s d
p d’
index segment
table
index page table offset within the page p
![Page 143: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/143.jpg)
Paged Segmentation
![Page 144: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/144.jpg)
MULTICS Example
GE 345 processor Logical address = 34 bits Page size = 1 KB s is 18 bits and d is 16 bits Size of p and d’, largest
segment size, and max. number of segments per process?
![Page 145: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/145.jpg)
MULTICS Example
Largest segment = 2d bytes= 216 bytes
Maximum number of pages per segment = 216 / 1 K = 64
|p| = log2 64 bits = 6 bits |d’| = log2 1 K = 10 bits Maximum number of segments
per process = 2s = 218
![Page 146: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/146.jpg)
MULTICS Example
s d
p d’
18 bits
6 bits 10 bits
![Page 147: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/147.jpg)
MULTICS Example Consider a process with its
segment 15 having 5096 bytes. The process generates a logical address (15,3921).
Is it a legal address? How many pages does the
segment have? What page does the logical
address refer to?
![Page 148: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/148.jpg)
MULTICS Example Is it a legal address? Yes How many pages does the
segment have? ceiling[5096/1024]= 5
What page does the logical address refers to? ceiling[3921/1024]= 4(i.e., page number 3)
![Page 149: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/149.jpg)
MULTICS Example
What are the value of d’ and the physical address if page number 3 (i.e., the fourth page) is in frame 12?
d’ = 3921 – 3*1K = 849
Physical address = 12*1K + 849
= 13137
![Page 150: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/150.jpg)
MULTICS Example
15 3921
3 849
s
p d’
d
page table for
segment 15
0
1
2
3
4
12
![Page 151: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/151.jpg)
MULTICS Example
15 3921
3 849
3921
12 12 849
13137
![Page 152: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/152.jpg)
Intel 80386 Example
IBM OS/2, Microsoft Windows, and Linux
Paged segmentation with two-level paging
Logical address = 48 bits 16-bit selector and 32-bit
offset Page size = 4 KB
![Page 153: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/153.jpg)
Intel 80386 Example
4-byte page table entry 32-entry TLB, covering
32*4K (128 KB) memory … TLB Reach
![Page 154: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/154.jpg)
Intel 80386 Example
13-bit Segment #
16-bit Selector
g p
32-bit Offset
s2-bit field for
specifying the
privilege level
1-bit field to specify GDT or
LDT
![Page 155: Memory Management. Topics What is memory management Source code to execution Address binding Logical and physical address spaces Dynamic loading, dynamic](https://reader035.vdocuments.net/reader035/viewer/2022081511/56649e605503460f94b5b707/html5/thumbnails/155.jpg)
Intel 80386 Example
Real Mode
20-bit physical address is obtained by shifting left the Selector value by four bits and adding to it the 16-bit effective address