Microelectronics Lab ELCT706 IC Design Lab Session #1
IC Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
1. VLSI Circuit Design Flow
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
System Requirements
Functional (Architecture) Design and Verification
Logic Design and Verification
Circuit Design and Verification
Physical Design and Layout Verification
Mask Generation
Silicon Processing and Wafer Testing
1. VLSI Circuit Design Flow- FA Example
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
1. System Requirements Full Adder: 3 inputs (A,B,Ci) & 2 outputs (S, Co) S = A xor B xor Ci Co= AB + ACi + BCi
2. Functional/Architecture Design Example
3. FA Logic Design Example
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
4. FA Circuit Design Example
1. VLSI Circuit Design Flow- FA Example
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
5. FA Layout Design Example
1. VLSI Circuit Design Flow- FA Example
2. CMOS Combinational Logic Circuits
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
CMOS Inverter CMOS NOR Gate CMOS NAND Gate
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- Layout Representation = Output of Physical Design Step - Physical Design: Translation of circuit schematics
into Silicon Form - Layout Design: Generating Layout masks needed
for the Fabrication and the Silicon processing. - Layout Design Rules = Common language between VLSI designers and process engineers - Stick Diagram: Initial Step needed for planning
the layout and routing of the circuit
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- Stick Diagram: - Initial Step needed for planning the layout
and routing the circuit. - Translate the layer information of the circuit
using the following sample color code Polysilicon (Gate) Active (n+, p+)
Metal 1
n+ n+ w
L
p+ p+
NMOS PMOS
Active contact
CMOS Combinational Logic Circuits Stick Diagrams CMOS Inverter
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
CMOS Combinational Logic Circuits Stick Diagrams CMOS NOR Gate
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
CMOS Combinational Logic Circuits Stick Diagrams CMOS NAND Gate
3. CMOS Circuits Layout
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- Stick Diagram: Planning for Layout - Layout: Applying the Design Rules on the
planned Stick Diagrams - Design Rules: reflect limit of a process. They
describe minimum width, minimum distance, overlap. - Micron Rules - Lambda Rules
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
CMOS Composite Layout
Layout Layers: Active Pselect Nselect Nwell Poly Active Contact Poly Contact Metal 1 Metal 2 Via
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- MOSIS Design Rules
Active Layer Rules
Rule Value
Minimum width 3λ
Min. Spacing Active –Active 3λ
Min. Spacing Active – P/Nselect 2λ
Min. Spacing Active – well 6λ
Min. Source/Drain Width 3λ
Active Overlap on Active Contact 1.5λ
Min. Spacing Active – Poly Contact 3λ
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- MOSIS Design Rules
Poly Layer Rules
Rule Value
Minimum width 2λ
Min. Spacing Poly –Poly 3λ
Min. extension outside of Active 2λ
Min. Source/Drain Width 3λ
Poly Overlap on Poly Contact 1.5λ
Min. Spacing Poly – Active Contact 3λ
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- MOSIS Design Rules
Layer Minimum width Minimum spacing**
Well 12λ 12λ
P/Nselect 3λ 3λ
Metal 1 3λ 3λ
Metal 2 3λ 4λ
** Minimum Spacing for layer x refers to minimum spacing between 2 similar layers of type x. Example: minimum spacing of Poly Layer = 2λ refers to minimum spacing between any 2 poly layers.
3. CMOS Circuits Layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- MOSIS Design Rules
Contact Rules
Rule Value
Active Contact Exact Size 2λ × 2λ
Poly Contact Exact Size 2λ × 2λ
Metal Overlap on Active/Poly contact 1λ
Via Rules
Rule Value
Via Exact Size 2λ × 2λ
Metal 1 Overlap on via 1λ
Metal 2 Overlap on via 1λ