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Microkernels and L4
Introduction
COMP9242 2006/S2 Week 1
cse/UNSW/NICTA
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WHY MICROKERNELS?
MONOLITHIC KERNEL
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WHY MICROKERNELS?
MONOLITHIC KERNEL:
• Kernel has access to everything
Ü all optimisations possibleÜ all techniques/mechanisms/concepts
implementable
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WHY MICROKERNELS?
MONOLITHIC KERNEL:
• Kernel has access to everything
Ü all optimisations possibleÜ all techniques/mechanisms/concepts
implementable
• Can be extended by simplyadding code
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WHY MICROKERNELS?
MONOLITHIC KERNEL:
• Kernel has access to everything
Ü all optimisations possibleÜ all techniques/mechanisms/concepts
implementable
• Can be extended by simplyadding code
• Cost: Complexity
Ü growing sizeÜ limited maintainability
cse/UNSW/NICTA COMP9242 2006/S2 W1 P1
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MICROKERNEL: IDEA
• Small kernel providing core functionality
Ü only code running in privileged mode
• Most OS services provided by user-level servers
• Applications communicate with servers via message-passing IPC
UNIXServer Driver
Device FileServer
usermode
modekernel
syscall
VFS
IPC, file system
Scheduler, virtual memory
Device drivers, Dispatcher, ... IPC, virtual memory
Application
Application
IPC
Hardware Hardware
cse/UNSW/NICTA COMP9242 2006/S2 W1 P2
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
Application
System: traditionalembedded
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
Application
System: traditionalembedded
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
Application
System: traditionalembedded
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
TCB: all code 100,000’s loc 10,000’s loc
cse/UNSW/NICTA COMP9242 2006/S2 W1 P3
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
Ü dramatic reduction of amount of privileged codeÜ modularisation with hardware-enforced interfacesÜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
Ü policies defined at user level, easy to changeÜ additional services provided by adding servers
• Hardware abstraction
Ü hardware-dependent part of system is small, easy to optimise
• Security, safety
Ü internal protection boundaries
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
Ü dramatic reduction of amount of privileged codeÜ modularisation with hardware-enforced interfacesÜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
Ü policies defined at user level, easy to changeÜ additional services provided by adding servers
• Hardware abstraction
Ü hardware-dependent part of system is small, easy to optimise
• Security, safety
Ü internal protection boundaries
REALITY CHECK!
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
Ü dramatic reduction of amount of privileged codeÜ modularisation with hardware-enforced interfacesÜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
Ü policies defined at user level, easy to changeÜ additional services provided by adding servers
• Hardware abstraction
Ü hardware-dependent part of system is small, easy to optimise
• Security, safety
Ü internal protection boundaries
REALITY CHECK!
slow, inflexible
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
Ü dramatic reduction of amount of privileged codeÜ modularisation with hardware-enforced interfacesÜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
Ü policies defined at user level, easy to changeÜ additional services provided by adding servers
• Hardware abstraction
Ü hardware-dependent part of system is small, easy to optimise
• Security, safety
Ü internal protection boundaries
REALITY CHECK!
slow, inflexible
100µsec IPC
cse/UNSW/NICTA COMP9242 2006/S2 W1 P4
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IPC COSTS
• First-generation microkernels
Ü Mach, Chorus, Amoeba
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IPC COSTS
• First-generation microkernels
Ü Mach, Chorus, Amoeba
... were slow...
Ü 100µs IPCÜ almost independent of clock speed!
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IPC COSTS
• First-generation microkernels
Ü Mach, Chorus, Amoeba
... were slow...
Ü 100µs IPCÜ almost independent of clock speed!
• L4 does better
Ü close to hardware costÜ 20 times faster than Mach
on identical hardware
cse/UNSW/NICTA COMP9242 2006/S2 W1 P5
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IPC COST IMPLICATIONS
cse/UNSW/NICTA COMP9242 2006/S2 W1 P6
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L4 IPC
cse/UNSW/NICTA COMP9242 2006/S2 W1 P7
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MICROKERNEL PERFORMANCE
FIRST-GENERATION MICROKERNELS WERE SLOW
• Reasons: Poor design [Liedtke SOSP 95]
Ü complex APIÜ too many featuresÜ poor design and implementation
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MICROKERNEL PERFORMANCE
FIRST-GENERATION MICROKERNELS WERE SLOW
• Reasons: Poor design [Liedtke SOSP 95]
Ü complex APIÜ too many featuresÜ poor design and implementationÜ large cache footprint ⇒ memory bandwidth limited
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MICROKERNEL PERFORMANCE
FIRST-GENERATION MICROKERNELS WERE SLOW
• Reasons: Poor design [Liedtke SOSP 95]
Ü complex APIÜ too many featuresÜ poor design and implementationÜ large cache footprint ⇒ memory bandwidth limited
• L4 is fast due to small cache footprint
Ü 10–14 I-cache linesÜ 8 D-cache linesÜ small cache footprint ⇒ CPU limited
cse/UNSW/NICTA COMP9242 2006/S2 W1 P8
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
Ü minimality: no unnecessary featuresÜ orthogonality: complementary featuresÜ well-designed, and well implemented from scratch!
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
Ü minimality: no unnecessary featuresÜ orthogonality: complementary featuresÜ well-designed, and well implemented from scratch!
• Kernel provides mechanisms, not services
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
Ü minimality: no unnecessary featuresÜ orthogonality: complementary featuresÜ well-designed, and well implemented from scratch!
• Kernel provides mechanisms, not services
• Design principle (minimality):
A feature is only allowed in the kernel if this is required for theimplementation of a secure system.
cse/UNSW/NICTA COMP9242 2006/S2 W1 P9
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L4 HISTORY
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L4 HISTORY
• Original version by Jochen Liedtke (GMD) ≈ 93–95
Ü “Version 2” APIÜ i486 assemblerÜ IPC 20 times faster than Mach [SOSP 93, 95]
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L4 HISTORY
• Original version by Jochen Liedtke (GMD) ≈ 93–95
Ü “Version 2” APIÜ i486 assemblerÜ IPC 20 times faster than Mach [SOSP 93, 95]
• Other L4 V2 implementations:
Ü L4/MIPS64: assembler + C (UNSW) 95–97Ü fastest kernel on single-issue CPU (100 cycles)
Ü L4/Alpha: PAL + C (Dresden/UNSW), 95–97Ü first released SMP version
Ü Fiasco (Pentium): C++ (Dresden), 97–99
cse/UNSW/NICTA COMP9242 2006/S2 W1 P10
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L4 HISTORY
• Experimental “Version X” API
Ü improved hardware abstractionÜ various experimental features (performance, security, generality)Ü portability experiments
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L4 HISTORY
• Experimental “Version X” API
Ü improved hardware abstractionÜ various experimental features (performance, security, generality)Ü portability experiments
• Implementations
Ü Pentium: assembler, Liedtke (IBM), 97-98Ü Hazelnut (Pentium+ARM), C, Liedtke et al (Karlsruhe), 98–99
cse/UNSW/NICTA COMP9242 2006/S2 W1 P11
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L4 HISTORY
• “Version 4” (X.2) API, 02
Ü portability, API improvements
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L4 HISTORY
• “Version 4” (X.2) API, 02
Ü portability, API improvements
• L4Ka::Pistachio, C++ (plus assembler “fast path”)
Ü x86, PPC-32, Itanium (Karlsruhe), 02–03Ü fastest ever kernel (36 cycles, NICTA/UNSW)
Ü MIPS64, Alpha (NICTA/UNSW) 03Ü same performance as V2 kernel (100 cycles single issue)
Ü ARM, PPC-64 (NICTA/UNSW), x86-64 (Karlsruhe), 03-04Ü UltraSPARC (NICTA/UNSW), 04–??
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L4 HISTORY
• “Version 4” (X.2) API, 02
Ü portability, API improvements
• L4Ka::Pistachio, C++ (plus assembler “fast path”)
Ü x86, PPC-32, Itanium (Karlsruhe), 02–03Ü fastest ever kernel (36 cycles, NICTA/UNSW)
Ü MIPS64, Alpha (NICTA/UNSW) 03Ü same performance as V2 kernel (100 cycles single issue)
Ü ARM, PPC-64 (NICTA/UNSW), x86-64 (Karlsruhe), 03-04Ü UltraSPARC (NICTA/UNSW), 04–??
• Portable kernel:
Ü ≈ 3 person months for core functionalityÜ 6–12 person months for full functionality & optimisation
cse/UNSW/NICTA COMP9242 2006/S2 W1 P12
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L4 HISTORY
• NICTA L4-embedded (Nx) API, 05–
Ü transitional API (pre-seL4)Ü de-featured (timeouts, “long” IPC, recursive mappings)Ü reduced memory footprint for embedded systems
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L4 HISTORY
• NICTA L4-embedded (Nx) API, 05–
Ü transitional API (pre-seL4)Ü de-featured (timeouts, “long” IPC, recursive mappings)Ü reduced memory footprint for embedded systems
• NICTA::Pistachio-embedded, derived from L4KA::Pistachio
Ü ARM9/ARM11, x86, MIPSÜ PPC 405, Blackfin under development
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L4 HISTORY
• NICTA L4-embedded (Nx) API, 05–
Ü transitional API (pre-seL4)Ü de-featured (timeouts, “long” IPC, recursive mappings)Ü reduced memory footprint for embedded systems
• NICTA::Pistachio-embedded, derived from L4KA::Pistachio
Ü ARM9/ARM11, x86, MIPSÜ PPC 405, Blackfin under development
• You’ll be using the (unreleased) N2 API implementation
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L4 PRESENT
• NICTA L4-embedded commercially deployed
Ü adopted by Qualcomm for CDMA chipsetsÜ under evaluation/development for other products at a number of multinationalsÜ about to establish strong presence in wireless and CE markets
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L4 PRESENT
• NICTA L4-embedded commercially deployed
Ü adopted by Qualcomm for CDMA chipsetsÜ under evaluation/development for other products at a number of multinationalsÜ about to establish strong presence in wireless and CE markets
• NICTA spinning out Open Kernel Labs
Ü further development of L4-embeddedÜ professional services for L4 usersÜ commercialisation of present NICTA microkernel research
cse/UNSW/NICTA COMP9242 2006/S2 W1 P14
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L4 FUTURE
• Security API: NICTA seL4
Ü draft published March 06Ü semi-formal specification in HaskellÜ “executable spec”: Haskell implementation plus ISA simulatorÜ used for exercising and porting appsÜ stable API August 06Ü C implementation end of 06Ü similar project at TU Dresden: L4sec (draft API Oct 05)
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L4 FUTURE
• Security API: NICTA seL4
Ü draft published March 06Ü semi-formal specification in HaskellÜ “executable spec”: Haskell implementation plus ISA simulatorÜ used for exercising and porting appsÜ stable API August 06Ü C implementation end of 06Ü similar project at TU Dresden: L4sec (draft API Oct 05)
• Features:
Ü user-level management of kernel resources (esp. memory)Ü low-overhead information-flow control mechanismsÜ suitable for formal verification
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L4 FUTURE
• Security API: NICTA seL4
Ü draft published March 06Ü semi-formal specification in HaskellÜ “executable spec”: Haskell implementation plus ISA simulatorÜ used for exercising and porting appsÜ stable API August 06Ü C implementation end of 06Ü similar project at TU Dresden: L4sec (draft API Oct 05)
• Features:
Ü user-level management of kernel resources (esp. memory)Ü low-overhead information-flow control mechanismsÜ suitable for formal verification
• Formal verification of L4 implementation: L4.verified project
Ü mathematical proof that implementation matches spec
cse/UNSW/NICTA COMP9242 2006/S2 W1 P15
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PISTACHIO: SIZE
• Source code:
Ü ≈ 10k loc architecture independentÜ ≈ 0.5–2k loc architecture specific
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PISTACHIO: SIZE
• Source code:
Ü ≈ 10k loc architecture independentÜ ≈ 0.5–2k loc architecture specific
• Memory footprint kernel (no attempt to minimise yet):
Ü using gcc (poor code density on RISC/EPIC architectures)
Architecture Version Text Totalx86 L4Ka 52k 98kItanium L4Ka 173k 417kARM NICTA 55k 117kPPC-32 L4Ka 41k 135kPPC-64 L4Ka 60k 205kMIPS-64 L4Ka 61k 100k
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PISTACHIO: SIZE
• Source code:
Ü ≈ 10k loc architecture independentÜ ≈ 0.5–2k loc architecture specific
• Memory footprint kernel (no attempt to minimise yet):
Ü using gcc (poor code density on RISC/EPIC architectures)
Architecture Version Text Totalx86 L4Ka 52k 98kItanium L4Ka 173k 417kARM NICTA 55k 117kPPC-32 L4Ka 41k 135kPPC-64 L4Ka 60k 205kMIPS-64 L4Ka 61k 100k
• Fast IPC cache footprint (typical):
Ü 10–14 I-cache linesÜ 8 D-cache lines
cse/UNSW/NICTA COMP9242 2006/S2 W1 P16
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SIZE COMPARISON
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PISTACHIO PERFORMANCE: IPC
port/ C++ optimisedArchitecture optimisation intra AS inter AS intra AS inter ASPentium-3 UKa 180 367 113 305
Small Spaces UKa 213Pentium-4 UKa 385 983 196 416Itanium 2 UKa/NICTA 508 508 36 36
cross CPU UKa 7419 7410 N/A N/AMIPS64 NICTA/UNSW 276 276 109 109
cross CPU NICTA/UNSW 3238 3238 690 690PowerPC-64 NICTA/UNSW 330 518 200‡ 200‡
Alpha 21264 NICTA/UNSW 440 642 ≈70† ≈70†
ARM/XScale NICTA/UNSW 340 340 151 151
† “Version 2” assembler kernel‡ Guestimate!
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L4 ABSTRACTIONS AND MECHANISMS
THREE BASIC ABSTRACTIONS:
• Address spaces
• Threads
• Time (second-class abstraction in N2 API, to vanish completely)
TWO BASIC MECHANISMS:
• Inter-process communication (IPC)
• Mapping
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L4 ABSTRACTIONS: ADDRESS SPACES
• Address space is unit of protection
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L4 ABSTRACTIONS: ADDRESS SPACES
• Address space is unit of protection
Ü initially emptyÜ populated by mapping in frames
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L4 ABSTRACTIONS: ADDRESS SPACES
• Address space is unit of protection
Ü initially emptyÜ populated by mapping in frames
• Mapping performed by privileged MapControl() syscall
Ü can only be called from root taskÜ also used for revoking mappings (unmap operation)
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L4 ABSTRACTIONS: ADDRESS SPACES
• Address space is unit of protection
Ü initially emptyÜ populated by mapping in frames
• Mapping performed by privileged MapControl() syscall
Ü can only be called from root taskÜ also used for revoking mappings (unmap operation)
• Root task
Ü initial address space created at boot timeÜ controls system resourcesÜ non-delegatable privilege (shortcoming of N2 API)
cse/UNSW/NICTA COMP9242 2006/S2 W1 P20
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L4 ABSTRACTIONS: THREADS
• Thread is unit of execution
Ü kernel-scheduled
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L4 ABSTRACTIONS: THREADS
• Thread is unit of execution
Ü kernel-scheduled
• Thread is addressable unit for IPC
Ü thread-ID is unique identifier
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L4 ABSTRACTIONS: THREADS
• Thread is unit of execution
Ü kernel-scheduled
• Thread is addressable unit for IPC
Ü thread-ID is unique identifier
• Threads managed by user-level servers
Ü creation, destruction, association with address space
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L4 ABSTRACTIONS: THREADS
• Thread is unit of execution
Ü kernel-scheduled
• Thread is addressable unit for IPC
Ü thread-ID is unique identifier
• Threads managed by user-level servers
Ü creation, destruction, association with address space
• Thread attributes:
Ü scheduling parameters (time slice, priority)Ü unique IDÜ address spaceÜ page-fault and exception handler
cse/UNSW/NICTA COMP9242 2006/S2 W1 P21
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L4 ABSTRACTIONS: TIME
• Used for scheduling time slices
Ü thread has fixed-length time slice for preemptionÜ time slices allocated from (finite or infinite) time quantum
Ü notification when exceeded
• In earlier L4 versions also used for IPC timeouts
Ü removed in N2
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L4 MECHANISM: IPC
• Synchronous message-passing operation
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L4 MECHANISM: IPC
• Synchronous message-passing operation
• Data copied directly from sender to receiver
Ü short messages passed in registers
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L4 MECHANISM: IPC
• Synchronous message-passing operation
• Data copied directly from sender to receiver
Ü short messages passed in registers
• Can be blocking or polling (fail if partner not ready)
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L4 MECHANISM: IPC
• Synchronous message-passing operation
• Data copied directly from sender to receiver
Ü short messages passed in registers
• Can be blocking or polling (fail if partner not ready)
• Asynchronous notification variant
Ü no data transfer, only sets notification bit in receiverÜ receiver can wait (block) or poll
cse/UNSW/NICTA COMP9242 2006/S2 W1 P23
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L4 CONCEPTS: ROOT TASK
• First task started at boot time
• Can perform privileged system calls
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L4 CONCEPTS: ROOT TASK
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
Ü threadsÜ address spacesÜ physical memory
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L4 CONCEPTS: ROOT TASK
Physical Memory
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
Ü threadsÜ address spacesÜ physical memory
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L4 CONCEPTS: ROOT TASK
Physical Memory
Root Task
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
Ü threadsÜ address spacesÜ physical memory
cse/UNSW/NICTA COMP9242 2006/S2 W1 P24
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L4 CONCEPTS: ROOT TASK
Physical Memory
Root Task
DriverDriver
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
Ü threadsÜ address spacesÜ physical memory
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L4 CONCEPTS: ROOT TASK
Physical Memory
Root Task
DriverDriver
Server Server
ServerServer
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
Ü threadsÜ address spacesÜ physical memory
cse/UNSW/NICTA COMP9242 2006/S2 W1 P24
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L4 CONCEPTS: ROOT TASK
Physical Memory
Root Task
DriverDriver
Server Server
ServerServer
Client Client
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
Ü threadsÜ address spacesÜ physical memory
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L4 EXCEPTION HANDLING
• Interrupts
• Page faults
• Other exceptions
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L4 EXCEPTION HANDLING
• Interrupts
Ü modelled as hardware “thread” sending messagesÜ received by registered (user-level) interrupt-handler threadÜ interrupt acknowledged when handler blocks on receiveÜ timer interrupt handled in-kernel
• Page faults
• Other exceptions
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L4 EXCEPTION HANDLING
• Interrupts
Ü modelled as hardware “thread” sending messagesÜ received by registered (user-level) interrupt-handler threadÜ interrupt acknowledged when handler blocks on receiveÜ timer interrupt handled in-kernel
• Page faults
Ü kernel fakes IPC message from faulting thread to its pagerÜ pager requests root task to set up a mappingÜ pager replies to faulting client, message intercepted by kernel
• Other exceptions
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L4 EXCEPTION HANDLING
• Interrupts
Ü modelled as hardware “thread” sending messagesÜ received by registered (user-level) interrupt-handler threadÜ interrupt acknowledged when handler blocks on receiveÜ timer interrupt handled in-kernel
• Page faults
Ü kernel fakes IPC message from faulting thread to its pagerÜ pager requests root task to set up a mappingÜ pager replies to faulting client, message intercepted by kernel
• Other exceptions
Ü kernel fakes IPC message from exceptor thread to its exception handlerÜ exception handler may reply with message specifying new IP, SPÜ can be signal handler, emulation code, stub for IPCing to server, ...
cse/UNSW/NICTA COMP9242 2006/S2 W1 P25
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FEATURES NOT IN KERNEL
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FEATURES NOT IN KERNEL
• System services (file system, network stack, ...)
Ü implemented by user-level servers
• VM management
Ü performed by (hierarchy) of user-level pagers
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FEATURES NOT IN KERNEL
• System services (file system, network stack, ...)
Ü implemented by user-level servers
• VM management
Ü performed by (hierarchy) of user-level pagers
• Device drivers
Ü user-level threads registered for interrupt IPCÜ map device registers
cse/UNSW/NICTA COMP9242 2006/S2 W1 P26