Network based System on Chip
Performed by: Medvedev Alexey
Supervisor: Walter Isaschar (Zigmond)
Winter-Spring 2006
Problem to solve
• In modern high-speed systems that contain a lot of components traffic is a major problem.
• Components are interacting with each other using a bus.
Problem
BUS
I/O ETC…CACHE
CPU FPU MEM
Problem
• This architecture has certain disadvantages: low speed, allows to connect only two components at a given
time, no parallel access, unconfigurable.
Solution
Solution• On-chip packet-switched networks have been
proposed as a solution for the problem of global interconnect in deep sub-micron VLSI Systems on Chip (SoC).
• Networks on Chip (NoC) can address and contain major physical issues such as parallelization, noise, configurability (traffic control), speed optimization
Project overview
• Implementation of a Network-on-Chip and NoC router featuring:
- service levels
- virtual channels
- flow control unit
NoC Router
CrossbarCrossbar
Buffers
CrossbarControllerCrossbarController
Input PortInput Port Input PortInput Port
Output PortOutput Port Output PortOutput Port
Router
• Central NoC unit for directing data streams and traffic control.
• 2 input ports
• 2 output ports
• 2 service levels per each port
Router schematic
Input port
• Receives data from another router or module.
• Consists of control unit and CRT (Current Routing Table) and a buffer for each service level
Input port schematic
Output port
• Transmits data to another router or module.
• Consists of control unit and NBS (Number of Buffer Slots) controller for each service level
Output port schematic
Crossbar
• Performs data routing between input and output ports in a router.
• Implemented using steering logic.
Crossbar schematic
Crossbar controller
• Directs data streams in the crossbar.
• Uses port selector and address resolver to determine data stream direction.
Crossbar controller schematic
First semester goal
• Implement a 2x2 router that supports [two] service levels and build a simple NoC to allow data transfers between 2 modules
Project ScheduleWeek 1: Get familiar with the Virtex II pro FPGA Week 2: Get familiar with the PowerPC 405
processorWeek 3-4: Studying the VHDL programming
language. Week 5: Get familiar with the FPGA design
process.Week 6: Studying the EDK software for
developing SoC
Week 7: Writing a simple application.Week 8-9: Developing NoC protocol.Week 10-12: Implementing a simple
router for NoC that allows data transfer to other routers.
Week 13-14: Implementing a basic NoC featuring two routers (no wormholes or virtual channels).
Project Schedule
Project Schedule (second semester)
• Implementing a Source Flow Control Unit
• Implementing a Hot-Spot Flow Control Unit (Scheduler) for bandwidth - consuming components.
• Evaluating Space-Cost efficiency of the design
The End