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A Two Stage and Three Stage CMOS OPAMP with Fast

Settling, High DC Gain and Low Power Designed in 180nm

Technology

Anshu Gupta Electronic and Instrumentation Deptt.

SGSITS, Indore

Indore, India

E-mail:[email protected]

U.B.S. Chandrawat SVCE, Indore

Email-id: [email protected]

D.K. Mishra, R. Khatri Electronic and Instrumentation Deptt.

SGSITS, Indore

Indore, India

E-mail: [email protected], [email protected]

Preet Jain SVITS, Indore

Abstract−Two Stage Opamp : An analog to digital converter

(ADC) uses switched capacitor stages that settle in two steps.

The first step of settling places charge onto the load

capacitance using charge pumps, and the second fulfills the

settling requirements using negative feedback. The key factor

is to establish the optimum combination of gm2/gm1 & Cl/Cc.

So, required accuracy & settling time can be established with

minimum power consumption. An experimental prototype

fabricated in a 0.18um CMOS UMC tech. using cadence

requires power consumption of 50 W for Cload=5pf. Typical

measured results are 75 dB gain, UGB of 16 MHz, 80ns

settling time, PM 60 deg, SR is +6/-6V/us, CMRR is 90dB .The

chip active area is about 45 m X 35 m.

Three stage CMOS opamp: The three stage CMOS opamp

with NMC technique is also designed. Simulated results are

DC Gain of 90dB, Unity Gain frequency 30MHz, Power

consumption 300 W, Settling Time 150 ns with Cload 1pf. In

this paper a novel time domain design methodology for three

stage NMC amplifiers was proposed.

Keywords- Fast settling; High gainbandwidth; low voltage;

multi-stage amplifier; frequency compensation; power

consumption.

I. INTRODUCTION

The rapid increase in chip complexity which has occurred

over the past few years has created the need to implement

complete analog-digital subsystems on the same integrated

circuit using the same technology. For this reason

implementation of analog functions in MOS technology has

become increasingly important, and great strides have been

made in recent years in implementing functions such as

highspeed DAC’s ,sampled data analog filters, voltage

references, instrumentation amplifiers, and so forth in

CMOS technology. The Two-stage CMOS opamp design

procedure suitable for pencil and paper analysis is given by

Palmisano, Palumbo and Pennisi (2001).This procedure is

allowed to use the limited range of compensation capacitor

(Cc>>Cgs6). Here Cc is the compensation capacitor and

Cgs6 parasitic capacitor of MOSFET in opamp second

stage. Mahattanakul and Chutichatuporn (2005) have

improved the design procedure that allows a wider range of

Cc which provides a higher degree of freedom in the trade

off between noise and power consumption. Design

procedure for programmable opamp is reported in literature

with noise power balancing (Bronskowski and Schroeder

2007). Pugliese, Cappuccino and Cocurullo (2008)

proposed a design procedure for settling time minimization

in multistage opamps with low power high accuracy.

Design procedures reported in literature have not given

much attention to settling time parameter of opamp. In this

work for the given constraints of speed, power, noise and

load, relationship between Cc and Cgs6 has been

established. Relationship between Cc and Cgs6 has been

used to find out optimum way of implementing the miller

compensation. Two stages refer to the number of gain

stages in the opamp. The first gain stage is a differential

input single ended output stage. The second gain stage is

normally a common source gain stage that has an active

load. Since opamps are designed to be operated with

negative-feedback connection, frequency compensation is

necessary for closed loop stability. The simplest frequency

compensation technique employs the miller effect by

connecting a compensation capacitor Cc across the high-

gain stage.

Fig 1. Block diagram two stage CMOS opamp

Opamp consists of one or more differential stages and

usually followed by additional gain stages depending upon

the requirements. The paper consists of understanding of

specifications and circuit topology of opamp. Design

448978-1-4244-7818-7/10/$26.00 c©2010 IEEE

procedures along with one example of opamp design using

UMC 0.18 um technology with single bias supply 1.8V is

also given. Amplifier slew-rate limiting can impose an

additional lower bound on the power consumption of

switched capacitor circuits. The proper choice of circuit

topology can improve the ratio of load to static currents for

an opamp. The load capacitance cannot decrease due to

thermal (kT/C) noise restrictions, and reducing the output

voltage swing by a fraction, results in an increase in load

capacitance by to maintain the same kT/C noise

performance. The proposed opamp maximizes this ratio by

sourcing and sinking arbitrarily large load currents while

using minimal or zero static current.

Three stage CMOS opamp: This paper presents a new time

domain design procedure for CMOS three stage amplifiers

with nested miller compensation. A conventional three

stage amplifier consists of three transconductance stages

gm1-gm3. Multistage amplifiers are widely used in the

analog and mixed signal circuits to achieve high dc gain and

large output signal swing simultaneously. Therefore, a

frequency compensation technique is needed to design

stable three-stage amplifiers. Nested Miller compensation

(NMC) is one of the well known techniques which are

suitable for three stage amplifiers. In this technique, two Cc

are used. The first capacitor is connected between the first

and third stages and the other capacitor is connected

between the second and third stages. The concept of this

technique is the pole splitting. So, a higher phase margin is

achieved, however, this solution results in the bandwidth

and SR reduction.

Fig 2: Structure of the three-stage NMC amplifier

The trend of low-voltage design is an unjustified fact in

today's circuit design world, and the demand of low voltage

cascade amplifiers in analog systems is increasing. As will

be shown in the paper, in low power CMOS design, the

stability of the NMC amplifier is deteriorated by a right

half- plane (RHP) zero. Moreover, as an amplifier with

three gain stages can generally provide sufficient DC

voltage gain (-90dB) with a good compromise on the power

consumption, the discussion in this paper is focused on

three-stage NMC amplifiers. The gain bandwidth product

(GBW) is reduced when an additional gain stage is added.

As will be shown in this paper, the published stability

criteria are not suitable for low-power CMOS design.

The phase margin (PM), slew rate (SR), settling time

(Ts) and power supply rejection ratio (PSRR) are not

optimized for low-power applications.

II. CIRCUIT CONFIGURATION

The schematic diagram of two stage CMOS opamp is

shown in fig 3. It comprised differential gain stage, second

gain stage and bias string. Examining the subsections

further will provide valuable insight into the operation of

this circuit.

Biasing string: Biasing circuit is made up of M5, M8, M10

and M11 transistors of P-type. It is used to provide

reference voltage to the differential amplifier. The biasing

Fig 3. Schematic diagram of two stage CMOS opamp

of the operational amplifier is achieved with only four

transistors. Transistors M5 and M8 form a simple current

mirror bias string that supplies a voltage between the gate

and source of M5 and M6. Transistors M5 and M6 source a

certain amount of current based difference of the two input

signals at the output. It comprises M1, M2 transistors of P-

type. Current mirror is used to provide constant current to

the branches of differential amplifier.

Common source amplifier: The purpose of the second

gain stage, as the name implies, is to provide additional gain

in the amplifier. Consisting of transistors M6 and M7, this

stage takes on their gate to source voltage which is

controlled by the bias string. M10 and M11 are diode

connected to ensure they operate in the saturation region.

Differential gain stage: Source coupled pair form the

differential amplifier which gives the output from the drain

of M2 and amplifies it through M6 which is in the standard

common source configuration.

Compensation circuit: It comprises NMOS transistor M9

and compensation capacitor Cc, used to ensure the stability

of the two stage CMOS operational amplifier.

III. DESIGN TECHNIQUES

The first aspect considered in the design was the

specifications to be met. Based on a clear understanding of

the specs, the circuit topology of the standard CMOS

operational amplifier was chosen.

TABLE 1. SPECIFICATION OF THE TWO-STAGE

parameters Results achieved

Supply voltages +1.8V/-1.8V

Unity gain bandwidth 16 MHz

Power consumption 50μw

Settling time(ns) 70ns

2010 International Conference on Computer Information Systems and Industrial Management Applications (CISIM) 449

Gain(dB) 75dB

Phase margin 60 deg

Slew Rate +6/6 V/μs

CMRR 90 dB

Dynamic input range +1/1 V

Load capacitance 5pF

A .Procedure

The schematic of the opamp is given in fig. 3. We adopted a

common procedure to design the opamp. On the basis of

above analysis and discussion design steps for two stage

opamp can be given as:

Step1: As per the discussions in value of driving voltage (

is to be set.

Step2: For the given constraints of settling time and

accuracy, required SR and u can be found out by using

equations

Step3: Constraint of noise sets the value of from

equation

Step4: By using equation calculate the value of

compensation Capacitor

Step5: Output swing requirement will set the upper limit

for the driving voltage of second stage ( as per the

discussions, can be set up at a value as high as

possible.

Step6: For the given constraint of power consumption

calculate the transconductance of second stage

from equation

Step7: Calculate from equation

Step8: On the basis of calculated value of

either or

relationship can

be used to calculate compensation resistance.

Step9: Compatibility of the given capacitive load with

derived circuit parameters can be verified.

Step10: By using calculated values of and

transistors ( aspect ratio can

be found out by using basic opamp relationship

Step11: Current through first and second stage

can be found out by using basic opamp equation

Step12: Driving voltage of M5 transistor can be calculated

by using the relationship

Common set so will be in deep saturation.

Step13: Aspect ratio for Transistors can be

found out from the design steps

B. Summary of proposed design steps.

Step1:

Step2:

Common set so will be in deep

saturation

Step3

Step4:

Step5:

Step6:

Step7:

Step8:

Step9:

TABLE 2. SPECIFICATION OF THE THREE-STAGE

parameters Results to be achieved

450 2010 International Conference on Computer Information Systems and Industrial Management Applications (CISIM)


Unity gain bandwidth 33 MHz

Power consumption 300 μw

Settling time(ns) 150 ns

Gain(dB) 90 dB

Phase margin 55 deg

SR +25/-25 V/μs

CMRR 110 dB


Dynamic Input Range 1/-1V

IV. NESTED MILLER

COMPENSATION

In this section CMOS design will be illustrated by a three-

stage NMC amplifier. The gain stages are having voltage

gain Av (1-3). The capacitors Cm1 and Cm2 are the

compensation capacitors, and CL is the loading capacitor. A

circuit diagram realizing the NMC amplifier is depicted in

Fig. 4.

Fig 4. Circuit diagram of the three-stage NMC Amplifier

The first, second and third gain stage are implemented by

M101-MI09, M201- M204 and M301-M302, respectively.

For the structure of the NMC amplifier, by solving the

circuit network without losing accuracy, the small-signal

voltage gain transfer function is calculated

as

Where is the DC gain of the

amplifier, and I s the5

dominated pole; and are the

transconductance and output resistance of the gain stages,

respectively. From (I), it shows that there are three poles

and two zeros. If the amplifier has High output current

capability, gm3 is large and the zeros which are located at

high frequencies can be neglected. The Stability of the

amplifier have third order Butter-worth frequency response

in unity-feedback configuration. The gain-bandwidth

product and phase margin are therefore given by

Applying these equations the position of the non-dominated

complex pole pair P2, 3 are given by

The above stability criteria are based on the assumption

that gm3 is much larger than gm1 and gm2. Nevertheless,

gm3 is comparable to gm1 and gm2 in low power CMOS

amplifiers, and the stability criteria stated are no longer

valid. Moreover, as gm3 is not large, the zeros cannot be

neglected. From the numerator a RHP zero and a left half

Fig 5. Schematic diagram of three stage CMOS opamp

-half-plane (LHP) zero are present. Since the s term is

negative, the RHP zero locates at a lower frequency than the

LHP zero and the effect of the RHP zero dominates. The

phase margin is decreased by the RHP zero and the stability

of the NMC amplifier is reduced.

The slew rate of the NMC amplifier is given by

Where Im1, Im2, Im3 are the maximum current of the first,

second and third gain stage to charge the capacitors. The

slew rate of the amplifier is poor as the values of the

compensation capacitors used in NMC are large, and it

takes a long time to charge or discharge them to the desired

voltage. Since the settling time of the amplifier consists of

the slewing and quasi-linear period, the Settling behavior of

the NMC amplifier is also degraded.


. V. SIMULATION RESULTS

The simulation results show that this op-amp performed to

within specs for all the specified parameters. For the

process p/m shown in table3,design p/m of opamp in table 4

and simulation results in table 5 are designed from the

proposed procedure for Cc=0.4pf

TABLE 3. PROCESS PARAMETER OF 0.18 μm

Process

parameters

NMOS PMOS

μ(cm2/v.s) 3.141 X 10

2 1.145 X 10

2

Tox (m) 4.2 X 10-9

4.2 X 10-9

Vt (V) 3.075 X 10-1

-4.55 X 10-1

TABLE 4. DESIGN PARAMETER OF TWO STAGE CMOS OPAMP

Aspect ratio Proposed Unit

Cc 0.4 Pf

(W/L)1,2 (1.08/0.36) μm/ μm

(W/L)3,4 (0.27/0.54) μm/ μm

(W/L)5,8 (0.36/0.36) μm/ μm

(W/L)6 (3.7/0.36) μm/ μm

(W/L)7 (3.9/0.54) μm/ μm

(W/L)9 (0.24/3.33) μm/ μm

(W/L)10,11 (0.32/0.54) μm/ μm

TABLE 5. SIMULATION RESULT OF TWO STAGES


Layout area(μm^2) 45 μm X 35 μm


Unity gain bandwidth 15.77 MHz

Power consumption 32.53 μw

Settling time(ns) 96.57 ns

Gain(dB) 70.98 dB

Phase margin 58 deg

3-db bandwidth 5.41KHz

SR +5.53/-8.17 V/μs

dynamic input range +1/-1 V


CMRR 81.09dB

Figure 6.AC response of two stage opamp

Figure 7. Settling time of two stage opamp

Figure 8. Input noise response of two stage opamp

Figure 9. Output noise response of two stage opamp

Figure 10. Offset voltages of two stage opamp

Figure 11.Frequency responses of the three stage opamp using NMC

452 2010 International Conference on Computer Information Systems and Industrial Management Applications (CISIM)

Figure 12. Common mode gain of 3 stage opamp

TABLE 6. SIMULATION RESULT OF TWO STAGE


Layout area(μm^2) 65 μm X 65 μm


Unity gain bandwidth 30.19 MHz

Power consumption 272.79 μw

Settling time(ns) 166.4 ns

Gain(dB) 81.32 dB

Phase margin 50.68 deg

3-db bandwidth 5.41KHz

SR +20.4/-28.54 V/μs

dynamic input range +1/-1 V


CMRR 100.42dB

Input referred noise 20 nV/Hz

Figure 13. .Layout of two stage CMOS opamp

Figure 14. av extracted view of two stage opamp

Figure 15. Layout of three stage opamp

VI. LAYOUT

In Cadence tool we used virtuoso Layout Editor. It is also

important to Extracted netlist underlying the layout view,

for two main purposes of the circuit. The layout area of this

two stage opamp die is 45 m X 35 m and layout area of

three stage is 65 m X 65 m.

VII. CONCLUSION

In this paper, we have presented the design of a fast settling,

low power OPAMP with a high DC gain. The fast settling

of the two stage CMOS opamp with DC gain of 70.98 dB,

Ts is 96.57 ns, UGB is 15.77 MHz with Cload of 5pf.

Simulation shows a power consumption of 32.53 W, layout

has been also made with die area of 45 m X 35 m. A novel

frequency compensation technique NMC which eliminates

the RHP zero in an NMC amplifier has been presented and

proved by experimental results after simulation results DC

Gain of 81.32dB, Unity Gain frequency 30.19MHz, Power

consumption 272.7 W, Settling Time 166.4 ns with Cload

1pf. In this paper a novel time domain design methodology

for three stage NMC amplifiers was proposed. In future we

can develop new current mirrors and third stage of opamp

so limitations of given procedure can be overcome.

ACKNOWLEDGEMENT

This work has been carried out in SMDP VLSI laboratory

of the Electronics and Instrumentation department of Shri

G. S. Institute of Technology and Science, Indore, India.

The author is thankful to the ministry for facilities provided

and also thankful to Dr. D. K. Mishra for guiding me.

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