Paper Report
Presenter: Jyun-Yan Li
Systematic Software-Based Self-Testfor Pipelined Processors
Mihalis Psarakis Dimitris Gizopoulos Miltiadis Hatzimihail Dept. of Informatics, University of Piraeus, GreeceAntonis Paschalis Dept. of Informatics & Telecomm., University of Athens, GreeceAnand Raghunathan Srivaths Ravi NEC Laboratories America, Princeton, NJ, USADAC2006, July24-28,2006, San Francisco, California, USA.
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Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor.
In this paper, we analyze the challenges involved in testing an important component of modem processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs.
Abstract
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We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15% (12% on average) for the entire processor, and fault coverage improvements of 22% for the pipeline logic, compared to a conventional SBST approach.
Abstract (cont.)
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Related work
Generate test pattern for
functional behavior[2,3,4]
testability[12]
This paper
Systematic testability analysis of pipelined logic
Function components self-
test routines for ISA and RTL
Component-oriented SBST
[8]
Advance SBST[9,10]
Testing for complex RISC
Random or pseudorandom
instruction sequence
No hazard dection & data
forwarding
miniMIPS & OpenRISC 1200
[14,15]
No provide fault coverage for
entire processor
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Testability Logic carrying address-related information
。Pipelined register of address information is used by other components 。 ex: bus controller, program counter, exception unit
Hazard detection and forwarding。 input data is from forwarding unit rather than from source register
What is the Problem
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Partition SBST program into multiple code segment and divide virtual memory into some regions
Load code segment into region in virtual memory
Mapping virtual memory to instruction memory
Address-related
0, m/r-1, 2m/r-1
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Address-related observability
Path1 : PC and IF fault propagated to address bus through bus controller Path2 : ID and EX fault
Path3 : use link instruction occur in the ID and EXPath4 : use exception occur in the EX and MEM
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Processor has n stages Ia: result at p stage, store at s stage Ib: read at d stage, actually need at f stage
Lemma 1 If s-d < c , no hazard , c:distance between two
instruction If s-d ≥ c , hazard
。If p-f ≥ c , unresolved。If p-f < c , can resolved
Hazard detection and forwarding
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Proposal MethodFunctional SBST
code
Identification of def-use pairs
Generation of test code variants
loop unrolling
Modification of the SBST code
Insertion of jump instructions
Address faults propagation
Enhanced SBST code
Partition of SBST program
Pipeline description
Memory and cache parameters
Phase 1
Phase 2
forwarding
Address-related
Enhanced code
Data dependency &
loop
1. N stage2. Each stage function3. Forwarding path
All possible dependencies between instructions
1. Virtual memory size2. Physical memory size3. Program size
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miniMIPS: 100MHz and 32817 gates OpenRSIC: 102MHz and 35657 gates Improve 22% for pipeline
Experimental results
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Fault coverage improve 12% on an average for entire processor
Experimental results (cont.)
Without multiplier
Original With
multiplier
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This paper present an enhance SBST methodology for pipelined processor Address-related component Hazard detection and forwarding mechanism
Conclusion
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Using lemma 1 to verify forwarding unit for different processor
It not describe how to loop unrolling and select code variants clearly
My comment
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Generating and combining code variants
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Selection of code variants