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Project Overview
The objective of this project is to capture images using a camera mounted on a
vehicle and RF link to a distant display for viewing. The schematic for the project is
shown in Figure 1.
Figure 1. Schematic for the Senior Design Project.
From the schematic, a camera would be mounted on a battery driven car. The image
signal captured by the camera will then be fed to a MPEG module and compressed. The
signal is then fed to D/A converters at around 15 Mbps. The DACs will be used to
convert the digital signal to analog so it can be transported over an RF link. The DACs
will provide I and Q signals that will be QAM encoded. The coded signal will then be
transported over a 2.4GHz RF link. The signal then goes through the QAM decoding
which will provide I and Q inputs for the ADCs. The processed signal will then be
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converted back to digital using ADCs, so it can be displayed over the user’s screen at the
controlling station.
QAM Group Overview
The QAM group’s responsibility begins with the D/A converter that receives the
compressed digital signal. The two areas that the QAM group is responsible for are:
• D/A conversion of the incoming digital signal and the subsequent QAM encoding
of the analog signal so that it can be transmitted on the RF link
• QAM decoding of the signal received from the RF link and the subsequent A/D
conversion of the I and Q signals received as a result of QAM decoding
QAM Group Objectives
We have identified several objectives for our project. We realize that many of
these objectives may not be feasible in one semester. However, the listing of these
objectives will simplify the task for any group that chooses to pursue this project in future
semesters. In the “Results” section, we will list the goals that we have accomplished this
semester, and make recommendations to any design group that follows us. The long-
term objectives for our project are:
• Researching D/A and A/D chips that meet the required specifications
• Ordering the above chips
• Understanding the theory behind how these chips work
• Obtaining evaluation boards to test the chips and designing additional evaluation
boards to test chips for which evaluation boards could not be obtained.
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• Testing the chips to ensure that they perform according to requirements
• Designing simple circuits that incorporate the A/D and D/A chips using
information obtained from the tests done with the evaluation boards. Possible re-
engineering of the circuits used in the evaluation board. Testing these circuits
• Understanding the theory behind QAM modulation
• Designing circuits to facilitate QAM modulation and demodulation. Testing these
circuits.
• Integrating the D/A and QAM modulation circuit onto one board with the RF
transmission circuit. Combining the RF receiving circuit, QAM demodulation
circuit, and A/D circuit onto another board.
Theory
A/D Conversion
Analog-to-digital conversion is the process of converting a continuous analog
signal into a sampled digital signal. The process begins with sampling, or measuring the
amplitude of the analog waveform at equally spaced discrete instants of time. When you
sample the wave with an analog-to-digital converter you have control over 2 variables.
The first is the sampling rate. The rate controls how many samples are taken per second.
The fact that samples of a continually varying wave may be used to represent that wave
relies on the assumption that the wave is constrained in its rate of variation. Because a
communications signal is actually a complex wave--essentially the sum of a number of
component sine waves, all of which have their own precise amplitudes and phases--the
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rate of variation of the complex wave can be measured by the frequencies of oscillation
of all its components.
The second variable is the sampling precision. The precision controls how many
different gradations (quantization levels) are possible when taking the sample. In order
for a sampled signal to be stored or transmitted in digital form, each sampled amplitude
must be converted to one of a finite number of possible values, or levels. For ease in
conversion to binary form, the number of levels is usually a power of 2--that is, 8, 16, 32,
64, 128, 256, and so on, depending on the degree of precision required. The input to the
quantizer is a sequence of sampled amplitudes for which there are an infinite number of
possible values. The output of the quantizer, on the other hand, must be restricted to a
finite number of levels. The degree of inaccuracy depends on the number of output levels
used by the quantizer. More quantization levels increase the accuracy of the
representation, but they also increase the storage capacity or transmission speed required.
In the next step in the digitization process, the output of the quantizer is mapped into a
binary sequence. An encoding table that might be used to generate the binary sequence is
shown below:
It is apparent that 8 levels require three binary digits, or bits; 16 levels require four bits;
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and 256 levels require eight bits. In general 2n levels require n bits. Although the
accuracy required determines the number of quantization levels used, the resultant binary
sequence must still be transmitted within the bandwidth tolerance allowed.
D/A Conversion
The Digital to Analog conversion process is opposite of the A/D process. In this
process the sampled digital signal having a few defined levels or states is simply decoded
and converted back to analog signal having a theoretically infinite number of states or
levels. The higher the sampling rate and precision of the signal, the more accurate analog
signal would be produced or higher fidelity will be achieved. Figure 2 shows an example
for A/D and D/A conversion.
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Figure 2. The steps in A-to-D and D-to-A conversion.
QAM Modulation:
We can’t simply transmit our digital video data through the air to a video screen.
We must first convert our information from a digital format to an analog format. Once
we have done this, we will be able to send the desired information. There are two basic
ways of converting our data. We may use Phase Shift Keying or Amplitude Modulation.
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The graph below has a signal with an amplitude of 1. We could let a signal with this
amplitude represent a binary 0.
A signal with an amplitude of 2 might be used to represent a binary 1 as shown below.
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Using our convention of 1 and 0, we could interpret the signal above to be the binary
word “0011”. This is amplitude modulation. Phase Shift Keying (PSK) involves
shifting the period of a wave so that a binary word can be represented. Notice that the
two signals below are out of phase by ¼ wavelength.
We could use a shift in phase to represent a binary word. This is the basis of Phase Shift
Keying. We could use the convention as follows in Table 1 below.
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Table 1. Example PSK TableBinary Word Phase Shift00 001 ¼10 ½11 ¾
Thus, given the Signal below we can obtain a binary word. PSK works in the manner
that the phase shift is measured from the wave preceding the wave in question. Thus, the
binary words for the wave below would be 00, 00, 10, 00.
Quadrature Amplitude Modulation or QAM is just the combination of Phase Shift Keying
and Amplitude Modulation. Quadrature Amplitude Modulation involves varying the
Amplitude and Phase of the carrier wave in order to generate combinations (or
constellations) of symbols. The equation of the carrier wave is:
x(t) and y(t) represent the inphase (I) and quadrature (Q) axis respectively. This clearly shows that
the amplitude of the signal varies with time as bits are modulated onto it. It is also apparent that the
phase also changes with time. For example, in 8-bit QAM there are 4 levels of phase changes and
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two levels of amplitudes. This allows for 8 combinations of 3 bits each. This means in 1 cycle we
can transmit 3 bits to represent the 8 states. Table 2 shows how each of the 8 bit patterns is given a
different signal.
Table 2. 8 bit QAM tableBit value Amplitude Phase shift
000 1 None
001 2 None
010 1 ¼
011 2 ¼
100 1 ½
101 2 ½
110 1 ¾
111 2 ¾
This can also be shown on a phasor diagram. This phasor diagram is referred to as a
constellation:
8 bit QAM constellation
The 8 states are spread apart from each other. They are 90 degrees apart, with half having
amplitude of 1, the other half having an amplitude of 2. Each shift in phase of each wave
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is shifted relative to the wave before it. Since each cycle of the carrier wave can transmit
3 bits, this scheme is said to have a baud rate of 3. Thus, if we were to have the signal
below, we could derive the corresponding binary words.
Other QAM schemes with higher baud rates such as 16 QAM, 32 QAM, 64 QAM, 256
QAM also exist. These involve more divisions of both phase and Amplitude. A problem
with having a large number of levels of amplitude is that it may introduce errors as one
level of amplitude may (due to the effect of noise) be confused with a higher level, thus
distorting the signal. In order to avoid this, it is necessary to allow for wide margins.
Doing this means increasing the available amplitude range, which can increase the
amount of power required for modulation. The other QAM Schemes are explained
below.
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4QAM
This is exactly the same as QPSK, this is because there are 2 levels per dimension. So the
phasor diagram will be a square of 4 states the same as QPSK.
16QAM
This example has 16 possible states. It gets 16 states by using 12 different phases, and 3
different amplitudes of modulation. The figure below is a phasor diagram showing these
16 states.
16 Bit QAM Constellation
This diagram has 4 levels per dimension. This means there are 4 I and 4 Q values.
Since 2^4 = 16, there are 4 bits to represent each state. So now the bit rate has increased
to 4 bits per cycle. 16 QAM is also represented as 4 baud.
32QAM
Another variation is 32QAM. This obviously has 32 states, 32 is chosen because it is
another power of 2 and it is close to a square number. But 32 is not a square number, the
closest square number is 36. This means there will be 6 I and 6 Q values. To get to the
correct number of states (32) the 4 corner states are ignored, this is an advantage because
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these corner states have the largest magnitude and therefore use up the most power to
modulate. The bit rate of 32QAM is 5 bits per cycle. This is shown in the constellation
phasor diagram below.
32 Bit QAM Constellation
Notice that the states are becoming closer together. This can make it difficult to
distinguish between adjacent states, therefore errors are found.
256QAM
Another widely used QAM is 256QAM. This has 256 states, because 256 is both a square
number and a power of 2 no states are ignored. This means it has 16 'I' and 16 'Q'
levels, and since 2^8 = 256 it takes 8 bits to represent a symbol. So the bit rate of
256QAM is 8 bits per cycle. This is a very efficient form of digital modulation.
256QAM is the current practical limitation. However, work is underway to extend to
limits to 512 and 1024QAM. This extension comes at a cost.
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Research and Design Process: Steps Followed
Obtaining Specifications:
After talking to Dr. Brooke, the required specifications for the converters were
obtained and are shown below in Table 3.
Table 3. Required Specifications for theDesired A/D and D/A Converters
MSPSBit Resolution
Power Consumption# of Converters
InterfaceSettling Time
>408-12
<200mW2
Parallel<7µs
The required specifications were determined to handle large data transfers quickly
with minimum power consumption. A rate of 40 MSPS and 8 to 12 bits resolution will
be capable of transferring the large amounts of data coming from the camera. Power
consumption under 200mW is required since the eventual design will run on batteries.
Parallel interfacing, dual converters and a settling time less than 7µs will also allow for
quicker transfer times.
Researching Chips:
The group’s first task was to purchase appropriate DACs and ADCs along with
the respective evaluation boards if they were available. The most important criterion was
to order DACs and ADCs that had similar specifications. After doing extensive research
on the Internet to find chips that not only matched our specifications, but were also
available to order, we identified the chips that we planned to purchase. Table 4, shown
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below, shows the various converters that were purchased with the manufacturer
specifications.
Table 4. Purchased A/D and D/A Converters with Specifications.
The first four converters that start with AD for the part number come from Analog
Devices and the rest come from Intersil. From the Table above, it can be seen that
various D/A and A/D converters were purchased with a wide range of specifications. All
eight converters had the required specifications for the number of converters, the type of
interface, and the number of bits. As for the number of MSPS, the AD9201 was the only
converter chosen with a value less than 40 MSPS. This part was still chosen with the
hope that the increase in the number of bits will compensate for the lower sampling rate.
The HI5662, HI5762, and the AD9059 power consumption levels are rather high. This is
due to the higher value of 5V for the supply voltage rather than 3V. A lower value for
the maximum power consumption will be possible with a lower supply voltage. These
values will be determined during the testing phase for our project. The settling time was
Part # Type MSPS # of Bits # ofConverters
Max PowerConsumption Interface Settling
TimeAD9288-40 DA 40 8 2 189mW Parallel N/A
AD9761 DA 40 10 2 250mW Parallel 35ns
AD9201 AD 20 10 2 245mW Parallel N/A
AD9059 AD 60 8 2 505mW Parallel 14.2ns
HI1177 DA 40 8 2 160mW Parallel 10ns
HI5628 DA 60 8 2 170mW Parallel 5ns
HI5662 AD 60 10 2 670mW Parallel 11.7ns
HI5762 AD 60 10 2 650mW Parallel 11.7ns
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not as important as the rest of the specs. The settling times for the AD9288-40 and the
AD9201 were not available from the data sheets produced by the manufacturer.
Therefore, these values will have to be determined in the testing phase if deemed
necessary. The value of 35ns for the AD9761 is rather high, but it was still selected
because it meets all the other required specifications. One other specification not listed
above is pre-existing I and Q channels for QAM modulation and demodulation. The
HI5628 was chosen because it’s the only D/A converter with a sampling rate of 60 MSPS
that matches the sampling rate of the HI5662 and the HI5762 A/D converters.
Cost Analysis, Ordering Chips, and Evaluation Boards:
Prior to ordering the chips, an evaluation of the cost effectiveness of the chips was
done. The cost of the D/A and A/D converters ranged from $6.49 to $43.15. The cost for
each converter is shown below in Table 5.
Table 5. Cost Analysis.Part # Cost ($)
AD9288-40 8.89
AD9761 14.34
AD9201 8.98
AD9059 43.15
HI1177 6.49
HI5628 13.43
HI5662 21.98
HI5762 28.43
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The converters with 10-bit resolution cost more than the converters with 8-bit
resolution. This was true for all the converters except the AD9059. This converter was
extremely expensive. This might be a direct result of price inflation due to limited
quantities available by the manufacturer. The AD9201 was close in price to the
converters with 8-bit resolution. This might be due to the fact that it has a lower
sampling rate than the rest of the 10-bit converters. As for price versus power
consumption, it would seem that the more you pay the more efficient the converter would
be. That’s not the case for the converters that were found. The AD9059, HI5662, and
the HI5762 all had the highest power consumption and cost. This goes against logic
because it seems that it would require more design time to create an efficient converter.
After determining that the above-mentioned chips met all our criteria (technical
specifications, cost, and power), we proceeded to put in orders for them. Evaluation
boards were not available for the Analog Devices parts, but they were available for the
Intersil chips. Hence, we put in orders for all the chips and evaluation boards for only the
Intersil chips based on availability. A major stumbling block that the group encountered
at this stage of the project was the arrival of the parts after their order was put in. Some
parts took a couple of weeks to arrive, while some parts haven’t come in yet in spite of us
repeatedly contacting the supplier. Table 6. shows the parts and whether they have
arrived or not. The third column shows the chips that we have evaluation boards for.
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Table 6. Order SummaryPart # Arrived Evaluation Board
AD9288-40 N NAD9761 N YAD9201 Y NAD9059 Y NHI1177 Y NHI5628 Y YHI5662 N NHI5762 N N
None of the evaluation boards that we ordered arrived within a reasonable time.
The group selected AD9201 and AD9761 for evaluation purposes. The AD9201 is an
A/D converter while the AD9761 is a D/A converter. These chips were picked because
their specifications exactly matched each other. However, evaluation boards for the
above chips were not available. We then proceeded to contact the college representatives
of Analog Devices, and explained our situation to them. We requested sample evaluation
boards and were sent an evaluation board for AD9761, but we still could not obtain an
evaluation board for AD 9201. Considering the shortage of time that we were faced with,
the group decided to focus on the D/A part of the project. After we obtained a sample
evaluation board for AD9761, the group was subdivided into two parts. One half of the
group worked on testing AD9761, while the other half worked on designing a board that
could be used to test AD9761. This division was done to help the group hbetter achieve
its goals in the limited time left in the semester. The idea behind designing a board to test
the AD9761 was that this simplified circuit could be combined with the QAM encoding
circuit and the RF transmission circuit on one board at a later stage of the project. The
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following two sections describe AD9201 and AD9761, the chips that we selected to
evaluate.
9201 A/D Converter
The input signal is converted to digital format by an A/D chip. Figure 3, shown
below, shows the block diagram of an A/D chip.
Figure 3. Block diagram of a dual 10-bit ADC.
The AD9201 is a complete dual channel, 20 MSPS, 10-bit CMOS ADC. The
AD9201 is optimized specifically for applications where close matching between two
ADCs is required (e.g., I/Q channels in communications applications). The 20 MHz
sampling rate and wide input bandwidth will cover both narrow-band and spread-
spectrum channels. The AD9201 integrates two 10-bit, 20 MSPS ADCs; two input buffer
amplifiers, an internal voltage reference and multiplexed digital output buffers. Each
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ADC incorporates a simultaneous sampling sample-and-hold amplifier at its input. The
analog inputs are buffered; no external input buffer op amp would be required in most
applications. The ADCs are implemented using a multistage pipeline architecture that
offers accurate performance and guarantees no missing codes. The outputs of the ADCs
are ported to a multiplexed digital output buffer. The AD9201 is manufactured on an
advanced low cost CMOS process, operates from a single supply from 2.7V to 5.5V, and
consumes 215mW of power (on 3 V supply). The AD9201 input structure accepts either
single-ended or differential signals, providing excellent dynamic performance up to and
beyond its 10 MHz Nyquist input frequencies.
9761 D/A Converter
Figure 4, shown below, shows the block diagram of a 10-bit dual parallel DAC
chip.
Figure 4. A 10-bit dual parallel DAC
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The AD9761 is a complete dual channel, high speed, 10-bit CMOS DAC. The
AD9761 has been developed specifically for use in wide bandwidth communication
applications (e.g., spread spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS DACs, dual 2x
interpolation filters, a voltage reference, and digital input interface circuitry. The
AD9761 supports a 20 MSPS per channel input data rate that is then interpolated by 2x
up to 40 MSPS before simultaneously updating each DAC. The interleaved I and Q input
data stream is presented to the digital interface circuitry, which consists of I and Q latches
as well as some additional control logic. The data is de-interleaved back into its original
I and Q data. An on-chip state machine ensures the proper pairing of I and Q data. A 2x
digital interpolation filter that eases the reconstruction filter requirements then processes
the data output from each latch. The interpolated output of each filter serves as the input
of their respective 10-bit DAC. The DACs utilize segmented current source architecture
combined with a proprietary switching technique to reduce glitch energy and to maximize
dynamic accuracy. Each DAC provides differential current output thus supporting
single-ended or differential applications. Both DACs are simultaneously up-dated and
provide a nominal full-scale current of 10mA. Also, the full-scale currents between each
DAC are matched to within 0.07dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry. The AD9761 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 2.7V to 5.5V and consumes 200mW of
power.
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Evaluation Board Testing:
The AD9761 DAC was tested using the sample evaluation board that we had
obtained. The evaluation board that we had ordered for the HI5628 – an Intersil D/A
converter, finally arrived. Therefore, we decide to also test the HI5628. The testing
procedure proved to be no walk in the park. We were simultaneously attempting to test
two D/A evaluation boards. There were three main reasons for the testing process. The
first was to familiarize the group with the chips and with basics of D/A conversion. Next,
it was necessary to determine which components on the evaluation boards were necessary
for us to put on our completed board. The third reason was to ensure that the chips
functioned according to required specifications.
The test setup for our evaluation boards consisted mainly of three components.
The first was a data generator that provided the digital input signal to our DAC, a DC
power supply to provide power to the chip, and an oscilloscope to analyze the analog
output. We utilized the DC power supply and the oscilloscope available in the electronic
circuits laboratory. To generate the digital data necessary to input to our D/A converter
we used the Sony Tektronix DG2020A Data Generator in combination with the Sony
Tektronix P3420 Pod Module. The main purpose of the DG2020A is for use in testing
and evaluating semiconductors and logic circuits. Figure 5 shows a picture of our setup
in the lab.
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Figure 5. Picture of the setup used to test HI5628
The most complicated part of the testing process was figuring out how to make
use of the data generator. After a tedious learning process we were able to use the data
generator efficiently enough to test our chip. Three pod modules may be connected to the
data generator simultaneously and each pod has 12 digital outputs on it providing a total
of 36 possible digital signals from the data generator. To successfully test each chip we
utilized 9 of these channels. Eight of them were used as digital inputs and one was
configured as the clock input. When deciding what type of signal to input we figured that
a binary counter was best because it corresponds to an easily identifiable step ramp at the
analog output of the chip. The output of the data generator was configured so that a level
of 4 volts was a digital “1” and a level 0 volts was a digital “0”. The power supply was
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set to provide an AVDD and a DVDD of 4 volts. To analyze the analog output from the chip
we connected the “IOUT” from the evaluation board to an oscilloscope. We configured the
digital input so that the least significant bit and the clock had a frequency of 25 MHz.
Figue 6., shown below, represents the output we obtained on the oscilloscope with the 8-
bit binary counter input.
Figure 6. Output of the HI5628 DAC with 25 MHz clock
This output does not look like a step ramp but we must remember that an 8-bit
binary counter counts up to 28 or from 0 to 255. Therefore if we are to zoom into the
graph we can see the individual steps. This is illustrated here.
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Figure 7. Output of the HI5628 zoomed in to show steps
Evaluation Board Design:
The AD9761 sample evaluation board from Analog Devices had some extra
hardware, like filters and transformers, so we decided to design our own board for the
Digital to Analog conversion of the signal for transmission from the car to the base
station. The board was designed using SuperPCB. This allowed for the board to be
manufactured here on campus.
The original schematic of the evaluation board is included in the QAM group
notebook. Since the chip being used is very small and we could not purchase a PAD for
it, the dimensions needed for the PAD were figured out. The notes and calculations for
exact dimensions of the PAD constructed for the chip are included in the notebook
submitted with this project report. Thus our first step in designing the board was to make
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a PAD with correct dimensions that the chip would fit in. The next step was figuring out
what circuitry was needed to make the digital to analog circuit work.
The group experimented with the evaluation board and also studied the schematic
provided by Analog Devices to figure out which parts were necessary to make the project
work. We consulted Dr. Brooke and some graduate students to better understand how the
evaluation board worked. For example, there were certain filters and resistor packs, on
the evaluation board that were not needed for this project. We also found out the biasing
of the various pins that would give us the correct output at the required frequency.
The next step in creating the evaluation board was to create it using the software
SuperPCB. The finished design can been seen below in Figure 8.
Figure 8. SuperPCB schematic for AD9761
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The design was first made on paper to weed out the extra hardware and to make
the circuit simpler to draw on SuperPCB. Due to manufacturing constraints we were
restricted to using just the top layer to complete the circuitry. This caused a lot of
problems because no paths could intersect another. Thus there are multiple ports on the
board for the same connection like an AC Ground, or an AC voltage source. After the
board is manufactured, a separate proto-board or another printed circuit board may be
used to provide a single wire to bias all the pins.
The input to the circuit board is provided with either BNC or SMA connectors. A
ground plane is needed for these connectors, which could not be designed by the group
due to the shortness of time. But since the connections for ground are provided for the
separate pins, the ground pin of the input connectors can be joined to these pins or a
separate board can be used for the same purpose. The same is true for some of the other
input signals like the clock and the select. The clock input and the write input have been
tied together in this design. While designing the board it was kept in mind that the space
needed for each connector would range form one inch to half an inch.
The other components needed for the design to work are capacitors and resistors.
Spacing has been left on the design for surface mount capacitors and resistors and their
respective values have been noted. Once the board has been manufactured the desired
components need to be soldered on to the printed circuit board. After the required
biasing has been done the output of the circuit can be obtained through the two output
ports IA and QA. Depending on the value of the Select, the output will either be on IA
(if select is high) or on QA (if select is low).
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Results and Recommendations:
The QAM group has achieved the following results:
• Researched and purchased D/A and A/D chips that met the required specifications
• Obtained evaluation boards for two D/A chips: AD 9761 and HI5628
• Tested AD9761 and HI5628 and verified that they met specifications
• Designed an evaluation board for AD9761
• Understood the theory behind A/D conversion, D/A conversion, and QAM
modulation
Owing to the shortage of time, our group succeeded in achieving many, but not all of the
objectives that we had set out to achieve. In order to simplify the task for any group that
chooses to pursue this project in future semesters, we have put together a notebook that
contains all our research and design information. We have included an electronic copy of
the PCB design of the AD9761. Here are our recommendations to the next group that
tackles this problem:
• Build and test the simplified circuit for the AD9761 using our design
• Obtain an evaluation board for the A/D converter that matches AD9761, i.e. AD
9201, from Analog Devices when this board is available. If this board remains
unavailable, contact the college representatives from Analog Devices and request
a sample.
• Design a simplified A/D conversion circuit that incorporates the AD9201
• Design QAM encoding and decoding circuits
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• Co-ordinate with the RF group to ensure that the QAM encoded signal can be
transmitted. Integrate the D/A circuit, QAM encoding circuit, and the RF
transmission circuit on one board
• Co-ordinate with the Display Group to make sure the output of the A/D signal can
be displayed. Integrate the A/D circuit, QAM decoding circuit, and the RF
receiving circuit on one board