2.54 ±0.2
8-0.6
2.5 MIN
0.50.5
0.5
14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12 2-R1.6
0.28
254-C1.2
Type nameLot No.
QRCode
24±0
.5
9.5±
0.5
5.5±
0.5
(1)
TERMINAL CODE
1. (VNC)2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC *10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN16. VNC *17. NC18. N19. N20. N21. W22. V23. U24. P25. NC
29.2
±0.5
14.4
±0.5
14.4
±0.5
(3.5
)
(3.3
)
HEAT SINK SIDE
0.4
0.4
1.5 ±0.05
3.5
B
0.8
(2.656)
(2.756)
(0~
5°)
(1.2)
(1.2
)
DETAIL A DETAIL B
0.28
1.778 ±0.2
35 ±0.3
20×1.778(=35.56)
38 ±0.5
17 1
A
16-0.5
0.51.5 MIN
PS21997-4INTEGRATED POWER FUNCTIONS
600V/30A low-loss CSTBT inverter bridge for threephase DC-to-AC power conversion
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES (PS21997-4)
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For P-side : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.• For N-side : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).• Fault signaling : Corresponding to a SC fault (N-side IGBT), a UV fault (N-side supply).• Input interface : 3~5V line (High Active).• UL Recognized : Yellow Card No. E80276
Dimensions in mm
*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside andleave another one open.
Sep. 2008
Note : CSTBT is registered trademark of MITSUBISHI ELECTRIC CORPORATION in Japan.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
2
Fig. 2 LONG TERMINAL TYPE PACKAGE OUTLINES (PS21997-4A)
Fig. 3 ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21997-4C)
2.54 ±0.28-0.6
2.5 MIN14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12 2-R1.6
0.2825
4-C1.2
Type nameLot No.
QRCode
24±0
.5
14±0
.5
5.5±
0.5
(1)
TERMINAL CODE
1. (VNC)2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC * 10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN16. VNC *17. NC18. N19. N20. N21. W22. V23. U24. P25. NC
29.4
±0.5
14.4
±0.5
14.4
±0.5
(3.5
)
(3.3
)
HEAT SINK SIDE
0.4
0.4
1.5 ±0.05
3.5
B
0.8
(2.656)
(2.756)
(0~
5°)
(1.2)(1
.2)
DETAIL A DETAIL B
0.28
1.778 ±0.2
35 ±0.3
20×1.778(=35.56)
38 ±0.5
17 1
A
16-0.5
1.5 MIN
0.50.50.50.5
2.54 ±0.2
8-0.6
14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12 2-R1.6
0.28
254-C1.2
Type nameLot No.
QRCode
24±0
.5
9.5±
0.5
5.5±
0.5
(1)
TERMINAL CODE
1. (VNC)2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC * 10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN16. VNC *17. NC18. N19. N20. N21. W22. V23. U24. P25. NC
29.2
±0.5
33.7
±0.5 14
.4±0
.5
18.9
±0.5
14.4
±0.5
(3.5
)
HEAT SINK SIDE
0.4
0.4
1.5 ±0.05
3.5B
0.8
DETAIL B
0.281.778 ±0.2
35 ±0.3
20×1.778(=35.56)
38 ±0.5
17 1
A
0.4
0.51.5 MIN
(0~
5°)
(0~
5°)
16-0.5
0.5
0.5 (2.656)
(2.756)
(1.2)
(1.2
)
DETAIL A
Dimensions in mm
Dimensions in mm
*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside andleave another one open.
*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside andleave another one open.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
3
2.54 ±0.25
7-0.6
2.5 MIN14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12(1
.8)
2-R1.6
0.28
254-C1.2
Type nameLot No.
QRCode
24±0
.5
11±0
.5
5.5±
0.5
(1)
TERMINAL CODE
1. (VNC)2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC *10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN16. VNC *17. NC18. N19. (N)20. N21. W22. V23. U24. P25. NC
35.2
±0.6
29.2
±0.5
14.4
±0.5
14.4
±0.5
17.4
±0.5
17.4
±0.5
(3.5
)
HEAT SINK SIDE
0.4
1.5 ±0.05
3.5
B
0.80.4
0.4
(2.656)
(2.756)(0
~5°
)
(1.2)(1
.2)
DETAIL A DETAIL B
0.28
1.778 ±0.25
35 ±0.3
20×1.778(=35.56)
38 ±0.5
17 1
A
16-0.5
0.4
1.5 MIN
(0~
5°)
0.50.5
0.5
M
C1 : Electrolytic type with good temperature and frequency characteristics. The capacitance also depends on the PWM control strategy of the application system.
C2 : 0.22µ-2µF ceramic capacitor with good temperature, frequency and DC bias characteristics.
D1 : Bootstrap diode (VRRM=600V or more. trr=100ns or less)D2 : Zener diode (24V/1W)
Z : Surge absorberC : AC filter(ceramic capacitor 2.2n -6.5nF)
(Common-mode noise filter)
UV lockoutcircuit
Drive circuit
AC line input
Input signalconditioning
Input signalconditioning
Input signalconditioning
Level shift
Drive circuit
Level shift
Drive circuit
Level shift
Drive circuit
Input signal conditioning Protectioncircuit (SC) UV lockout
circuit
FO
DIPIPM
Inrush limiting circuit
VD
C1C2D2
VNC
P-side IGBTS
N-side IGBTS
WVU
C2C1D2D1
P
VNC
N1 N
CIN
Z C
P-side input (PWM)
(15V line)
AC output
FO output (5V line)N-side input (PWM)
Fo logic
Fig. 5 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
Fig. 4 BOTH SIDES ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21997-4W) Dimensions in mm
*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside andleave another one open.
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
4
V
V
V
VmAV
20
20
–0.5~VD+0.5
–0.5~VD+0.51
–0.5~VD+0.5
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-WApplied between UP, VP, WP, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminalApplied between CIN-VNC
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output currentCurrent sensing input voltage
VD
VDB
VIN
VFO
IFO
VSC
450
500
600
30
60
47.6–20~+125
Applied between P-N
Applied between P-N
TC = 25°CTC = 25°C, less than 1msTC = 25°C, per 1 chip
(Note 1)
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
ConditionSymbol Parameter Ratings Unit
Supply voltage
Supply voltage (surge)Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipationJunction temperature
V
V
V
A
A
W°C
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
ConditionSymbol Parameter Ratings Unit
CONTROL (PROTECTION) PART
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIPIPM is 150°C (@ TC ≤ 100°C). However, toensure safe operation of the DIPIPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Drive circuit
Drive circuit
Protection circuit
WVU
B
C
VNC
CIN
A
P
N1 N
C R
Shunt Resistor
External protection circuit
DIPIPM
N-side IGBTS
P-side IGBTSSC Protection
Trip Level
IC (A)
tw (µs)20
Short Circuit Protective Function (SC) :SC protection is achieved by sensing the N-side DC-Bus current (through the externalshunt resistor) after allowing a suitable filtering time (defined by the RC circuit).When the sensed shunt voltage exceeds the SC trip-level, all the N-side IGBTs are turnedOFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it isrecommended to stop the system when the Fo signal is received and check the fault.
Collector currentwaveform
(Note 1)
(Note 2)
Fig. 6 EXTERNAL PART OF THE DIPIPM PROTECTION CIRCUIT
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
5
2.502.602.20
1.90—
0.60
2.651.00
110
2.1
3.0
mA
V
Tj = 25°CTj = 125°C
IC = 30A, Tj = 25°CIC = 30A, Tj = 125°C
VCE(sat)
VEC
ton
trrtc(on)
toff
tc(off)
ICES
ConditionSymbol ParameterLimits
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Rth(j-c)Q
Rth(j-c)F
Min.
THERMAL RESISTANCE
Typ. Max.
—
—
—
—
Unit
Tj = 25°C, –IC = 30A, VIN = 0V
ConditionSymbol ParameterLimits
Min. Typ. Max.———
0.70——————
Unit
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Collector-emitter saturationvoltage
FWDi forward voltage
Junction to case thermalresistance (Note 3)
VD = VDB = 15V
VIN = 5V
Switching times
VCC = 300V, VD = VDB = 15V
IC = 30A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
Collector-emitter cut-offcurrent VCE = VCES
1.902.001.701.300.300.40
1.700.40——
Vµsµsµsµsµs
°C/W
°C/W
Note 3 : Grease with good thermal conductivity and long-term quality should be applied evenly with +100µm~+200µm on the contactingsurface of DIPIPM and heat sink.The contacting thermal resistance between case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity ofthe applied grease.For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and the thermal conductivity is 1.0W/mK.
DIPIPM
IGBT chip position
Power terminals
FWDi chip position
Control terminals
TC point
Heat sink side
11.6mm 3mm
400
–20~+100
–40~+125
1500
VD = 13.5~16.5V, Inverter partTj = 125°C, non-repetitive, less than 2µs
(Note 2)
60Hz, Sinusoidal, 1 minute,Between pins and heat sink plate
VCC(PROT)
TC
Tstg
Viso
Symbol Ratings Unit
Self protection supply voltage limit(short circuit protection capability)Module case operation temperature
Storage temperature
Isolation voltage
V
°C°C
Vrms
TOTAL SYSTEM
Parameter Condition
Note 2: TC measurement point
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
6
CONTROL (PROTECTION) PART
Note 4 : Short circuit protection works only for the N-side. Please select the external shunt resistance such that the SC trip-level is up to 1.7times of the current rating.
5 : Fault signal is asserted only corresponding to a SC or a UV failure at N-side, and the Fo pulse width is different for each failure modes.For SC failure, Fo output is with a fixed width of 40µs(min), but for UV failure, Fo outputs continuously during the whole UV period,however, the minimum Fo pulse width is 40µs(min) for very short UV period less than 40µs.
Symbol
ID
VFOH
VFOL
VSC(ref)
IINUVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Vth(hys)
Parameter ConditionLimits
Unit
VD = VDB = 15VVIN = 5V
VSC = 0V, FO terminal pull-up to 5V by 10kΩVSC = 1V, IFO = 1mAVD = 15V (Note 4)VIN = 5V
Trip levelReset levelTrip levelReset level
(Note 5)
Applied between UP, VP, WP, UN, VN, WN-VNC
————4.9—
0.430.7010.010.510.310.840—0.8
0.35
——————
0.481.00—————2.11.3
0.65
2.800.552.800.55—
0.950.531.5012.012.512.513.0—2.6—
—
Min. Typ. Max.mAmAmAmAVVV
mAVVVVµsVV
V
VD = VDB = 15VVIN = 0V
Tj ≤ 125°C
Circuit current
Fault output voltage
Short circuit trip level
Control supply under-voltageprotection
Fault output pulse widthON threshold voltageOFF threshold voltageON/OFF threshold hysteresisvoltage
Total of VP1-VNC, VN1-VNC
VUFB-U, VVFB-V, VWFB-WTotal of VP1-VNC, VN1-VNC
VUFB-U, VVFB-V, VWFB-W
Input current
Note 7: Flatness measurement position
+ –
+–
Heat sink side
Heat sink side
4.6mm
Measurement position
17.5mm
Mounting screw : M3(Note 6)
ConditionParameterLimits
Mounting torque
WeightHeat-sink flatness
Min.
MECHANICAL CHARACTERISTICS AND RATINGS
Typ. Max.
0.59
—
–50
Unit
—
10—
0.78
—
100
N·m
gµm
Recommended : 0.69 N·m
(Note 7)
Note 6 : Plain washers (ISO 7089~7094) are recommended.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
7
VVV
V/µsµs
kHz
Supply voltageControl supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Applied between P-N
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
For each input signal, TC ≤ 100°CTC ≤ 100°C, Tj ≤ 125°C
40016.518.5
1—20
VCC
VD
VDB
∆VD, ∆VDB
tdead
fPWM
ConditionSymbol ParameterLimits
Min. Typ. Max.
013.513.0–12.0—
Unit
RECOMMENDED OPERATION CONDITIONS
30015.015.0———
Note 8 : The allowable rms current value depends on the actual application conditions.9 : Input signal with on pulse width less than PWIN(on) might make no response.10: Input signal with off pulse width less than PWIN(off) might make no response, or make delayed response to P-side input only.
(The delay is less than about 4µs.)Please refer Fig.7 about delayed response and Fig.11 about N-line inductance.
IO Allowable rms currentVCC = 300V, VD = VDB = 15V,P.F = 0.8, sinusoidal PWM,Tj ≤ 125°C, TC ≤ 100°C (Note 8)
Arms
0.5
1.5
3.0
–5.0
—
—
—
—
—
—
—
5.0
fPWM = 5kHz
fPWM = 15kHz
—
—
—
—
15.0
10.0
Fig. 7 About Delayed Response Against Shorter Input Off Signal Than PWIN(off) (P-side only)
Real line···off pulse widthPWIN(off); turn on time t1Broken line···off pulse widthPWIN(off); turn on time t2
P-side control input
Output current Ic
Internal IGBT gate
t1t2
200V ≤ VCC ≤ 350V,13.5V ≤ VD ≤ 16.5V,13.0V ≤ VDB ≤ 18.5V,-20°C ≤ Tc ≤ 100°C,N-line wiring inductance less than 10nH
(Note 10)
µs
µs
V
Allowable minimum inputpulse width
VNC variation
PWIN(on)
PWIN(off)
VNC
(Note 9)
Between VNC-N (including surge)
Below ratedcurrent
Betweenrated currentand 1.7 timesof ratedcurrent
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
8
Fig. 8 THE DIPIPM INTERNAL CIRCUIT
UOUT
VOUT
UOUT
VVS
WOUT
VWS
VOUT
WOUT
VNO
GND
Fo
WN
VN
UN
VCC
HVIC
LVIC
CIN
CIN
N
W
V
U
P
COM
VUB
VUS
VCC
VVB
VP
VWB
WP
Fo
WN
VN
UN
WP
VP
UP UP
VNC
VN1
VP1
VVFB
VWFB
VNC
VUFB
IGBT1
IGBT2
IGBT3
IGBT4
IGBT5
IGBT6
Di1
Di2
Di3
Di4
Di5
Di6
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
9
Error output Fo
Output current Ic
Control supply voltage VD
Protection circuit state
Control input
b1
b2
b3
b5
RESETRESET
UVDt
UVDr
SET
b6
b4 b7
Protection circuit state
N-side control input
Fault output Fo
Sense voltage of theshunt resistor
Output current Ic
Internal IGBT gate
SC reference voltage
RC circuit time constant delay
a5
a8a4
a3
a1
a2SC
RESETSET
a7a6
Fig. 9 TIMING CHART OF THE PROTECTIVE FUNCTIONS[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation : IGBT ON and carrying current.a2. Short circuit is detected (SC trigger).a3. All N-side IGBTs’ gates are hard interrupted.a4. All N-side IGBTs turn OFF.a5. FO is output (tFO(min) = 40µs).a6. Input “L”.a7. Input “H”. But IGBT is still OFF state during outputting FO.a8. IGBT turns ON when L→H signal is input after FO is reset.
[B] Under-Voltage Protection (N-side, UVD)
b1. Control supply voltage VD rises : After VD level rises over under voltage reset level (UVDr), the circuits start to operate when next inputis applied.
b2. Normal operation : IGBT ON and carrying current.b3. VD level dips to under voltage trip level. (UVDt).b4. All N-side IGBTs turn OFF in spite of control input condition.b5. FO is output. (tFO ≥ 40µs and FO outputs continuously during UV period).b6. VD level rises over UVDr.b7. Normal operation : IGBT ON and carrying current.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
10
MCU
10kΩ
UP,VP,WP,UN,VN,WN
VNC(Logic)
Fo
DIPIPM
5V line
3.3kΩ (min)
Error output Fo
Output current Ic
Control supply voltage VDB
Protection circuit state
Control input
c6
c1
c2 c4
c5c3
RESET
UVDBt
UVDBr
SETRESET
High-level (no fault output)
[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage VDB rises : After VDB level rises over under voltage reset level (UVDBr), the circuits start to operate when nextinput is applied.
c2. Normal operation : IGBT ON and carrying current.c3. VDB level dips to under voltage trip level. (UVDBt).c4. P-side IGBT turns OFF in spite of control input signal level, but there is no FO signal output.c5. VDB level rises over UVDBr.c6. Normal operation : IGBT ON and carrying current.
Fig. 10 AN INSTANCE OF INTERFACE CIRCUIT
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and thewiring impedance of the printed circuit board.Input circuit integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external filtering resistor,pay attention to the turn-on threshold voltage.
Fig. 11 WIRING CONNECTION OF SHUNT RESISTOR
N
DIPIPMWiring inductance should be less than 10nH.
Shunt resistor
Equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100µm, length=17mm
Please connect GND wiring from VNC terminal to the shunt resistor terminal as close as possible.
VNC
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21997-4/-4A/-4C/-4WTRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2008
11
Fig. 12 AN EXAMPLE OF TYPICAL DIPIPM APPLICATION CIRCUIT
15V line
WOUT
VOUT
C3
C2C2 C2C1 C1 C1
UOUT
WP
VWB
VP
VVB
5V line
UP
COM
UOUT
VOUT
WOUT
GND
Fo
WN
VN
VCC
C
B
A
R1
N1
C4
CIN
N
W
V
U
P
VWS
VVS
VUS
VUBVCC
Fo
WN
VN
UNUN
WP
VP
UP
VNC
VNC
VN1
VP1
VUFB VVFB VWFB
C3
MC
U
HVIC
LVIC
Shuntresistor
Long wiring here might cause SClevel fluctuation and malfunction.
Long GND wiring here might generate noise to input and cause IGBT malfunction.
Long wiring here might cause short-circuit. Long wiring here might cause short-circuit.
MM
Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
Note 1 : Input drive is High-active type. There is a 3.3kΩ (Min.) pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring ofeach input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage.
2 : Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.3 : Fo output is open drain type. It should be pulled up to the MCU or control power supply (e.g. 5V, 15V) by a resistor that makes IFo
up to 1mA.4 : To prevent erroneous protection, the wiring of A, B, C should be as short as possible.5 : The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C46 : All capacitors should be mounted as close to the terminals of DIPIPM as possible. (C1: good temperature, frequency characteristic
electrolytic type, and C2, C3 (0.22~2µF) : good temperature, frequency and DC bias characteristic ceramic type are recommended.)7 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.8 : Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND and leave the other open.9 : It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.10 : If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation. It is
recommended to connect control GND and power GND at only a point N1.11 : High voltage (VRRM =600V or more) and fast recovery type (trr=100ns or less) diodes should be used in the bootstrap circuit.