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Radix-4 BoothMultiplier with
Neighborhood
Dependent Approach
for Video Processing
Applications
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Abstract: Neighborhood Dependent Approach (NDA)
High performance low power Radix-4 Booth Multiplierfor kernel based operation
Such as 2-D convolution in video processingapplications
This technology reduces
1. Dynamic power consumption due to reduced switching
2. Special values, such as 0, repeated values orrepeated bit combinations are detected and data pathsare disabled accordingly
3. Input pixels are halved to increase probability ofspecial value detection
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4. Reduces operation and switching activities in 2Dconvolution upto 46% of switch rate
As a result we get; Reduced significant power
Low hardware overheads
Introduction: Due to the need of time, it is necessary to
develop low power design techniques
Dedicated hardware designers can provide lowpower system by reducing dynamic power
dissipation that;1. Relies on load capacitance
2. Clock frequency of the system
3. Toggle rate of the system
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Video applications have a unique characteristic whichis the neighboring pixels in a finite block usually havethe same pixel value or just slightly different value
This character can be exploited to reduce switching activityin arithmetic and processing modules by;
Bypassing smaller pixel values
Retaining intermediate results
Disabling data paths in architecture
This paper proposes a low power design for kernel basedoperations such as 2D-convolution, used in videoprocessing applications. The proposed features are;
1. Utilization of repetition of pixels and insignificant parts;to reduce operations and switching activities
2. Exploit the presence of repeated values, zeros,insignificant bits and special bit pattern in binaryrepresentation of pixels; to reduce switching activity inradix Booth multipliers of 2D convolution unit
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3. If special condition is detected, appropriate signal is
generated to disable parts or all data paths of the
architecture
This is called
NEIGHBORHOOD DEPENDENT APPROACH
(NDA)
4. Partitioning the input pixel data into smaller parts
increases the chances of special conditions in higher
order parts of the data
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Low Power Multipliers:
Because of massive multiplication, it is desired to have low power
multipliers, some low power multiplier techniques proposed by other
researchers are;
Multiplier using Carry Save Array (CSA)
Column bypass method
Hybrid multipliers
All these methodologies are applied to radix-2 operations.
Most widely applied implementation of high performance multiplier is
Modified Booth Algorithm
It is commonly used because it reduces number of partial products .i.e.
accumulation is faster with less switching
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According to different researchers, certain amendments are
made in the Booth Multipliers
Modification to increase probability of zero in partialproducts
Arranging CSA in Most Significant Bit First to utilize
sign extension zero encoding to reduce switching
Input data manipulation Changing operands to increase probability of zero-
encoding
Partitioning input data into smaller parts to increase
chances of data interchanging
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Neighborhood Dependent Approach (NDA)
for Kernel Based Operations In computing, the kernel is thecentral component of most
computeroperating systems; it is a
bridge between applications and
the actual data processing done atthe hardware level.
Most operating systems rely on
this concept of the kernel. The
existence of a kernel is a naturalconsequence of designing a
computer system as a series of
abstraction layers
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Image and video framing pixels have high spatial
redundancy (Elements that are duplicated within a
structure) in binary representation of pixels. Difference in consecutive pixel values in same
neighborhood is usually small
Only small number of bits will be changed in consecutive
operations; this character is used to reduce switching
activity.
Architectural approach refers to overall computation
where blocks of pixels are examined for possible
redundant computation
Spatial redundancy is exploited in higher bits of operands,by dividing them into small bits and multiple smaller
multipliers are used.
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The partitioning process of the operands in the
multiplication P=XY into higher and lower halves is
described as
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This approach is useful in 2D convolution
operations where coefficients have small
magnitudes.
Partitioning the operands will increase chances
that higher order bits are zero
If condition is detected, control signal isgenerated to turn off the corresponding registers
and functional units
If YH is zero in above equation, we are only left
with single multiplication and addition
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Similarly, the pixels and coefficients values
in the kernel-based operation with a KK
mask can be partitioned into multiplehalves as
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With this partitioning method, we can evaluate the higher
bits of the pixels in the same neighborhood to determine
if they are the same.
If the higher bits IH of the pixels in neighborhood under
consideration are the same, only one multiplication with
the sum of the coefficients is needed instead of K2
multiplications. The sum of the coefficientsWs can bepre-computed and loaded at system initialization.
The same reduction applies to additions. Whenever the
higher bits of the input pixels in the same neighborhood
are the same the operation for the term ,
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and the term,
can be reduced to one multiplication
and one addition operation for each term.
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The block diagram
in Figure shows overview of the architecture with
consideration of the neighborhood dependent approach.
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Design assumes the block of pixels is
cached in the memory block before theoperations
The block diagram shows only one Boothmultiplier being used for discussion and
simulation purposes.
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Arithmetic level Approach:
To consider the special bit patterns in the inputs to the
modified Booth multiplier and to turn off functional units
and data buses appropriately to reduce switching
activity. Inputs to the multiplier are partitioned into halves and
smaller Booth encoders and adders are used to perform
the necessary operations.
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Results And Conclusions
Five different implementations are carried out in thiswork to evaluate effectiveness of the proposedtechnique, these techniques are;
1. Conventional carry-save array multiplier (CSA)2. Radix-4 Booth multiplier (mBooth or modified Booth)
3. Conventional radix-4 Booth multiplier with dynamicrange detection and operand interchange(mBoothDRD)
4. The mBoothDRD multiplier with partitioning method(mBoothPAR)
5. NDA multiplier (mBoothNDA)
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Two commonly used kernel-based operations in image
and video processing applications are performed for
the evaluation
1. 2D convolution with a Gaussian kernel (low pass filter)
2. Edge detection operation (2D convolution with a
Laplacian kernel)
Both kernels have size of 33.
Some standard images are used to evaluate these
implementations. In this simulation;
1. The Lenna image
2. Lighthouse image
3. An outdoor image with high dynamic range
Are used
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Conclusions
The hardware design utilized special characteristics in
the video stream, to achieve;
1. Less dynamic power dissipation2. Reduced Power losses
3. Reduced switching
4. Disabling of data paths in architecture for special
values5. The architecture design helps to reduce up to 46
percent in transition rate in various applications
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Future Horizon
This approach can be further improved by
considering hybrid multipliers to reduce
the sign extension portion in the Boothmultiplier
Furthermore, partitioning the data into
smaller parts is also a good research topicto be considered.