Design Rules

• Interface between designer and process engineer

• Guidelines for constructing process masks• Unit dimension: Minimum line width– scalable design rules: lambda parameter– absolute dimensions (micron rules)

5

6

Stick Diagram

• A stick diagram is a graphical view of a layout.• Does show all components/vias (except

possibly tub ties), relative placement.• Does not show exact placement, transistor

sizes, wire lengths, wire widths, tub boundaries.

Stick Diagram

• Represents relative positions of transistors• Stick diagrams help plan layout quickly– Need not be to scale– Draw with color pencils or dry-erase markers

In

Out

VDD

GND

Inverter

A

Out

VDD

GNDB

NAND2

Stick Diagram

Metal (BLUE)

Polysilicion (RED )

N-Diffusion (Green)

P-Diffusion (Brown)

Contact / Via

Layers

Jhon P. U

Stick Diagrams

• Cartoon of a layout.

• Shows all components.

• Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules.

• Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.

Jhon P. U

5 V

Dep

Vout

Enh

0V

Vin

5 v

0 V

Vin

5 v

Jhon P. U

Parallel Connected MOS Patterning

x

y

A B

X X X

A B

x

y

Jhon P. U

Alternate Layout Strategy

A B

x

y

X X

X X

x

A B

y

Jhon P. U

Designing MOS ArraysA B C

yx

y

x

A B C

Jhon P. U

The CMOS NOT Gate

X

X

X

X

Vp

Gnd

x

Gnd

n-well

Vp

x xx

Contact Cut

Jhon P. U

Alternate Layout of NOT Gate

Gnd

Vp

x

x

X

x

Vp

Gnd

X

x

X

X

Jhon P. U

NAND2 Layout

Gnd

Vp

ba.

a b

X

Vp

Gnd

X X

X X

a b

ba.

Jhon P. U

NOR2 Layout

Gnd

Vp

ba

a bX

Vp

Gnd

X X

X X

a b

ba

Jhon P. U

NAND2-NOR2 ComparisonX

Vp

Gnd

X X

XX

XX

X

XX

Vp

Gnd

MOS Layout Wiring

2: MIPS Processor Example Slide 20

Activity 2

• Sketch a stick diagram for a 4-input NOR gateA

VDD

GND

B C

Y

D

Jhon P. U

Stick Diagram - Example II

Power

Ground

B

C

OutA