The Frontiers of Robust Circuit Designin Sub‐28nm Process Technologiesg
Jim Dodrill
ARM
“The conventional wisdom that led to our success in the past will no longer work in the future.”
Cliff Hou, VP R&D, TSMC, at DAC 2014
2
3
Agenda
• The Cost of Design Margins
• FinFET Changes the LandscapeFinFET Changes the Landscape
• Variation– Process, Voltage, and TemperatureProcess, Voltage, and Temperature
– Location and Layout Dependent Effects
• Random Failures– Radiation, Synchronization, and Noise
• Aging– BTI, HCI, EM, and TDDB
• Putting it All Together
4
Focus
• Focus is on SoC implementation aspects
Assume foundry and IP partners have done their– Assume foundry and IP partners have done their best to offer reliable products
• For each failure mechanism:
I d h h i l b k d– Introduce the physical background
– Compare planar vs. FinFET
– Offer practical design advice
5
Device Lifetime
• Testing• defects
• Random Failures• soft errors
• Aging• BTI HCI• defects
• variation• soft errors• synchronization• noise
• BTI, HCI• EM, TDDB
e rate
failure
burn‐in useful life wear‐out
6
log time
The Heart of the Matter…
“At the heart of reliability engineering is the fact that there is a di ib i f lif i f h f il h i Wi h ldistribution of lifetimes for each failure mechanism. With low failure rate requirements we are interested in the early time‐range of the failure time distributions. There has been an increase in process variability with scaling (e.g., distribution of dopant atoms, CMP variations, and line‐edge roughness). At the same time the size of a critical defect decreases with scalingsame time the size of a critical defect decreases with scaling. These trends will translate into an increased time spread of the failure distributions and, thus, a decreasing time to first failure.”
ITRS 2013, Process Integration, Devices, and Structures
7
Tactics
• Margining
Th l M t• Thermal Management
• Dynamic Voltage and Frequency Scaling (DVFS)
– In‐situ monitors
– Adaptive Supply Voltage (ADV) or Back‐Bias (ABB)
• Redundant Components
– Error Detection and/or Correction/
– Time Multiplexing (Resource or Task Allocation)
– Cannibalization (Resource Sharing)
8
Cannibalization (Resource Sharing)
The Cost of Design Margins
Moore’s Law
Dark Silicon
Margin Cost
“Traditional VLSI design bypasses the analysis and optimization of such non‐uniform, dynamic network by approximating the problem into optimization of uniform static network with certain
d b d ”guard band.”
Muhammad Alam,“Reliability and process variationReliability‐ and process‐variation aware design of integrated circuits”2008 Elsevier Ltd.
10
Moore’s Law is Still Alive
• The cost per transistor continues to reduce
Or does it?– Or does it?
11 Source: Bill Holt (Intel), “Intel Investor Meeting,” (2014)
Another View…
• Lower yield will drive costs up in at 20nm and smaller while competition will drive costssmaller while competition will drive costs down at 28nm and larger.
12
The Dark Silicon Apocalypse“Where once we would spend exponentially increasing amounts of silicon area to buy performance, now, we will spend exponentially increasing amounts of silicon area to buy energy efficiency.”
Michael B. Taylor, “Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse ” ACM (2012)Dark Silicon Apocalypse,” ACM (2012)
Will increasing amounts of silicon area be used to buy reliability?
13
Will increasing amounts of silicon area be used to buy reliability?Of course!
Timing Margins
• More accurate modeling of timing variation results in more efficient implementationsresults in more efficient implementations
120%
OCV Margin Methods
106%
94% 96%
86%
80%
100%
60%
80%
OCV
AOCV
LVF
20%
40%
14
1% 1% 1% 1%0%
frequency dynamic power static power cell area
FinFETs Change the Landscape
Planar vs. FinFET
Multi‐patterned Interconnect
Introducing the FinFET
Source: GLOBALFOUNDRIES
16
Planar vs. FinFET
17 Source: Mark Bohr , et al. (Intel) (2011)
Fins are Very Thin
• This is a TEM image of the Intel 22nm Fin
At 14 Fi ill b b t 20 t id• At 14nm, Fins will be about 20 atoms wide
18 Chipworks (2012)
The Future…
19
Source: Martin van den Brink, “Many ways to shrink: The right moves to 10 nanometer and beyond,” AMSL (2014)
Delay vs. Voltage
20 Source: Mark Bohr , et al. (Intel) (2011)
Power vs. Speed
21 Source: Shien‐Yang Wu, et al. (TSMC), IEDM (2013)
Leakage vs. Achieved Frequency
• Leakage reduction from FinFET is significant
age
Leak
a
22Source: Leah Schuth, (ARM) (2014)
Achieved Clock Frequency
Interconnect
23Source: S. Natarajan, et al. (Intel), IEDM (2014)
Wire Resistance
• The RC time constant of wires is increasing substantially as line widths reducesubstantially as line widths reduce
24Source: Serkan Kincal, et al., “RC Performance Evaluation of Interconnect Architecture Options Beyond the 10‐nm Logic Node,” IEEE (2014)
Cell vs. Wire Delay
• Wire delay is becoming as big as cell delay
We’ve heard this for years but its real now– We ve heard this for years, but its real now
25Source: Greg Yeric (ARM), “Design, Technology and Yield in the Post‐Moore Era,” ITC (2014)
Double Patterning
26
Source: Andrew J. Hazelton, et al. “Double‐patterning requirements for optical lithography and prospects for optical extension without double patterning,” J. Micro/Nanolith. MEMS MOEMS (2009)
RC Variation
• Note the wire thickness and spacing differences in the two metal patterns A & Bdifferences in the two metal patterns, A & B
27Source: ITRS 2013 EDITION: INTERCONNECT
On‐Chip Variation
Process, Voltage & Temperature Variation
Layout Dependent Effects
OCV Modelling
Sources of Variation
• Process (transistor and wire)
V lt• Voltage
• Layout Dependent Effects (LDE)
• Temperaturetemperature variation
LDE
voltage variation
process variation
29
Variation: Planar vs. FinFET
• Single fin FinFETs are not used due to high variationvariation
Source Planar FinFET
Random Dopant (less)Line Edge Roughness Gate Edge Roughness Gate Granularity Fin Edge Roughness Fin Height Fi Sh
30
Fin Shape Source: Greg Yeric (ARM), “Design, Technology and Yield in the Post‐Moore Era,” ITC (2014)
Variation vs. Voltage
• Delay and variation increase as voltage decreasesdecreases
31 Source: Isadore Katz, CLK DA (2014)
Voltage Variation
• Chip dynamic voltage drop based on two different operating modesdifferent operating modes
32 A. Shanmugavel, Ansys Inc. (2013)
Temperature Variation
• Thermal conduction from the channel
planar transistors: tends toward the substrate– planar transistors: tends toward the substrate
– finFET transistors: tends toward the metal
~12C
~
33 A. Shanmugavel, Ansys Inc. (2013)
Layout Dependent Effects
• Non‐uniformities in the surrounding context of a transistor adds to delay variationof a transistor adds to delay variation
34
OCV Modeling
• Traditional OCV
Percentage derate applied to clock paths– Percentage derate applied to clock paths
– Plus a fixed margin added to the clock uncertainty
eren
ce
intercept=margin
of d
elay
diff
e3s
igm
a o
35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
path depth
AOCV Modeling
• Advanced OCV (AOCV)
Tables of derate values for cells and nets indexed– Tables of derate values for cells and nets indexed by path depth
– These tables are called Stage‐Based OCV (SB‐OCV)– These tables are called Stage‐Based OCV (SB‐OCV)
– May include location‐based (LOCV) derate tables
1 5
1
1.5
1±nσ/μ early
late
0.5
1
derate=
36
0 20 40 60 80 100
d
path depth
Stage Based‐OCV Limitation
• SB‐OCV is limited to:
One timing arc per cell– One timing arc per cell
– One load/slew point
Delay Variation vs. Load/Slew
n index
e (σ/µ)
1
3
5
put tran
sition
Variance
37
7
1 2 3 4 5 6 7 8
inp
output load index
OCV Modeling
• Liberty Variance Format (LVF)
Table of sigma values for cell delay transition– Table of sigma values for cell delay, transition time, and constraints in the Liberty model
– Derates are calculated by the timing engine based– Derates are calculated by the timing engine based on N*sigma and path depth
LOAD
σ σ σ σ σ
SLEW
σ σ σ σ σ
σ σ σ σ σ
σ σ σ σ σ
38
σ σ σ σ σ
Statistical Constraint Margins
• Timing Constraints also have variation
Usually only hold and removal constraints are– Usually only hold and removal constraints are margined
lay
rop
agat
ion
de
Setup and hold are defined by a specified increase in
additional hold margin
Prp
CK->Q
39
Data arrival w.r.t. clocktsu_tp_r th_tp_r
Constraint Margins vs. Voltage
• The variation of also constraints increases as voltage decreasesvoltage decreases
40 Source: Isadore Katz, CLK DA (2014)
PVT Corners
Hold must beHold must be met across the entire
Full‐yield setup corner
process range
Typical On‐DieMean
FastestSlowest On‐DieMean
41
MeanFast
MeanSlow
Determining N*sigma
• LVF allows users to choose N*sigma
Native die yield should dominate not timing yield– Native die yield should dominate, not timing yield
Step Examplep p
Yield Failure Rate
Estimate manufacturing yield 95% 5/100
Chose a timing yield target that is better
97% 3/100
Estimate the number of near‐critical hold paths
50K 2/100K
multiply 99 99994% 6/10M
42
multiply 99.99994% 6/10M
Derive sigma about 5σ
“Statisticians, like artists, have the bad habit ofStatisticians, like artists, have the bad habit of falling in love with their models.”
‐‐ George Box
43
Practical Advice
• Use the latest, most accurate variation models availableavailable
– Consult your foundry and IP provider for guidance
B t t f b i i ti• Be sure to account for non‐obvious variation
– Layout Dependent Effects
– Wire Variation
• Consider the cost of design margins
– Yield loss vs. power, area, and design schedule
– Prioritize good hold margins
44
Random Failures
Soft Error Rate (SER)
Synchronization
Random Telegraph Noise (RTN)
The Neutron Strike
• Cosmic radiation includes alpha particles and high energy neutrons that can createhigh energy neutrons that can create ionization which can upset logic
46
Source: Christopher Frost, “How Alien InvadersCan Change Governments,” ISIS (2014)
SER of Planar vs. FinFET
• The trend is for improvement in SER
FinFET has 3X 10X lower SER than planar– FinFET has 3X‐10X lower SER than planar
47 Anthony S. Oates (TSMC), “Will Reliability Limit Moore’s Law?,” IEDM (2014)
SER of Systems
• While the SER of individual state elements is improving overall chip SER is notimproving, overall chip SER is not
– Flip‐flops dominate in systems with ECC
48Source: Vikas Chandra, “Cross layer resilience in real world,” DATE (2014)
SER vs. Voltage in FinFET
• SER increases as voltage decreases
Various FinFET technologies can improve SER– Various FinFET technologies can improve SER
49Source: Huichu Liu, et al., “Soft‐Error Performance Evaluation on Emerging Low Power Devices,“ IEEE (2014)
Practical Advice
• Acquire FIT rate estimates from foundries and IP providersIP providers
– Consider the lowest operating voltage domain
D t i hi h t t l t t ib t• Determine which state elements contribute the most to the probability of program failure
– The “Architectural Vulnerability Factor” (AVF)
– Harden those state elements
• Use appropriate error detection and correction
50
Clock domain crossing
• Synchronizers are used when data crosses between two asynchronous clock domainsbetween two asynchronous clock domains.
– That means data can change during the window between the setup and hold constraintsbetween the setup and hold constraints.
CK1Y
CK2
YD DQ Q
CK1 CK2
Y
CK2
tsu th
51
CK1 and CK2 are asynchronous
Metastability
• When setup and hold constraints are violated, the signals inside the receiving flip‐flop can failthe signals inside the receiving flip‐flop can fail to resolve within a clock period
CK
D
nm
CKCK
m
CK2
tsu th
Dnm
CK
m
m/nm
m fails to resolve to ‘1’ or ‘0’
52
m fails to resolve to 1 or 0
MTBF for Synchronizers
TS is the resolution time, which is approximately the clock periodτ is the resolution time constantτ is the resolution time constant,
a function of the latch design and PVT cornerTW is the time window, also a function of the latch design and PVTfd is the data frequencyfd is the data frequencyfc is the clock frequencyn is the number of synchronizers in the entire system
53
MTBF vs. Voltage
• MTBF reduces as voltage decreases– MTBF also decreases as the period decreases– MTBF also decreases as the period decreases
– VT choice is critical
MTBF vs. Voltage MTBF vs. VT and LG
70
80
90
1 E+50
1.E+60
1.E+70
1.E+80
600
700
800
1E+50
1E+60
1E+70
1E+80T G
30
40
50
60
1.E+20
1.E+30
1.E+40
1.E+50
τ(ps)
MTB
F (years)
300
400
500
1E+20
1E+30
1E+40
1E+50
τ(ps)
MTTF (years)
The universe
is 1 38*1010
0
10
20
30
1.E‐20
1.E‐10
1.E+00
1.E+10
0
100
200
1E 20
1E‐10
1
1E+101.38*1010
years old
54
01E‐20
lowest VT highest VT
Practical Advice
• Use specially constructed synchronizer cells
– One cell N‐stages deep– One cell, N‐stages deep
– Choose the lowest VT and shortest LG available
• Obtain the necessary MTBF parameters for your• Obtain the necessary MTBF parameters for your synchronizers
– Use the model for an average transistor on a slow die– Use the model for an average transistor on a slow die
– Calculate the MTBF at each voltage and frequency combination
– Account for the total number of synchronizers in the computing system
55
Random Telegraph Noise
• Random Telegraph Noise (RTN) is caused by the capture and emission of carriers at trapsthe capture and emission of carriers at traps (defects) in the oxide boundary
56Source: Xiaoming Chen, et al., “Statistical Analysis of Random Telegraph Noise in Digital Circuits,” IEEE (2014)
Random Telegraph Noise
• “The static variability of the source‐induced RDF is found to overwhelm the dynamic on‐current f yfluctuation due to RTN.”
RTN = Random Telegraph NoiseRDF R d D t Fl t ti
57Source: Akito Suzuki, et al, “Source‐induced RDF Overwhelms RTN in Nanowire Transistor: Statistical Analysis with Full Device EMC/MD Simulation Accelerated by GPU Computing,” IEEE (2014)
RDF = Random Dopant Fluctuation
Aging
BTI: Bias Temperature Instability
HCI: Hot Carrier Injection
EM: Electro‐migration
TDDB: Temperature Dependent Dielectric Breakdown
BTI: Stress and Recovery
VDD VDD VSSPMOS:Negative Bias
G:0(on)
D:1
G:1(off)
D:1 or 0
G:1(off)
D:1 or 0
TemperatureInstability(NBTI)
D:1 D:1 or 0 D:1 or 0
Stress NaturalRecovery
ProactiveR
D:0 or 1D:0 D:0 or 1
Recovery Recovery
NMOS:Positive Bias
G:0(off)
G:1(on)
G:0(off)
VDD
Positive BiasTemperatureInstability(PBTI)
59
VSSVSS
(PBTI)
Based on: Lin Li, “Improving the Reliability of Microprocessors Under BTI and TDDB Degradations,” University of Pittsburgh (2014)
BTI: Planar vs. FinFET
• The VT shift due to PBTI is lower, and due to NBTI is higher for FinFETNBTI is higher for FinFET
60 Kyong Taek Lee, (Samsung) IEEE (2013)
BTI: Ring Oscillator Degradation
• VT shifts due to BTI lead to larger propagation delaydelay
61
Source: Halil Kükner, et al., “Scaling of BTI reliability in presence of Time‐zero Variability,” IEEE (2014)
BTI vs. Voltage
• At higher voltage, delay degradation is more
62
Source: Halil Kükner, et al., “Scaling of BTI reliability in presence of Time‐zero Variability,” IEEE (2014)
BTI and Variation
• Process variation remains a normal distribution after agingdistribution after aging
63 D. Angot, et. al. , IEDM (2013)
BTI: Stress vs. Relaxation
• Partial healing during relaxation leads to delay degradation that is state dependentdegradation that is state dependent
64 Kyong Taek Lee, (Samsung) IEEE (2013)
BTI and Duty Cycle
DutyFactor
Square WaveArbitrary Switching
100%75%50%
Factor
50%25%5%
65
Source: Haldun Kufluoglu, “MOSFET Degradation due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) and its Implications for Reliability‐Aware VLSI Design ,” Purdue University (2007)
Path Rank Analysis
• Rank paths in fresh and aged design, sorted by slack
• Non‐critical paths can become critical vice versaNon critical paths can become critical, vice versa
Path rank% Timing
DegradationFreshAged
(Dhrystone)
Path rank% Timing
DegradationAged
(Dhr stone)Freshg
(Dhrystone)
1 14084 7.642 9781 7.94
3 9329 8.02
g(Dhrystone)
1 179394 15.612 145042 15.413 134419 15.183 9329 8.02
4 12345 7.875 6220 8.316 36672 7.16
3 134419 15.18
4 1413427 17.575 272323 15.676 224034 15.46
7 7771 8.198 11580 7.969 28975 7.40
10 20054 7 66
7 331934 15.768 275422 15.569 481425 16.06
10 208561 15 24
66
10 20054 7.66 10 208561 15.24
Source: Vikas Chandra, et al. (ARM), “Workload dependent NBTI and PBTI analysis for a sub‐45nm commercial microprocessor,” IEEE (2013)
Hold Time with Gated Clocks
• Since the rising edge of a gated clock spends most of its time in recovery it does not agemost of its time in recovery, it does not age
• Rising edge of un‐gated clocks does age
• Leading to potential hold failures over time
Rising edge does not age
EN0
1 0 1 0
CK
67
Both edges age
Practical Advice (1/2)
• Set critical range to at least 10% of the clock periodperiod
– Prevents area and leakage recovery from creating setup paths that will age to become criticalsetup paths that will age to become critical
critical range
percentile
area and leakage recovery
path p
68
0 +10%path slack
Practical Advice (2/2)
• Most gated clocks should connect directly to sequential elementssequential elements
– Identify cases of clock tree stages beyond the gated clock and add extra hold margingated clock and add extra hold margin
• Advocate with EDA vendors for static timing with aging based on time and switchingwith aging based on time and switching activity
Th i f d t i i i t it hi– The issue of determining an appropriate switching activity remains
69
Hot Carrier Injection
Channel Hot‐Electron Injection Drain Avalanche Hot‐Carrier Injection
70
Channel Hot Electron Injection Drain Avalanche Hot Carrier Injection
Source: Robert Entner , “Modeling and Simulation of Negative Bias Temperature Instability,” Technische Universitat Wien (2007)
HCI: Planar vs. FinFET
• HCI in FinFET is better than planar transistors
71Source: S. E. Liu, et. al., (TSMC) “Self Heating Effect in FinFETs and its Impact on Device Reliability Characterization,” IEEE (2014)
Practical Advice
• Limit the maximum transition time to reduce degradation due to HCIdegradation due to HCI
– This will insure HCI has less effect than BTI
Ad t ith EDA d f t ti ti i• Advocate with EDA vendors for static timing with aging due to HCI
– Table based on input transition, output load, and switching activity
72
Electromigration
(Black’s Equation)
73 Source: Y. L. Hsu, et al., “Failure Mechanism of Electromigration in Via Sidewall for Copper Dual Damascene Interconnection,” ECS (2006)
EM: Resistance vs. Time
• Resistance changes as dislocations form– Failure criteria is specified as a given resistance shift in a– Failure criteria is specified as a given resistance shift in a percentage of samples
74Source: Zhuojie Wu, “Study of Initial Void Formation and Electron Wind Force for Scaling Effects on Electromigration in Cu Interconnects,” University of Texas (2013)
EM Trend
• With stronger FinFET transistors and thinner interconnect EM is becoming criticalinterconnect, EM is becoming critical
75 ITRS (2013)
EM and FinFETs
• Self‐Heating in FinFETs may lead to worse EM in surrounding wiresin surrounding wires– Self‐heat manifests as a sensitivity to the fin or gate count in switching aging degradationg g g g
76http://semimd.com/blog/tag/rram/
Practical Advice
• Take advantage of the Blech effect whenever possible, especially in VIA stackspossible, especially in VIA stacks
• Build and verify power grids early– Limit placement density in areas with high powerLimit placement density in areas with high power
• Limit wire length and maximum transition times to reduce RMS EM violations on signalstimes to reduce RMS EM violations on signals
• Follow IP provider guidelines for cell level EM compliancecompliance
• Carefully balance operating temperatures and MTBF due to EM
77
MTBF due to EM
Time Dependent Dielectric Breakdown
78 Source: ITRS 2013 EDITION: INTERCONNECT
TDDB:
• Electric fields are highest at wire tips
Line edge roughness contributes on wire sides– Line edge roughness contributes on wire sides
79Source: Ong, IEEE IPFA (2012)
TDDB vs. Spacing
• TDDB is becoming a concern
m m 4nm
28nm
22nm
20/14
80Anthony S. Oates (TSMC), “Will Reliability Limit Moore’s Law?,” IEDM (2014)
Summary
The Balancing Act
The Balancing Act: Temperature
* * * *
rature
Temper
T
equen
cy
Power
ariation
SER
c. M
TBF
BTI/HCI
EM
TDDB
82
Fre Va
Sync B
*Depends on voltage
The Balancing Act: Voltage
age
Volta
equen
cy
Power
ariation
SER
c. M
TBF
BTI/HCI
EM
TDDB
83
Fre Va
Sync B
84