The Ultimate System Integration Platform
VIRTEX-5 FPGAs
V5_SXTbroc_Final.qxd 1/5/07 8:04 AM Page 1
THE WORLD’S FIRST 65nm FPGA
One Family—Multiple Platforms
The Virtex™-5 family of FPGAs offers a choice of four new platforms,each delivering an optimized balance of high-performance logic,serial connectivity, signal processing, and embedded processing.Three platforms are available now:
Optimized for high-performance logic
Optimized for high-performance logic with low-power serial connectivity
Optimized for DSP and memory-intensive applications with low-power serial connectivity
Discover how this new family delivers even higher performance,lower power, and lower system cost than previous-generationVirtex-4 FPGAs.
Meet Your Performance Targets Easily
• Achieve a two speed-grade performance gain with new ExpressFabric™ technology
• 550 MHz clocking technology and performance-tunedIP blocks
• 352 GMACS performance from DSP48E slices • 1.25 Gbps LVDS I/O: up to 600 pin pairs (1,200 I/Os)
Optimize I/O Bandwidth, Power and Cost with Easy-to-Use High-Speed Serial Solutions
• RocketIO™ GTP transceivers deliver 100 Mbps – 3.2 Gbpsserial connectivity
• First FPGA with hardened PCI Express endpoint blocksand Tri-mode Ethernet MACs
• Lowest power in the industry: less than 100 mW per transceiver at 3.2 Gbps
• Advanced equalization techniques to drive backplanes beyond 40”
• Protocol solutions kits accelerate development
Beat Your Power Budget while Maximizing Performance
• 35% lower dynamic power with 65nm ExpressFabricand power-saving IP blocks
• Reduce serial connectivity power consumption: RocketIOGTP transceivers consume less than 100 mW at 3.2 Gbps
Perf
orm
ance
LogicFabric
Performance
On-chipRAM
550 MHz
DSP32-Tap Filter
550 MHz
I/O LVDSBandwidth750 Gbps
I/O MemoryBandwidth384 Gbps
Virtex-5 FPGAs Virtex-4 FPGAs Nearest Competitor
Numbers show comparision with nearest competitorBased on competitor’s published datasheet numbers
1.3 x
1.3 x 1.6 x
2.4 x
4.4 x
Industry’s fastest 90nm FPGA benchmark
Virtex-5
V5_SXTbroc_Final.qxd 1/5/07 8:04 AM Page 2
Reduce Cost through System Integrationwith Domain-Optimized Platform FPGAs
• Choose a smaller device: 65nm process shrinks die size andnew 6-input LUT increases utilization and efficiency
• Meet aggressive performance targets in the least expensivespeed grade
• Reduce part count with built-in, low-power transceivers • Increase logic efficiency with built-in PCI Express® endpoint
and Ethernet MAC blocks • Select smaller heat sinks, fans, and power supplies enabled
by reduced power consumption • Bring your product to market faster with proven development
and verification tools • Reduce component cost in volume production with Virtex-5
EasyPath™ FPGAs
Finish Your Design Ahead of Schedule
• Achieve FPGA performance goals quickly with ISE™ Fmaxtechnology and PlanAhead™ design analysis tools
• Reach timing closure up to 6x faster with newSmartCompile technology
• Design faster and reduce risk with over 225 pre-verifiedIP cores
• Reduce debug cycle time with the real-time verification capabilities of ChipScope™ Pro tools
• Build complete embedded processing systems withPlatform Studio and Embedded Development Kit
• Implement DSP algorithms in custom-configured hard-ware with the AccelDSP™/MATLAB™ tool flow
• Accelerate product development with online resources,training courses, and premium support services
• Get Xilinx Productivity Advantage (XPA) bundles of software, education, support services, and IP cores
• Augment your development team with a worldwide network of Xilinx Design Service (XDS) and partner experts
The conversion-free cost-reduction path for volume production.
• EasyPath FPGAs reduce component cost by 30–75%with no risk of conversion, no hidden costs
• Enjoy unprecedented flexibility and fastest turn-around times
VIRTEX-5 EASYPATH™ FPGAs
Solve Signal Integrity Challenges and Simplify PCB Layout
• Second-generation sparse chevron packaging delivers SSOnoise and crosstalk benefits, essential for reliable operationof high-bandwidth parallel interfaces (e.g. memories)
• On-substrate bypass capacitors and a unique pinout simplifyPCB design, improve power integrity, and reduce system cost
• Built-in serial connectivity reduces pin/trace count and eliminates parallel interface design challenges
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The Right Memoryfor Any Application
Distributed RAM—Small
• Build 256-bit memory per CLB • 64 bits per LUT
550 MHz, 36 Kbit Block RAM—Medium
• Configure Block RAM as multi-rate FIFO• Built-in ECC for high-reliability systems• Automatic power conservation circuitry
High-Performance External Memories—Large
• ChipSync™ technology for reliable interfaces• Achieve data rates up to 389 Gbps
65nm ExpressFabric™
Technology
Achieve highest performance, most efficient utilization on 65nm triple-oxide process
• 30% higher speed, 35% lower dynamic power,and 45% less area than the previous generation
• Industry’s first LUT with six independent inputs for fewer logic levels
• Flexible LUTs are configurable as logic, distributed RAM or shift registers
• Advanced diagonally symmetric interconnect enables shortest,fastest routing
• From 30,000 to 330,000 logic cells for system-level integration
THE ULTIMATE SYSTEM
INTEGRATION PLATFORM
550 MHz Clocking Technology
Achieve highest speeds with high-precision, low-jitter clocking
• 12 DCMs provide phase control of less than 30 ps for better design margin
• 6 PLLs reduce reference clock jitter by more than 2x• Differential global clocking ensures low skew and jitter
Virtex-5
V5_SXTbroc_Final.qxd 1/5/07 8:04 AM Page 4
M
M
Ethernet Media Access Controller:10/100/1000 Mbps
Connect to the Internet via an integrated tri-mode Ethernet MAC
• UNH-verified compliance • Built-in hard IP frees user logic resources and reduces power • Four Ethernet MAC blocks on every Virtex-5 LXT/SXT device
RocketIO™ GTP Transceivers:100 Mbps–3.2 Gbps
Implement serial protocols atlowest power
• Flexible SERDES supports multi-rateapplications
• Designed to work with integrated PCIe™
and Ethernet MAC blocks • 77% lower power consumption:
less than 100 mW at 3.2 Gbps
PCI Express Endpoint Block:x1/x2/x4/x8-lane
Built-in support for ubiquitous serial connectivity standard
• PCI-SIG-verified compliance (on integrators list) • Works with RocketIO GTP transceivers to deliver
full PCIe endpoint function • Built-in hard IP frees user logic resources and
reduces power
Sparse Chevron Packaging Technology
Keep system noise under control and simplify PCB layout
• Unique PWR/GND pin pattern minimizescrosstalk and reduces PCB layers
• On-substrate bypass capacitors shrink PCB area
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Enhanced Configuration and Bitstream Protection
Reduce system cost, increase reliability,and safeguard your design
• Configure with commodity SPI and parallel flash memory • Easier partial reconfiguration and smaller frame size • Greater reliability for in-system reconfiguration with
multi-bitstream management • Protect your designs with 256-bit AES
(Advanced Encryption Standard) security
mode Ethernet MAC
reduces power XT/SXT device
550 MHz DSP48E Slice
Achieve up to 352 GMACS DSP Performance
• Up to 640 DSP48E slices in Virtex-5 SX95T device • Enhanced slice with 25 x 18 multiplier and 48-bit adder
enables single-precision floating-point math and wide filters with fewer slices
• Configurable for DSP, arithmetic, and bit-wise logic • Enables efficient adder-chain architectures • 40% lower power consumption: 1.38mW/100MHz at
a 38% toggle rate
1.25 Gbps SelectIO™ with ChipSync™
Source-Synchronous Technology
Implement industry-standard and custom protocols
• Simplify board design with built-in input delay and new output delay circuits that compensate for unequaltrace lengths
• Adaptive delay setting recalibrates automatically tocompensate for changing operating conditions
• Interface to popular standards with 1.25 Gbps differential and 800 Mbps single-ended I/O
• Digitally controlled impedance improves signal integrity,reduces component count, and shrinks board size
System Monitor and Analog-to-Digital Converter
Simplify system management and diagnostics
• Fully specified 10-bit, 200k samples/s ADC with programmable monitoring functions (sequencing,averaging, alarms)
• Simplify the implementation and reduce the cost of environmental monitoring
• On-chip temperature and supply voltage sensors • 17 user-selectable external inputs • Analog measurements accessible via JTAG at any time
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Implement Parallel Networking and System Interface Standards
SelectIO circuitry, combined with pre-verified IP cores,make it easy to support all popular interface standards
• 1.25 Gbps LVDS, 800 Mbps single-ended • Interface or bridge to virtually any external component • Support multiple electrical standards in the same device with
35 individually configurable I/O banks• Design with PCI, RapidIO, XSBI, SPI4.2, and more • Configure I/Os to support HSTL, LVDS (SDR and DDR), and more,
at voltages from 1.2V to 3.3V
A SOLUTION FOR EVDESIGN CHALLENGE
Accelerate Development with Complete Serial Solutions
Build chip-to-chip, board-to-board, and box-to-box applications quickly and easily
• Obtain assured compliance with popular standards • Reduce design time with integrated interface blocks and
pre-verified IP • Implement custom solutions • Reduce pin/trace count to simplify board design and reduce
manufacturing cost • Start designing with ready-to-use solution kits including protocol-
specific characterization reports, boards, and simulation models
Bridge Protocols
Protect your investment by interfacing easily to legacy ASSPs or ASICs
• Reduce design time with built-in support for PCI Express and Ethernet • Implement other popular protocols with pre-verified IP • Connect external peripheral components to any processor with
standards-compliant I/O
Simplify Source-Synchronous Interfacing
ChipSync technology in every SelectIO block provides precise control over critical timing for high-performancesource-synchronous interfaces
• Achieve performance targets and simplify PCB layout with flexible per-bit deskew
• Synchronize incoming data to FPGA internal clock with built-inSerializer/Deserializer
Build Highest-Bandwidth Memory Interfaces
ChipSync technology and the Memory Interface Generator tool make it easy to build reliable interfaces to the latest high-performance memories, including:
Data Rate(Mbps)
400
667
600
600
MemoryInterface
DDR SDRAM
DDR2 SDRAM
QDR II SRAM
RLDRAM II
Data Width(# of bits)
576
576
2 x 324
648
Bandwidth(Gbps)
230
384
389
389
Telecom OC-3 CPRI CPRI CPRI SFI-5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Per-channel Line Rate (Gbps)
0.0
OC-12
Networking 1GbE XAUI10G Base-CX4
Storage FibreChannel FibreChannelSATA, SAS
Video SDIDVB-ASI HD-SDI HD-SDI
SATA, SAS
OBSAI
Computing PCIeInfiniband
SRIO SRIOSRIO
OBSAI OBSAISFI-5OC-48
Virtex-5
µP ASSPCLK1 CLK6
CLK2 CLK5
CLK3 CLK4
V5_SXTbroc_Final.qxd 1/5/07 8:05 AM Page 7
Implement PCI Express with Reduced Cost,Power, and Complexity
Minimize design risk with hardened PCIe blocks for buildingnext-generation graphics, storage, networking, and I/O devices
• Integrate multiple functions into a single PCIe-enabled FPGA • Preserve software investment and extend infrastructure life with
scalable bandwidth (x1, x2, x4, x8) • Re-target designs without changing your PCIe interface implementation
as your project evolves
FOR EVERY PLATFORM NGE
PCI Express Design Example: High-End Desktop/Server System
Integrate Flexible EmbeddedControl Processors
Combine high-performance logic with the flexibility of software
Virtex FPGAs provide high-bandwidth I/Os, power-efficient embedded blocks, and high-performance logic fabric.Xilinx offers the MicroBlaze™ processor for efficient,flexible implementation of control functions.
Build a processor subsystem tailored to your requirements with Embedded Development Kit
• Start with award-winning Platform Studio tool suite • Instantiate a customizable 32-bit MicroBlaze soft processor • Select peripherals from a comprehensive IP catalog • Create custom peripherals to interface with system I/O
Develop your application using industry-standard software IDE tools from Xilinx or partners
• Choose an RTOS from Alliance Embedded partner offerings • Create custom hardware accelerators using ESL Ecosystem
partner tools
MicroBlaze Processor Subsystem Design Example
V5_SXTbroc_Final.qxd 1/5/07 8:05 AM Page 8
Create Highest-Performance DSP Systems
Increase DSP algorithm performance
• Build single or multi-rate filters for high-sample-rate applications in wireless RF or HD video systems with cascadable DSP48E slices
• Perform fine-granularity data shifting, control, and small bit-widtharithmetic functions efficiently in programmable logic fabric
• Free up DSP processor CPU cycles by off-loading algorithmic-intensivetasks to the FPGA co-processor
• Obtain highest memory-to-logic ratio with Virtex-5 SXT platform for efficiently implementing memory-intensive functions in video processing and medical imaging
Optimize DSP power consumption and cost
• Achieve efficient implementation with Xilinx algorithm/IP core supportfor base functions (e.g. FFT, filters), wireless functions (e.g. DDC, DUC,CFR, DPD) or video/imaging functions (e.g. CODECs)
• Use power-efficient Virtex-5 FPGAs in military manpack or handheldsoftware defined radios
Accelerate development with ready-to-use solution kits
• Protocol compliance reports • Device characterization • Reference designs • Development boards• Simulation models • Pre-verified IP • Development tools • User documentation • Partner solutions
TAKE THE NEXT STEPVisit us online at www.xilinx.com/virtex5
System Integration Design Example: Video-Over-IP
Build flexible, high-bandwidth interfaces
• Simplify design with built-in support for PCI Express interfaces • Obtain complete Xilinx solutions for market-specific interfaces such as
CPRI/OBSAI for wireless and HDI/SDI for professional broadcast systems• Build high-bandwidth interfaces to DSP processors using Xilinx IP and
reference designs for Serial RapidIO, VLYNQ™, or EMIF™ when usingFPGAs as DSP co-processors
Increase DSP Design Productivity
• Design using MATLAB™, Simulink™, Verilog, VHDL, or C, in any combination• Simulate and verify your design on the FPGA using high-bandwidth
hardware-in-the loop capability
Building on Proven DSP Leadership
The Berkeley Design Technology Inc.(www.bdti.com) 2006 independent technical benchmark analysis concluded that Virtex-4 SX25 FPGAs delivered 2X lower cost-per-channel compared to Altera Stratix-II 2S15FPGAs,for the BDTI Communications Benchmark (OFDM)™.
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Corporate Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Tel: 408-559-7778
Fax: 408-559-7114
Web: www.xilinx.com
Europe Headquarters
Xilinx Ireland
One Logic Drive
Citywest Business Campus
Saggart, County Dublin
Ireland
Tel: +353-1-464-0311
Fax: +353-1-464-0324
Web: www.xilinx.com
Japan
Xilinx, K. K.
Shinjuku Square Tower 18F
6-22-1 Nishi-Shinjuku
Shinjuku-ku, Tokyo
163-1118, Japan
Tel: 81-3-5321-7711
Fax: 81-3-5321-7765
Web: www.xilinx.co.jp
Asia Pacific Pte. Ltd.
Xilinx, Asia Pacific
No. 3 Changi Business Park Vista,
#04-01
Singapore 486051
Tel: (65) 6544-8999
Fax: (65) 6789-8886
Web: www.xilinx.com
The Programmable Logic CompanySM
www.xilinx.com
©2007 Xilinx Inc. All rights reserved. The Xilinx name and logo are registered trademarks, and The Programmable Logic Company is a service mark of Xilinx Inc. All other trademarks are theproperty of their respective owners.
Printed in U.S.A. PN 0010938-3
Notes: 1 A single Virtex-5 CLB comprises two slices, with each containing four Real 6-input LUTs and four Flip-Flops (twice the number found in a Virtex-4 slice), for a total of eight 6-LUTs and eight Flip-Flops per CLB.
2 Virtex-5 logic cell ratings reflect the increased logic capacity offered by the new Real 6-input LUT architecture.3 Number of available RocketIO™ multi-gigabit transceivers (MGTs) for each device/package combination shown in parentheses.
LX30XC5VLX30
–
80 x 30
4,800
30,720
19,200
320
32
1,152
42400
13
Yes
200
3210008.4
220
400
LX50XC5VLX50
–
120 x 30
7,200
46,080
28,800
480
48
1,728
126560
17
Yes
280
481000
12.6
220
440
560
CLB Resources
Mem
oryResources
ClockResources
I/O Resources
Embedded
Hard IP
Resources
Part Num
ber
EasyPath™
Cost Reduction Solutions
CLB Array Size (Row x Colum
n)
Slices 1
Logic Cells 2
CLB Flip-Flops
Maxim
um Distributed RAM
(Kbits)
Block RAM/FIFO
w/ECC (36 Kbits each)
Total Block RAM (Kbits)
Digital Clock Manager (DCM
)
Phase Locked Loop (PLL)/PMCD
Maxim
um SelectIO
™Pins
SelectIO™
Banks
Digitally Controlled Impedance
Maxim
um Differential I/O
Pairs
DSP48E Slices
System M
onitor Blocks
PCI Express Endpoint Blocks
10/100/1000 Ethernet MAC Blocks
RocketIO™
GTP Low
-Power Transceivers
Configuration Mem
ory (Mbits)
PackageA
reaIO
MG
T 3
FF32419 x 19 m
m220
FF67627 x 27 m
m440
FF115335 x 35 m
m800
FF176042.5 x 42.5 m
m1200
FF66527 x 27 m
m360
8
FF113635 x 35 m
m640
16
FF173842.5 x 42.5 m
m960
24
LX85XC5VLX85
XCE5VLX85
120 x 54
12,960
82,944
51,840
840
96
3,456
126560
17
Yes
280
481000
21.8
440
560
LX110XC5VLX110
XCE5VLX110
160 x 54
17,280
110,592
69,120
1,120
128
4,608
126800
23
Yes
400
641000
29.1
440
800
800
LX220XC5VLX220
XCE5VLX220
160 x 108
34,560
221,184
138,240
2,280
192
6,912
126800
23
Yes
400
1281000
53.1
800
LX330XC5VLX330
XCE5VLX330
240 x 108
51,840
331,776
207,360
3,420
288
10,368
126
1,200
33
Yes
600
1921000
79.7
1200
VIR
TEX-5 FA
MILY
VIR
TEX-5 LX
Optim
ized for High-performance Logic
VIR
TEX-5 LX
TO
ptimized for High-perform
ance Logic with
Low-pow
er Serial Connectivity
VIR
TEX-5 SX
TO
ptimized for DSP w
ith Low-
power Serial Connectivity
LX30TXC5VLX30T
–
80 x 30
4,800
30,720
19,200
320
36
1,296
42360
12
Yes
180
3211489.4
360 (8)
LX50TXC5VLX50T
–
120 x 30
7,200
46,080
28,800
480
60
2,160
126480
15
Yes
240
4811412
14.1
360 (8)
480 (12)
LX85TXC5VLX85T
XCE5VLX85T
120 x 54
12,960
82,944
51,840
840
108
3,888
126480
15
Yes
240
4811412
23.3
480 (12)
LX110TXC5VLX110T
XCE5VLX110T
160 x 54
17,280
110,592
69,120
1,120
148
5,328
126680
19
Yes
340
6411416
31.1
640 (16)
680 (16)
LX220TXC5VLX220T
XCE5VLX220T
160 x 108
34,560
221,184
138,240
2,280
212
7,632
126680
20
Yes
340
12811416
55.1
680 (16)
LX330TXC5VLX330T
XCE5VLX330T
240 x 108
51,840
331,776
207,360
3,420
324
11,664
126960
27
Yes
480
19211424
82.7
960 (24)
SX35TXC5VSX35T
—
80 x 34
5,440
34,816
21,760
520
84
3,024
42360
12
Yes
180
1921148
13.3
360 (8)
SX50TXC5VSX50T
XCE5VSX50T
120 x 34
8,160
52,224
32,640
780
132
4,752
126480
15
Yes
240
28811412
20.0
360 (8)
480 (12)
SX95TXC5VSX95T
XCE5VSX95T
160 x 46
14,720
94,208
58,880
1,520
244
8,784
126640
19
Yes
320
64011416
35.7
640 (16)