Tom NewsomVice President & General ManagerSOC Business UnitMay 2003
Agilent TechnologiesAccelerating the Future of DFT
CTL Press EventMay 2003
Overview
Increasing Market Momentum
Agilent Introduces the FIRST Browser for DFT
CTL: what is it, why it’s important
Design-to-Test Process
Agilent’s Power of DFT3 Solution
The Future…What’s Next?
CTL Press EventMay 2003
Agilent Q2 ResultsOrder Momentum(Feb.-April)
Automated Test Group
3
0
1
2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
2.92.7
2.5
1.4 1.3 1.21.5 1.6 1.5 1.5 1.4 1.5
2000 2001 2002 2003
Orders ($ Billion)
Q1 03 Q2 03
Orders
Loss Revenue
-35.3 % of revenue
-24.2 % of revenue
-$48-$37
$136$153
$115
$219
0
100
50
200$ Million
150
CTL Press EventMay 2003
Introducing—SmarTest PG CTL Browserthe FIRST browser for DFT
CTL = Core Test Language (IEEE P1450.6)
CTL Press EventMay 2003
MPEG
1394
ARMCore
RAM
EDA/designdatabase
CoreARM
RAM
MPEG
1394
Test development
Turn-on &characterization
Diagnostics
MPEG
1394
ARMCore
RAM
Customer shipHigh-volume
manufacturing
SOC Development Process
‘Design for test’ (DFT) - general design procedures, practices and rules that allow cost-effective solutions to achieve SOC quality and fast time to market.
Different colors = different tools from different companies..
interfering with DFT implementation.
CTL Press EventMay 2003
MPEG
1394
ARMCore
RAM
EDA/designdatabase
CoreARM
RAM
MPEG
1394
Test development
Turn-on &characterization
Diagnostics
MPEG
1394
ARMCore
RAM
Customer shipHigh-volume
manufacturing
SOC Development Process
‘Design for test’ (DFT) - general design procedures, practices and rules that allow cost-effective solutions to achieve SOC quality and fast time to market.
Different colors = different tools from different companies...
interfering with DFT implementation.
connectout scan chain1 96:99;enableOut coreSignal oe forceUp;disableOut coreSignal oeforceDown Z;
Period
‘tper’;
Clocks
{ PS { ‘0ns ’ U
; ‘t1’ D/U;
‘t2’ U
; }}
Control
{ 01 { ‘
0ns’ D
/U; }}
datain
{ 01 { ‘0ns’ D
/U; }}
dataout
{ LHX { ‘
sb1 ’ L
/H/X;
}}
purpose testTemplate;W base;C {se = 1; oe = 0;}
shift {// shift inscanin = si_bits;scanout= X;clocks = P;}V ( // normal modesi = 0;oe = 0;clocks=P;}
C {se = 1; oe = 0;}Shift {// shift outscanin = unknown;scanout= so_bits;clocks = P;}
Period
‘tper’
;
Clocks
{ PS
{ ‘0ns
’ U; ‘
t1’ D/
U; ‘t2
’ U; }
}
Contro
l
{ 01
{ ‘0ns
’ D/U;
}}
datain
{ 01
{ ‘0ns
’ D/U;
}}
dataou
t
{ LHX
{ ‘sb1
’ L/H/
X; }}
macro shiftNormalShift {// pattern 1
si_bits {000000…0010;}
so_bits {HLH…LHLHL;}
} macro shiftNormalShift {// pattern 2
si_bits {000000…0010;}
so_bits {HLH…LHLHL;}
}…………… macro shiftNormalShift {// pattern 99
si_bits {000000…0010;}
so_bits {HLH…LHLHL;}
} macro shiftNormalShift {// pattern 100
si_bits {000000…0010;}
so_bits {HLH…LHLHL
Inset into slide 9
CTL Press EventMay 2003
MPEG
1394
ARMCore
RAM
EDA/designdatabase
CoreARM
RAM
MPEG
1394
MPEG
1394
ARMCore
RAM
Test development
Diagnostics
Customer shipHigh-volume
manufacturing
SOC Development Process
CTL allows the parts to talk with each other.
Turn-on &characterization
Different colors = different tools from different companies...
interfering with DFT implementation.
CTL Press EventMay 2003
MPEG
1394
ARMCore
RAM
EDA/designdatabase
CoreARM
RAM
MPEG
1394
MPEG
1394
ARMCore
RAM
Test development
Diagnostics
Customer shipHigh-volume
manufacturing
SOC Development Process
CTL allows the parts to talk with each other.
Turn-on &characterization
Different colors = different tools from different companies...
interfering with DFT implementation.
Hig
h Qua
lity Te
st
Time
With core test re-use
Without core test re-use
CTL Provides Faster TTMthrough core test re-use
CTL Press EventMay 2003
MPEG
1394
ARMCore
RAM
EDA/designdatabase
CoreARM
RAM
MPEG
1394
MPEG
1394
ARMCore
RAM
Test development
Diagnostics
Customer shipHigh-volume
manufacturing
SOC Development Process
CTL allows the parts to talk with each other.
Turn-on &characterization
Different colors = different tools from different companies...
interfering with DFT implementation.
Pattern Exec {Spec { Category norm {
tper ‘100ns’;t1 ‘0.5*tper’;t2 ‘0.95*tper’;sb1 ‘t2 – 0.1’;
}waveformtable base {
Period ‘tper’;Clocks { PS { ‘0ns’ U; ‘t1’ D/U; ‘t2’ U; }}
Control { 01 { ‘0ns’ D/U; }}datain { 01 { ‘0ns’ D/U; }}
dataout { LHX { ‘sb1’ L/H/X; }}} Pattern burst {ScanStructures {ScanChain chain1 { ScanLength 100; ScanIn si; ScanOut so; ScanMasterClock clk; } }
Signals { Clk in { datatype clock; coreexternal { connectto PI; } } se in { datatype testcontrol; } oe in {}
si in { datatype scan; } d[3:0] in { coreInternal {
Inset into slide 12
CTL Press EventMay 2003
The Answer—SmarTest PG CTL Browser
CTL Press EventMay 2003
The Answer—SmarTest PG CTL Browser Finally,
a user-friendly
interface
CTL Press EventMay 2003
The Evolution of DFT - an Analogy
Internet Evolution
Darpaneta set of
tools and rules to
allow geeks to
communicate
TCP/IPstandards to move packets around
HTML language of
the Web
HTMLBrowser
allows humans to easily use the web
DFT Evolution
DFTa set of
tools and rules to
implement testability
in an SOC
P1500 embedded core test standard
to add DFT to an SOC
P1450.6CTL
emerging as
language for DFT
SmarTest PG CTL
Browser allows
humans to implement
DFT
CTL Press EventMay 2003
The Powerof the
Browser
Shift { C {si[1]=#; si[0]=#; so[0]=#; so[1]=#;} V { si_m123='d[0..4] si[1] si[0]'; so_m123='so[1] so[0] q[0..2]'; clk=P; WRCK=P;
}}V { clk=0; WRCK=0; sc=0; CaptureWR=1; ShiftWR=0;}V { clk=P; WRCK=P;}V { CaptureWR=0; clk=0; WRCK=0;}}} ActiveState U;Pattern Pat1 {M do_intest { d[0..4]=00000; si[0]=111000; si[1]=11110000;}M do_intest { so[0]=001X11; so[1]=111100X1; q[0..2]=001;
d[0..4]=01101; si[0]=011010; si[1]=01011101;}M do_intest { so[0]=1100X1; so[1]=10110000; q[0..2]=110;
d[0..4]=11001; si[0]=110010; si[1]=00011100;}M do_intest { so[0]=010001; so[1]=1X110100; q[0..2]=00X;
d[0..4]=01010; si[0]=001101; si[1]=10011101;}M do_intest { d[0..4]=00000; si[0]=111000; si[1]=11110000;}
M do_intest { so[0]=001X11; so[1]=111100X1; q[0..2]=001;d[0..4]=01101; si[0]=011010; si[1]=01011101;}
M do_intest { so[0]=1100X1; so[1]=10110000; q[0..2]=110;d[0..4]=11001; si[0]=110010; si[1]=00011100;}
M do_intest { so[0]=010001; so[1]=1X110100; q[0..2]=00X;
HTML
CTL
CTL Press EventMay 2003
Without Champions Leading End-to-End Solution, Benefits from Standards Languish
Lack of tools limited STIL Adoption
2000 2001 20021999 2003 2004
STIL
Ad
op
tion Agilent
SmarTest PGSTIL
readerintroduc
ed
StandardPublished
19981997
StandardStable /Balloted
CTL Press EventMay 2003
Customer Ship
MPEG
1394
ARMCore
RAM
EDA/DesignDatabase
CoreARM
RAM
MPEG
1394
MPEG
1394
ARMCore
RAM
Test Development
Turn-On &Characterization
Diagnostics
High-VolumeManufacturing
SmarTest PG CTL Browser
Industry Leaders Speed End-to-End Solution for maximum benefit from CTL standard
End-to-end tools speed CTL adoption
CTL A
dop
tion
Standardstable
2003
2004
2005
ToolsDelivered
ARM1136JF-S™ core
Program to prove concept
• DFT Compiler• TetraMAX• SoCBIST
CTL Press EventMay 2003
CTL Press EventMay 2003
1. EDA/Standards
• seamless design-to-test by driving partnerships and industry standards
• over 3100 hours invested by partners to ensure tools are interoperable
“We’re doing it so our customers don’t have to.“
2. Tools
• fast development and learning for the SOC development process
• Agilent SmarTest PG CTL browser
3. Agilent 93000 Single Scalable Platform
• with test processor per pin architecture
Agilent’s Power of DFT3
shortens TTM and lowers cost of test
CTL Press EventMay 2003
1. EDA/Standards
• seamless design-to-test by driving partnerships and industry standards
• over 4500 hours invested by partners to ensure tools are interoperable
“We’re doing it so our customers don’t have to.“
2. Tools
• fast development and learning for the SOC development process
• Agilent SmarTest PG CTL browser
3. Agilent 93000 Single Scalable Platform
• with test processor per pin architecture
Agilent’s Power of DFT3
shortens TTM and lowers cost of testScalable Platform vs. Limited DFT Tester
Limited DFT Testerü Basic DFT
§ Scan
93000 Scalable Platformü Basic DFT
§ Scan
CTL Press EventMay 2003
1. EDA/Standards
• seamless design-to-test by driving partnerships and industry standards
• over 4500 hours invested by partners to ensure tools are interoperable
“We’re doing it so our customers don’t have to.“
2. Tools
• fast development and learning for the SOC development process
• Agilent SmarTest PG CTL browser
3. Agilent 93000 Single Scalable Platform
• with test processor per pin architecture
Agilent’s Power of DFT3
shortens TTM and lowers cost of testScalable Platform vs. Limited DFT Tester
Limited DFT Testerü Basic DFT
§ Scan
q SOC DFT§ ?§ ?§ ?
93000 Scalable Platformü Basic DFT
§ Scan
ü SOC DFT§ Concurrent Test§ Compressed Scan Diagnostics§ New techniques
CTL Press EventMay 2003
1. EDA/Standards
• seamless design-to-test by driving partnerships and industry standards
• over 4500 hours invested by partners to ensure tools are interoperable
“We’re doing it so our customers don’t have to.“
2. Tools
• fast development and learning for the SOC development process
• Agilent SmarTest PG CTL browser
3. Agilent 93000 Single Scalable Platform
• with test processor per pin architecture
Agilent’s Power of DFT3
shortens TTM and lowers cost of testScalable Platform vs. Limited DFT Tester
Limited DFT Testerü Basic DFT
§ Scan
q SOC DFT§ ?§ ?§ ?
q SOC Functional Test§ ?§ ?
93000 Scalable Platformü Basic DFT
§ Scan
ü SOC DFT§ Concurrent Test
§ Compressed Scan Diagnostics
§ New techniques
ü SOC Functional Test§ Mixed Signal
§ Timing
CTL Press EventMay 2003
FIRST ATE/EDA alliance for lower cost of test: Agilent/Synopsys
FIRST ATE influenced design-to-test product: SmarTest PG
FIRST Concurrent test design-to-test support: SmarTest PG
FIRST ATE advocacy for P1450.3: Open standard for tester targeting paper
FIRST Automatic scan compression design-to-test support: SmarTest PG
FIRST ATE advocacy for open EDA databases: Synopsys MilkyWay
FIRST Browser for CTL: SmarTest PG CTL Browser
FIRST IEEE 1450/1999 STIL to ATE: SmarTest PG
FIRST Support for SOC DFT diagnostics: Synopsys SoCBIST
FIRST Industry Leaders Speed End-to-End CTL Solution: Agilent/Synopsys/STM/ARM
FIRST Concurrent test paper and proposal: ITC 20002000
2001
2002
2003
Breaking Down the Wall Between Design and Test
Power of DFT3 - a history of FIRSTS
CTL Press EventMay 2003
Power of DFT3
shortens TTM and lowers cost of test
1. EDA/Standards• Agilent will make CTL the language of DFT
2. Tools
SmarTest PG CTL BrowserSee demo of complete SOC development process Semicon West Booth #10516
3. Agilent 93000 Single Scalable Platform
• DFT solution available TODAY! New announcements & demo planned for Semicon West
CTL Press EventMay 2003
Visit Agilent at Semicon WestBooth # 10516
• Talk to industry CTL experts
• Hear real customer stories
• Meet with Agilent IEEE committee members
• See LIVE demonstrations:
• Power of DFT3 solution in process TODAY!!- meet w/Agilent partners and customers - see SOC DFT process demo at Semicon West
•SmarTest CTL Browser announced TODAY!! - see live demo at Semicon West
• Agilent 93000 DFT solution available TODAY !! - new announcements at Semicon West
CTL Press EventMay 2003
CTL Press EventMay 2003
Appendix
CTL Press EventMay 2003
CTL Background
IEEE P1450.6 core test language (CTL)http://grouper.ieee.org/groups/1450/index.html
an extension to IEEE 1450 standard test interface language (STIL)
• utilizing IEEE P1500 embedded core test. IEEE P1500 standard for embedded core test (SECT) tells the IP core provider how to wrap cores in a standard way for testability
• all necessary information for test pattern re-use
• the need for test during SOC system integration
• structural and test modes information to allow insertion of IP cores in an SOC design
CTL Press EventMay 2003
Example SOC pinout
Agilent 93000 TPPA enables:
Concurrent Test*SOC DFT sets up the cores for independent operation during test, allowing them to be executed concurrently using the 93000 TPPA. Can reduce test time typically by 30-50%.
SoCBIST DiagnosticsSynopsys’ SoCBIST is a SOC DFT technique that reduces the number of vectors by 100-400x and test time by over 10x. Diagnostics of failures detected by SoCBIST requires a 93000 TPPA enabled capability called “Selective BIST Capture.”
BIS
T C
on
trol
1G
b S
eri
al
JTA
G S
can
Port
800 M
Hz c
lock
50M
Hz c
lock
An
alo
g I
nstr
um
en
t
* Concurrent test requires an additional charge software license
Agilent 93000 Test Processor Per Pin Architecture (TPPA) - what it means for SOC DFT