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Topics
Review of VHDL
Discussion of simulation test methods
Advantages of HDL-based design
Discussion of current design methodologies
Presentation of an example design using VHDL
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What is VHDL?
VHDL is a Hardware Description Language used to capture the design in a technology independent medium.
The VHDL design is targeted to the FGPA or ASIC through synthesis.
RTLVHDLRTL
VHDL
SYNTHESISSYNTHESIS
FPGAFPGA
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What is VHDL? (2)
VHDL is also a high-level language used to simulation test a device.
TESTBENCHTESTBENCH VHDLVHDL
The testbench is writtenin “behavioral VHDL”.
The design is writtenin “RTL VHDL”.
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Simulation Test Methods
BEHAVIORALTESTBENCH
BEHAVIORALTESTBENCH
RTL VHDLRTL VHDL
BEHAVIORALTESTBENCH
BEHAVIORALTESTBENCH
RTL VHDLRTL VHDL
SIMULATORSTIMULUSCOMMANDS
DESIGN(SCHEMATIC OR OTHER)
DESIGN(SCHEMATIC OR OTHER)
Stimulus Design
Non-portable
Complex
Simple
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Modern Design Methodology Using HDL’s
CODEVHDL
BLOCK
CODEVHDL
BLOCK
SIMULATION TEST
BLOCK
SIMULATION TEST
BLOCK
SYNTHESISSYNTHESIS
VENDORPLACE &ROUTE
VENDORPLACE &ROUTE
STATICTIMING
ANALYSIS
STATICTIMING
ANALYSIS
TIMINGSIMULATION
TIMINGSIMULATION
BLOCKS
DONE?
BLOCKS
DONE?
START
SYSTEM-LEVEL
SIMULATION
SYSTEM-LEVEL
SIMULATION
yes
no
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Advantages of HDL-Based Design
Technology independence
Re-use of Intellectual Property
Advantages of high-level language design
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Technology Independence
Vendor independence through synthesis
MAP TO TARGET
TECHNOLOGY
MAP TO TARGET
TECHNOLOGY
RTLVHDL OPTIMIZE
LIBRARYLIBRARY CONSTRAINTSCONSTRAINTS
GATE-LEVELNETLIST
OPTIMIZE
MAP TO BOOLEANMAP TO
BOOLEAN
$ Allows vendor decisions to be based upon both cost and technology
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Technology Independence (2)
Allows for FPGA to ASIC, and FPGA to FPGA retargetting simply by re-synthesizing
$ Not having to recapture the design saves substantial time.
$ Masked gate arrays can cost substantially less than FPGAs for high-volume applications.
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High-Level Language Design
Easier design entry(count <= count + 1)
$ Faster design is faster time to market
Use of high-level language for simulation test pseudo-code stimulus file I/O for regression testing, etc. dynamic protocol checking timing checks
$ Debug is more effective during simulation than in the lab due to visibility.
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Re-use of Intellectual Property
Applicable for both stimulus (BFM’s) and RTL (the design)
Complex functions: bus interfaces memory controllers proprietary blocks purchased IP
Simple functions: decoders parity generators readback muxes
Advanced VHDL features for IP creation (GENERATE, GENERIC)
$ Long term savings
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Current Methodologies in Use
A mixture of AHDL, schematics, and proprietary vendor tools Vendor specific Difficulties applying multiple
engineers
$ Being tied into one vendor eliminates the “playing card” for the supply chain
$ Can’t take advantage of technology advances from different vendors
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Current Methodologies (2)
FPGAFPGASIMULATORSTIMULUSCOMMANDS
Test method Single device test Stimulus method proprietary Little or no protocol/timing checks No modeling of purchased
components
$ Longer debug time
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An Example Design- A Marine Radar Tracker/Detector
RMWSRAM
CONTROLLER
RMWSRAM
CONTROLLER
BEAMRULESBEAMRULES
TRACKERTRACKER
PULSERULES
PULSERULES
AUTOACQUIREAUTO
ACQUIRE
TRACKMEM
TRACKMEM
ACQMEM
ACQMEM
TRACKWINDOW
MEM
TRACKWINDOW
MEM
RANGE
WIDTH
SUM
MOMENT
BUSINTERFACE
BUSINTERFACE
EXTERNALSRAM
EXTERNALSRAM
BEAMVIDEO
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Example Design - Simulation Testbench
TARGETTRACKER DETECTOR
FPGA
TARGETTRACKER DETECTOR
FPGA
SRAMSRAM
VIDEOGENERATOR
VIDEOGENERATOR
PROCESSORBFM(68K)
PROCESSORBFM(68K)
-- normalize start and end test */
starttest := starttest - 1;endtest := endtest - 1;currenttest := starttest;
-- Put CW2 in TRAINING modewrite(CW2_REG, CONV_SLV(INTERN_DSYNC,16), cyc);
-- Set errors to 0err.errors := 0;-- perform all desired testsdo_all_tests : WHILE currenttest <= endtest and err.errors = 0 LOOP write(linedata, STRING'("Starting test #")); write(linedata,currenttest+1); writeline(output,linedata);
err.test := currenttest; tst_ctrl(tib(currenttest), err, ret_data, cyc); currenttest := currenttest + 1;END LOOP do_all_tests;