Download - Track e low voltage sram - adam teman bgu
May 4, 2011
Low Voltage SRAM Design
Challenges and Solutions
May 4, 2011
Adam Teman, Janna Mezhibovsky, Dr. Alexander FishLow Power Circuits and Systems Lab (LPC&S)
The VLSI Systems CenterBen-Gurion University
May 4, 2011
Lecture Contents
• Introduction
• Standard SRAMs at Low Voltages
• Existing Solutions
• LPC&S SRAM Design Activities
May 4, 2011
Introduction
• SRAMs are one of the main on-chip power consumers, often comprising 50% of silicon area and 50% of static power.
www.anandtech.comTotal cache size per chip
May 4, 2011
Introduction
• The standard SRAM implementation is the 6T bitcell. Both write and read power are quadratically dependenton VDD.
M2 M5
M3
M1
M6
M4
BLBBL
Q QB
WL WL
2
read WL DD BL DD swing SAE C V C V V E
2 2
write WL DD BL DDE C V C V
May 4, 2011
Introduction
• During hold cycles, the 6T SRAM presents both subthreshold (DIBL) and gate leakage.
• Both are exponentially dependent on supply voltage.
32
328 2 1 1
exp3
GBox B
B
GB
GB ox
Vm
IhqV t
(1 )
GS T DS DS
t t t
V V V V
nv v nv
subI e e e
DIBLGate Bias and
Oxide Thickness
May 4, 2011
M2 M5
M3
M1
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M4
BLBBL
Q QB
WL WL
0 VDD
VDD VDD
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M3
M1
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M4
BLBBL
Q QB
WL WL
0 VDD
VDDVDD
Introduction
• Cutoff Devices with VDS=VDD
suffer from DIBL.• Devices with VGB=VDD suffer
from Gate Leakage.
May 4, 2011
Introduction
• The best way to aggressively reduce SRAM power is to lower the operating voltage.
– Quadratic reduction of Dynamic Power
– Exponential Reduction of DIBL
– Exponential Reduction of Gate Leakage
May 4, 2011
Standard SRAMs at Low Voltages
• The positive feedback of the 6T structure provides strong bi-stability and large noise margins.
QB
[V
]
VDD
VDD0
Q [V]
May 4, 2011
Standard SRAMs at Low Voltages
• However, under read and write operations, the noise margins are depleted.
QB
[V
]
VDD
VDD0
Q [V]
QB
[V
]
VDD
VDD0
Q [V]
May 4, 2011
Standard SRAMs at Low Voltages
• Read and write accesses are ratioed operations and require two basic drive strength constraintsto succeed.
M2
M1
BL=VDD
Q=0
WL=VDD
QB=VDD
M2
M3
BL=0
Q=VDD
WL=VDD
QB=0
Read Constraint
K1>K2Write Constraint
K2>K3
May 4, 2011
Standard SRAMs at Low Voltages
• Under strong-inversion operation, sizing the devices is usually sufficient.
• However, global and local mismatch cause loss of functionality at voltages under ~700mV-800mV
M2
M3
BL=0
Q=VDD
WL=VDD
QB=0
M2
M1
BL=VDD
Q=0
WL=VDD
QB=VDD
M2
M3
BL=0
Q=VDD
WL=VDD
QB=0
Read Constraint
K1>K2Write Constraint
K2>K3
May 4, 2011
Existing Solutions
• The basic solution to the read margin problem is decoupling the readout path.
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WBLBWBL
QQB
WWLWWL
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RWL
RBL
May 4, 2011
Existing Solutions
• A differential decoupled readout provides better Sense Amplifier operation:
AL1 AR1
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M1
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M4
BL
QQB
WWL WWL
AR2
WL
NR
AL2
WL
NL
VGND
BLB
May 4, 2011
Existing Solutions
• Write margin still limits 8T operation to ~700mV, therefore write assist techniques are required.
M2M6
M3
M1
M5
M4
BLBBL
QQB
WWLWWL
M8
M7
RWL
M9
M10
VVDD VVDDRBL
Virtual Supply
May 4, 2011
Existing Solutions
• Word Line boosting and RSCE sizing have been implemented to improve 8T functionality.
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M3
M1
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M4
WBLBWBL
QQB
WWLWWL
M8
M7
RWL
RBL
Boosted WL
RSCE
May 4, 2011
Existing Solutions
• Several readout path implementations have been proposed to fight off-row leakage.
QB
M8
M7
RWL
RBL
M9QB
QB
M8
M7
RWL
RBL
M9QB
M10 QB
M8
M7
RWL
RBL
M9
M10
May 4, 2011
Our work
• Very few groups have tried to “think outside the box” and modify the internal cell structure.
• We have proposed an internal supply feedback concept that cuts off the supply to reduce internal leakage.
May 4, 2011
Our work
• One example is the Quasi-Static RAM cell that floats the internal nodes, drastically reducing leakage.
• This and other solutionsare under intensiveexamination and testing.
M9
M4M1
M6M3
M5M2
WB
L
WB
LB
WW
L
WW
L
M7
M8
RW
L
RB
L
QBQRB
VVDD
May 4, 2011
Questions?
