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Using the Enhanced Local Bus Controller "eLBC" in PowerQUICC and/or QorIQ Processors
June, 2010
Zhongcai ZhouApplication Engineer
FTF-NET-F0809
TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Agenda
►eLBC Overview►General Purpose Chip-
select Machine (GPCM)►NAND Flash Control
Machine (FCM)►User Programmable
Machine (UPM)
22
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How to Use the Enhanced Local Bus Controller (eLBC) in PQ and/or QorIQ
►After the power is turned on, a typical system:1. Starts execution from non-volatile memory, typically flash memory 2. Copies/loads the code to main memory (DDRx)3. Starts the execution from the main memory
Core
FlashU-boot/BIOS
Main MemoryDDRx
1
StorageROMzz/Hard Drive
2
3
3
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System Must Talk to Flash Memory Without Any Configuration
►A system must be able to talk to non-volatile memory without any configuration steps
►eLBC is the controller that does this initial booting job• eLBC has three controllers:
1. General purpose chip-select machine (GPCM)– Regular NOR flash for booting– SRAM or FPGA
2. NAND flash control machine (FCM)– NAND memory for storage and/or booting
3. User programmable machine (UPM)– FPGA, ZBT RAM, etc.
4
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eLBC Diagram
5
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Basic Operation
► A transaction request comes to the local bus with address/size/read-write
► The address is compared against the BRx and ORx to determine which bank(#CS) this address belongs to
• There is one BR/OR pair for each bank(#CS)► The transaction is routed to the corresponding controlled determined by BR[MSEL]
BRx
AM Controller dependentORx
BA: Base AddressPS: Port SizeV : ValidAM: Address MaskMSEL: Machine Select
000 GPCM 101: UPMB001 FCM 110: UPMC100: UPMA others: Reserved
6
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Boot from eLBC
► Flexibility of programming each CS to any one of the controllers (GPCM, FCM, UPMA, UPMB, UPMC)
► CS0 is specialIf the device is configured to boot from the local bus, then the boot ROM, either flash or NAND, must be connected to /CS0
BR0 and OR0 will be set by the hardware automatically to appropriate value:
7
BR0[PS] BR0[MSEL] BR0[V] FCM: OR0[PGS]
Boot from GPCM8-bit ROM
8-bit(01) GPCM(000) 1 x
Boot from GPCM16-bit ROM
16-bit(10) GPCM(000) 1 x
Boot from NAND8-bit small page
8-bit(01) FCM(001) 1 Small page(0)
Boot from NAND 8-bit large page
8-bit(01) FCM(001) 1 Large page(1)
Boot from non-eLBC interface
x x 0 x
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Boot from eLBC (cont.)
►OR[AM] set to all 0This means all the address bits are masked and not used for the comparison. Any address hits bank 0. The bank size is 4 GB.
►How about timing?GPCM or FCM is set most conservatively in terms of timing out of reset. This guarantees that GPCM or FCM can talk to any flash or NAND.
►The boot code should shrink the bank size and adjust the timing according to the specific boot memory used to speed up the booting process.
8
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Key Feature of eLBC
►Address and data are big-endian indexedLAD[0:31]: LAD[0] is the MSB; LAD[31] is the LSBLA[16:31]: LA[16] is the MSB, LA[31] is the LSB
►Buffer controlLBCTL: The LBCTL pin functions as a write/read control for a bus transceiver connected to the LAD lines
►Register writing and local bus request are two different ports. The race condition is possible.For example, in the code:
write(eLBC register)read from eLBC
eLBC could start the read before write32 takes effect. Change to:write(eLBC register)read(same eLBC register)read from eLBC
9
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Key Feature of eLBC: It Is a Multiplexed Bus
► Address and data are multiplexed in the same pins to reduce pin counts.► LALE (Local bus Address Latch Enable): Indicates the address phase
• There are two main variations:
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32-bit bus:LAD[0:31]LA[25:31]
latchlale
lad[0:26] la[0:26]
la[25:31]
la[0:31]
16-bit bus:LAD[0:15]LA[16:31]
latchlale
lad[0:15] la[0:15]
la[16:31]
la[0:31]
Advantage: Fewer pins, narrower latchAdvantage: Higher performance
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Key Feature of eLBC (cont.)
► Port size and address connection• This applies to GPCM and UPM• 1 MB Flash
LA[31]
LAD[0:7]
A18
A0LA[30]
LA[12]
8-bit port
LA[30]
LAD[0:15]
A18
A1LA[29]
LA[12]
16-bit port
LA[29]
LAD[0:31]
A17
A1LA[28]
LA[12]
32-bit port
A-1 A0 A0
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Key FEATURE of eLBC
►Debug feature• When an error happens, the transaction info is logged into:
LTEAR ( Transfer Error Address Register)LTEATR (Transfer Error Attributes Register)
►Bus monitor
12
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General Purpose Chip-select Machine (GPCM)
►The simplest among the three controllers
►Designed to interface to flash devices
►Typical flash signals and timing (from a flash device datasheet)
13
Generic Flash Read Timing Generic Flash Write/Program Timing
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GPCM Timing Control
► GPCM needs to control the relative timing between the address, /CS, /WE, /OE signals
► All the timings are controlled by OR register
CSNT: /LCS and LWE negation timingACS: Address to /CS setup timeXACS: Extra address to /CS setup timeTRLX: Timing relaxedEHTR: Extended hold time on read accessEAD: LALE width control
14
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There is a table in the manual listing the timings for all the parameter combinations.
► tARCS• Mainly controlled with OR[ACS]• Recommended to set to ACS=00
tAwCS=0• This gives one cycle address to /CS setup
time (address starts with LALE assertion). Sufficient for flash
► tAOE • At least one cycle. Sufficient for flash• No programming needed
► tRC/tCSRP • Mainly determined by OR[SCY]• Programmed according to flash speed
► tOEN• Controlled with OR[CSNT] • There is one automatic cycle between a read
and next transaction• Program to 0 for most flashes• Only flash that shuts off very slowly after read
needs to add extended cycles
How to Program GPCM Read Timing
Read Timing15
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How to Program GPCM Write Timing
There is a table in the manual listing the timings for all the parameter combinations.
► tAWCS• Mainly controlled with OR[ACS]• Recommended to set to ACS=00
tAwCS=0• This gives one cycle address to /CS setup
time (address starts with LALE assertion). Sufficient for flash
► tAWE • At least one cycle. Sufficient for flash• No programming needed
► tWC/tCSWP • Mainly determined by OR[SCY]• Programmed according to flash speed
► tWEN• Controlled with OR[CSNT] • Program to 0 for most flashes
16
Write Timing
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Connection Example: Both NAND and NOR
17
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Key Feature of GPCM
►External GTA termination• GPCM is terminated by programmed cycle number or LGPL4/GTA if
asserted earlier.• OR[SETA] =‘1’: GPCM ignores OR[SCY] and terminated by GTA only.• This feature is useful for some devices that have variable access time.
►Why do we need LA[27:31]?
►No support for burst• What happens if a burst request goes to GPCM?
18
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NAND Flash
►Overview of NAND flash• Higher density than regular flash (NOR flash)• IO device using commands to read/write
No address busPage-oriented, not suitable for random accessNo execute in place
• Possible bit error Usually a certain number of blocks are marked bad by the manufacturerDuring the operation, more blocks can go badECC is a must
19
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NAND FCM Connection
Note: Data bus must be bit reversed.
CE: Chip EnableCLE: Command Latch EnableALE: Address Latch EnableObservation: There is no address bus
WE: Write EnableRE: Read Enable
20
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How to Read NAND
cmd1 cmd2
21
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How to Write NAND
22
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Observations
►Different vendors might have slightly different sequences.
►The commands might be different.
►In order to talk to all the vendors, FCM takes a generic approach. User has the flexibility/responsibility to define the command sequence.
►512K vs. 2K
23
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How FCM Operates
►Internal 8K buffer. Data is exchanged through buffer normally. User has the option to read/write single byte from MDR register.
• For large page size NAND, 8K is split into two 4K-buffers.4K-buffer: 2K for main region, 64 bytes for spare.
• While one 4K buffer is exchanging data with NAND, the core can access the other 4K-buffer.
• For small page sizes, there are 8 1K-buffers.
24
NANDcore
4K
4K
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How FCM Operates
►Write data1. Initialize FCM registers for write2. Set FMR[OP]=00, normal operation
Write to the buffer3. Set FMR[OP]=11 after the data (usually one whole page)
is in the buffer4. Dummy write to memory bank
or write to LSOR to start the write sequence5. FCM reads data from buffer, writes to NAND
25
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How FCM Operates
►Read data1. Initialize FCM registers for read2. Set FMR[OP]=113. Dummy write to memory bank
or write to LSOR to start the read sequence4. When the data read is finished, the status bit is set5. Set FMR[OP]=00, normal operation
read data from the buffer
26
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Programming Model
►Command sequence control
►Timing control
27
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Command Sequence Control
0000: NOP. End of sequence 1000: WB. Write FBCR bytes
0001: CA. Column Address 1001: WS. Write one byte
0010: PA. Block+Page address 1010: RB. Read FBCR bytes
0011: User-defined address 1011: RS. Read one byte
0100: CM0. Cmd from FCR[CMD0] 1100: CW0. Wait R/B. Issue FCR[CMD0]
0101: CM1. Cmd from FCR[CMD1] 1101: CW1. Wait R/B. Issue FCR[CMD1]
0110: CM2. Cmd from FCR[CMD2] 1110: RBW. Wait R/B. Read FBCR bytes
0111: CM3. Cmd from FCR[CMD3] 1110: RSW. Wait R/B. Read one bytes
28
►Flash instruction register (FIR)
FCM starts with OP0, until it encounters OPx=0000 User must program the sequence according to the NAND datasheet.
OP definition
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Command Sequence Control Example
►Read sequence programming (slide 19)
FCR CMD0 CMD1 CMD2 CMD3
0x00 0x30
FIROP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
CM0 CA PA CM1 RBW NOP
0100 0001 0010 0101 1110 0000
For CA (column address), the controller handles the lengthautomatically according to ORx[PGS], the page size field. It is one cycle for small-page NAND and two cycles for large-page NAND.
For PA (page address)The controller handles the length based on FMR[AL].
29
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Command Sequence Control Example
►Write sequence programming (Slide 20)
FCR CMD0 CMD1 CMD2 CMD3
0x70 0x80 0x10
FIROP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
CM1 CA PA WB CM2 CW0 RS NOP
0101 0001 0010 1000 0110 1100 1011 0000
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Timing Control: Command/Address/Data Write
►The timing is controlled by OR[CST], OR[CHT], OR[TRLX].• There is a table in the manual listing all the combinations.
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Timing Control: Data Read
►The timing is controlled by OR[RST], OR[TRLX].• There is a table in the manual listing all the combinations.
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Boot from NAND
►When eLBC is configured to boot from NAND• FCM automatically reads 4K data from NAND to the buffer• Core waits until this 4K transfer finishes, then executes the code out of
this 4K buffer• This 4K code cannot call the function outside of the 4K range. It needs
to copy the rest of the code to DDR and continue the bootstrap process
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
User Programmable Machine (UPM) Controller
►Very flexible timing
►Supports burst• Better performance than GPCM
►There are three independent UPMs.
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Basic Principle of Operation
UPM Routine Start Address
Read single-beat 0x00
Read burst 0x08
Write single-beat 0x18
Write burst 0x20
Refresh Timer 0x30
Exception Condition 0x3C
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Programming Model
►UPM reads the appropriate RAM array based on the transaction type: read/write, single/burst
►RAM array instructs the controller what level to drive to each signal
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Programming Model: RAM Array
►Basic Timing• CST1-4: LCS level at phase 1-4• BST1-4: LBS level at phase 1-4
These two signals can be controlled to a resolution of a quarter of LCLK.
• G0L/H: LGPL0 level control• G1-5T1: LGPL1-5 level at phase 1 and 2• G1-5T3: LGPL1-5 level at phase 3 and 4
These signals have resolution of half clock
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
INDEX
CST1
CST2
CST3
CST4
BST1
BST2
BST3
BST4
G0L
G0H
G1T1
G1T3
G2T1
G2T3
G3T1
G3T3
G4T1
G4T3
G5T1
G5T3
0 1 0 1 1 1 1 0 0 10 11 0 1 0 1 0 1 0 1 0 1
1 1 1 0 0 0 0 1 1 11 10 0 0 1 0 1 0 1 0 1 0
T1 T2 T3 T4 T1 T2 T3 T4LCLK
LCS
LBS
LGPL0
LGPL1
Basic Timing Control
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
RAM Array (cont.)
Advanced features:► There are only 8-entries for single read/write, 16-entries for burst read/write.
• If this is insufficient, thenREDO: Redo current RAM array once, twice, three timesLOOP:
RAMx LOOP=1, loop start………………RAMy LOOP=1, loop endLoop Number: MxMR[RLF] for read and MxMR[WLF] for write
• If this is insufficient, then REDO:LOOP:
RAMx LOOP=1, loop start………………RAMy LOOP=1, loop endLoop Number: MxMR[RLF] for read and MxMR[WLF] for write
NA: Next address. Increment LA[27:31]/UTA: UPM TA assertionLAST: Last entry
► Less common/useful fields:• EXEN: Exception enable• AMX: Address muxing• TODT: Turn-on disable timer
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TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
UPWAIT
►LGPL4/UPWAIT • UPM supports wait signal to handle variable-speed devices• LGPL4/UPWAIT can be programmed as either
LGPL4, an outputUPWAIT, an input
►Polarity of UPWAIT is programmable (MxMR[UWPL)
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TM