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VHDL Very High Speed Integrated Circuit Hardware Description Language
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Introduction
VHDL
Texas Instrument
intermetricsIBM
Under US department of Defense order for High speed ICs
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Introduction
VHDL is a language forSimulationSynthesisDocumentation
of complex digital systems.
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VHDL Standards
IEEE std 1076-2002 The latest language reference
manual Not much different from 1993
IEEE std 1076-1993 Most tools uses it. Used in this tutorial
IEEE std 1076-1987 Old standard, almost obsolete.
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VHDL/FPGA Design Flow
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Design Entity
A component or a system to be designed is a VHDL “design entity”
VHDL divides entities into two parts: External (interface): how it connects to
other components Internal (architecture): how it behaves
and how it is implemented Behavioral Structural Hybrid
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Design Entity
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Example
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Example(cont’d)
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Example(cont’d)
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Example(cont’d)
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Example(cont’d)
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VHDL Construct
Entity definition Architecture definition Configuration Process Subprogram Package A VHDL design can be broken into
multiple files. Each file contains entity and architecture definitions, or packages.
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Expressions
An expression is a formula that specifies how to compute a value. Example (D**3) + ((A*B) mod 2)
VHDL operators:
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Defining scalar types
Syntax:Type identifier is range expression {to|downto} expression;Type identifier is ( list_of_items );Subtype identifier is type_name range expression {to|downto} expression;
ExampleType opcode is (nop,load,store,add,subtract,negate,branch,halt);Type system_state is (unknown, idle, busy, ready);Type bit is (‘0’, ‘1’);Type boolean is (false,true);Type std ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);Subtype small_int is integer range –128 to 127;Subtype bit_index is integer range 31 downto 0;Type frequency is range 0 to 1e15
Units hz; khz=1000 hz; mhz=1000 khz; ghz=1000 mhz;End units;
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arrays
An array is an ordered collection of elements of the same type.
Two types of array can be defined Constrained arrays:
Type word is array (0 to 15) of bit; Type byte is array (7 downto 0) of bit; Type ram is array (0 to 16#FFFF#) of byte; Type int array is array (1 to 100) of integer;
Unconstrained arrays Type bit_vector is array (natural range <>) of bit; Type string is array (positive range <>) of
character; Type std_ulogic_vector is array (natural range
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Array Elements & slices
Example:Variable B : bit_vector(7 downto 0);
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Array operations
Shift, rotate and concatenate examples
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Simulation Example
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VHDL Statements
VHDL has two kinds of statements Sequential statements: they are
executed one after another, like C or Pascal. Signal and variable assignments, flow
control constructs (if, case,while, loop, …), subprogram call, wait
Concurrent statements: all are executed at the same time. Processes, block statements, component
instantiations, generate statements, concurrent assignments and concurrent procedures
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Syntax
Entity:entity entity_name is [ generic (generic_declarations); ] [ port (port_declarations); ]end [entity] [entity_name];
Generic:generic ( [constant_name : type [:=value]] { ; constant_name : type [:=value] } );
Port:port ( [ port_name : port_mode type { ; port_name : port_mode type } ] );
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Syntax
Port Modes: In : port can only be read Out : port can only be assigned Inout : Can be read and
assigned a value. The value read is not the assigned value.
Buffer : Similar to out, but can be read
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Syntax
Architecturearchitecture architecture_name of entity_name is { declarative_item }begin { concurrent_statement }end [architecture_name];
A declarative item can be any of these: Use clause Subprogram declaration and body Type or subtype declaration Constant declaration Signal declaration Component declarationShiraz University of shiraz spring 2011
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Syntax Process
[label:] process [( sensitivity_list )] { process_declarative_item }begin { sequential_statement }
end process; The sensitivity list is a list of signals
read by the process. The process declarative items can
include: Use clause Subprogram declaration and body Variable and constant declaration Type and subtype declaration
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Signlas “Signals” carry information among
processes and components in an architecture.
Signal declaration syntaxsignal signal_name : signal_type
[:=expression]; signal address : bit_vector(31 downto 0); signal mem_read : bit := ‘0’;
Signal assignment syntax[Label:] signal_name <= value [after
time_expression]
address <= x”18FE5900” after 20 ns;mem_read <= ‘1’;data_reg <= ”1101_0010”;
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Example
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Array Attributes
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Wait Statement Wait causes a process to wait for an
event Syntax
wait [on signal_name {,signal_name}];wait [until boolean_expression];wait [for time_expression];
Examplewait on a,b;wait until clk=‘1’ and clk’event;wait for 100 us;wait;
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Wait Statement
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if Statement Syntax
[label]:if boolean_expression then {sequential_statement}elsif boolean_expression then {sequential_statement}[else {sequential_statement} ]end if [lable];
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Example
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Case Statement
Syntax[Label:]case expression is
{ when choice => {sequential_statement} }end case [label];
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Example
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Loop, While & For Statement
Syntax[label:] loop
{sequential_statement}end loop [label];
Syntax[label:] while condition loop
{sequential_statement}end loop [label];
Syntax[label:] for identifier in discrete_range loop
{sequential_statement}end loop [label];
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Example
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Next, Exit, Null
Syntax[label:] next [when boolean_expression];[label:] exit [when boolean_expression];[label:] null;
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Example
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Concurrent Signal Assignment
Conditional signal assignment[label:] Signal_name <= { value when
boolean_expression else } value [when boolean_expression];
Selected signal assignment[label:] with expression selectsignal_name <= { value when choices}value when choices;
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Example
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Subprograms
Procedures Generalize a statement Encapsulate a collection of sequential
statements that are executed for their effect
Functions Generalize an expression Encapsulate a collection of sequential
statements thatcompute a result
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Procedures
Syntaxprocedure identifier [ ( parameter_list ) ] is{ declarations }begin{ sequential statements }end [procedure];
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Example 1
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Example 2
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Example 3
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Functions
Syntax[pure|impure] function identifier [ ( parameter_list ) ]return type_name is
{ declarations }begin
{ sequential statements }end [function] [identifier];
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Example
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IEEE Std_Logic Multivalued logic:
‘U’ : Uninitialized ‘X’ : Forcing Unknown ‘0’ : Forcing Zero ‘1’ : Forcing One ‘Z’ : High Impedance ‘W’ : Weak Unknown ‘L’ : Weak Zero ‘H’ : Weak High ‘-’ : Don’t care
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;Shiraz University of shiraz spring 2012
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IEEE Std_Logic Std_logic Resolution Table
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State Machine Finite State Machines:
Moore Mealy
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State Machine Example 1 Moore
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State Machine Example 1
Moore
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State Machine Example 2
Mealy
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State Machine Example 2
Mealy
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Questions?
THANKS
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