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IEEE 802.15.4 and cc2420
By
Salah
Borrow slides!
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Constraints in WSNLimited Power
If it is battery powered Computation power
Higher the frequency, higher the power consumptionMemory
> 100 KB code size> 10 KB RAM sizeCost is proportional to the memory size
Time constraintsMany applications has time constraints (Real-time)
You must turn off radio for some time. Otherwise it wouldn’t last for too long
You cannot do complicated algorithm on one node
Cost is very important for the success of wireless sensor network
You must finish something within some time
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OSI ModelIn computer networkIn WSN
Due to the constraints, usually we have only three layers for data transmission
Application specificUse the protocols
that fits your needConsider routing and
MAC together to achieve better performance
Physical
MAC
Routing
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Physical LayerHow the bits transmit in real physical worldFor wireless communication, it defines
Operating frequency 2.4 GHz, programmable channel for Taroko
Modulation/demodulation methodPhysical data rate
250 kbps Transmission power
Programmable How the radio chip detect a valid data packet
Synchronization headerPreambleSYNC
Synchronization header
LengthData
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MACMedium Access Control
Control the access of a shared channel
Wireless channel are shared among different nodesOne node access the
shared channel at a timeTwo nodes send packet
at the same time, both packet will drop (usually)
Need a mechanism to control the usage of the channel
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Contention BasedNo specific schedule, a node will try to send packet
when it needs to sendCSMA: Carrier Sense Multiple Access
C wants to send to D But A is sending packets to B C listen to the channel It can hear A is sending So C backoff and wait When the channel is clear C sends packets to D
B
A
D
C
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Turn-off RadioPower consumption while listening
IEEE 802.15.4: approximate 19 mAFor two AAA batteries with 1600 mAh capacity
Out of power in 84 hours if radio is always onIf these are you requirements
Battery poweredLong time operation without replace/recharge battery
Then, you MUST turn-off radio periodically
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S-MACS-MAC
listen – sleep – listen – sleepUse RTS-CTS-DATA-ACK
Trade throughput and latency for energy
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B-MACKey: Low Power Listening (LPL)
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B-MACCSMA (no RTS-CTS)Improves over S-MAC
Higher ThroughputLower LatencyLess energy consumption
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TDMATime divided
multiple accessDivided into time
slotsTDMA require Time
synchronization
I
B
A
L
G
K
M
E
J
F
D
H
C
TimeA sends; B, C, F
listenC sends; A, G, M
listenE sends; J, B, L, K listen
Nodes that do not listen or send, go to sleep
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CC2420 FeaturesIEEE 802.15.4 compliant250 kbps effective data rateHardware MAC encryption (AES-128)Programmable output power2400 – 2483.5 MHz
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MAC Hardware Support802.15.4 MAC hardware support:
Automatic preamble generatorSynchronization word insertion/detectionCRC-16 computation and checking over the MAC
payloadClear Channel AssessmentEnergy detection / digital RSSILink Quality IndicationFull automatic MAC security(CTR, CBC-MAC, CCM)Stand-alone AES encryption
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IEEE 802.15.4 and ZigbeeIEEE 802.15.4
Wireless MAC and PHY specifications for low-rate wireless personal area networks (LR-WPANs)
Zig
Bee
…8
02.1
5.4
Layer 7: ApplicationLayer 7: Application
Layer 6: PresentationLayer 6: Presentation
Layer 5: SessionLayer 5: Session
Layer 4: TransportLayer 4: Transport
Layer 3: NetworkLayer 3: Network
Layer 2: Data Link • (MAC)
Layer 2: Data Link • (MAC)
Layer 1: Physical (PHY)Layer 1: Physical (PHY)
OSI 7-Layer
IEEE 802.15.4 MAC
IEEE 802.15.42400 MHz PHY
IEEE 802.15.4868/915 MHz PHY
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868MHz / 915MHz PHY
2.4 GHz
868.3 MHz
Channel 0 Channels 1-10
Channels 11-26
2.4835 GHz
928 MHz902 MHz
5 MHz
2 MHz
2.4 GHz PHY
IEEE 802.15.4 PHY
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PreambleSYNC
Synchronization header
LengthData
Typical Data Transmit
Transmitter Receiver
listen
PreambleSYNC
Synchronization header
LengthData
Somebody wants to send somethingData Frame startLength of the data
PreambleSYNC
Synchronization header
LengthData PreambleSYNC
Synchronization header
LengthData
Receive data
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PHY Packet Fields• Preamble (32 bits)• Start of Packet Delimiter (8 bits)• PHY Header (8 bits) – PSDU length• PSDU (0 to 1016 bits) – Data field
IEEE 802.15.4 Packet
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IEEE 802.15.4 MAC
Full function device: can do routing
Reduced function device: end device, cannot do routing
Peer-Peer TopologyStar Topology
PAN Coordinator: (1) every network should have at least one coordinator (2) Other devices joint the coordinator they found (3) PAN Coordinator assign a 16 bit network to the device
IEEE 802.15.4 Addressing: MAC address: 64-bit Network address: 16-bit PAN identifier: 16-bit
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IEEE 802.15.4 Device Classes
Full function device (FFD) Any topology PAN coordinator capable Talks to any other device Implements complete protocol set
Reduced function device (RFD) Limited to star topology or end-device in a
peer-to-peer network. Cannot become a PAN coordinator Very simple implementation Reduced protocol set
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IEEE 802.15.4 Definitions
Network Device: An RFD or FFD implementation containing an IEEE 802.15.4 medium access control and physical interface to the wireless medium.
Coordinator: An FFD with network device functionality that provides coordination and other services to the network.
PAN Coordinator: A coordinator that is the principal controller of the PAN. A network has exactly one PAN coordinator.
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Low-Power Operation
Duty-cycle control using superframe structure Beacon order and superframe order
Coordinator battery life extension
Indirect data transmission Devices may sleep for extended period
over multiple beacons Allows control of receiver state by higher
layers
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General MAC Frame Format
Octets:2 1 0/2 0/2/8 0/2 0/2/8 variable 2Destination
PAN identifier
Destination address
Source PAN
identifier
Source address
MAC payload
MAC footer
Frame check
sequence
MAC header
Addressing fields
Frame control
Sequence number
Frame payload
Bits: 0-2 3 4 5 6 7-9 10-11 12-13 14-15
Frame typeSequrity enabled
Frame pending
Ack. Req. Intra PAN ReservedDest.
addressing mode
ReservedSource
addressing mode
Frame control field
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Beacon Frame Format
Bits: 0-3 4-7 8-11 12 13 14 15Beacon
orderSuperframe
orderFinal CAP
slotBattery life extension
ReservedPAN
coordinatorAssociation
permit
Octets:2 1 4 or 10 2 variable variable variable 2
MAC footer
Frame check
sequence
MAC header
Source address information
MAC payload
Superframe specification
GTS fields
Pending address
fields
Frame control
Beacon sequence number
Beacon payload
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MAC Command Frame
Command Frame Types Association request Association response Disassociation
notification Data request PAN ID conflict
notification
– Orphan Notification– Beacon request– Coordinator realignment– GTS request
Octets:2 1 4 to 20 1 variable 2
MAC footer
Frame check
sequence
Frame control
Data sequence number
Address information
MAC header MAC payload
Command type
Command payload
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Data Frame Format
Acknowledgement Frame FormatOctets:2 1 2
MAC footer
Frame check
sequence
MAC header
Frame control
Data sequence number
Octets:2 1 4 to 20 variable 2
MAC PayloadMAC
footer
Data payloadFrame check
sequence
MAC header
Frame control
Data sequence number
Address information
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Inter-frame Spacing
For frames ≤ aMaxSIFSFrameSize use short inter-frame spacing (SIFS)For frames > aMaxSIFSFrameSize use long inter-frame spacing (LIFS)
Long frame ACK Short frame ACK
tack LIFS tack SIFS
Acknowledged transmission
Long frame Short frame
LIFS SIFS
Unacknowledged transmission
aTurnaroundTime ≤ tack ≤ (aTurnaroundTime (12 symbols) + aUnitBackoffPeriod (20 symbols))LIFS > aMaxLIFSPeriod (40 symbols)SIFS > aMacSIFSPeriod (12 symbols)
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Slotted CSMA Procedure
NB = 0, CW = 0
Battery lifeextension?
BE = macMinBE
BE = lesser of(2, macMinBE)
Locate backoffperiod boundary
Delay forrandom(2BE - 1) unit
backoff periods
Perform CCA onbackoff period
boundary
Channel idle?
CW = 2, NB = NB+1,BE = min(BE+1, aMaxBE)
CW = CW - 1
CW = 0?NB>
macMaxCSMABackoffs?
Failure Success
Slotted CSMA
Y
Y Y
Y
N
N
N
N
Used in beacon enabled networks.
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Un-slotted CSMA Procedure
NB = 0,BE = macMinBE
Delay forrandom(2BE - 1) unit
backoff periods
Perform CCA
Channel idle?
NB = NB+1,BE = min(BE+1, aMaxBE)
NB>macMaxCSMABackoffs
?
Failure Success
Un-slotted CSMA
Y
Y
N
N
Used in non-beacon networks.
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General View
CC2420CC2420 MSP430F1611MSP430F1611
Power and reset control
SPI interface:
Status indication pins
Initialization: Turn on CC2420, setting the
register and memory Now CC2420 is in idle mode
Transmit Do your MAC layer operations Write the packet into the transmit
buffer Send a transmit command to
CC2420 Do your MAC layer operations
Receive Turn on receiver to listen If a packet arrive, after receive the
last byte of the packet, FIFOP interrupt will generate
Go to the FIFOP ISR, fetch the received packet from receive buffer
Do your MAC layer operations
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CC2420: RegistersCommunication: CC2420 MSP430F1611
SPI interface33 16-bit configuration and status registers
Configuration registers Initialization: make the device operate in the way you want
Status registers Get the status of the device
15 command strobe registersSingle byte instructions: ask the device to do somethingEg. “send packet”, “start encryption”
Two 8-bit FIFO(buffer) access registersAccess receive and transmit buffer
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CC2420: RAM Internal 368 bytes RAM
4 bytes blank (not used) 16 bytes IEEE802.15.4 addressing 112 bytes security bank 128 bytes receive FIFO 128 bytes transmit FIFO
IEEE802.15.4 addressing
security bank
receive buffer
Transmit buffer
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MSP430 SPIIt is similar to UART
Initial SPI module by setting proper registersCheck User guide for further detail
Send a byte to CC2420Write to U0TXBUF
Receive a byte from CC2420Write a byte to U0TXBUF Wait for U0RXBUF ready, read the byte from U0RXBUFYou must send a byte to CC2420 in order to read a byte
In SPI protocol, master must send something to push slave send data back
You don’t need receive interrupt (unlike UART)When will CC2420 know MSP430 wants to send something to
it?Pull the CSn pin low
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Access RegistersRegisters
Read/write registers
RAM (1)/Reg (0)
Read(1)/Write(0) Address
BIT 7 BIT 6 BIT 5:0
Register ValueSetting Register
0 0 Address
Register ValueRead Register value
0 1 Address
Status
send
Receive
Register ValueSend Command Strobe
0 0 Address
Status
send
Receive
send
Receive StatusStatus
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Access RAMRAM access:
Crystal oscillator must be running and stable for RAM access DO NOT use RAM access for FIFO
FIFO access: use FIFO access register (Tx: 0x3E, Rx: 0x3F)
Luckily, you don’t need to write these hardware access routines
RAM (1)/Reg (0) Address
BIT 7 BIT 5BIT 6:0
BankRead(1)/Read+Write (0)
X X X X X
BIT 7:6 BIT 4:0
DATA
Receive FIFO
0 0 111110
FIFO DATA
Transmit FIFO
0 1 111111
Status
send
Receive
send
Receive StatusStatus
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Status ByteStatus byte is returned
When MSP430 write something to CC2420Issue a SNOP command (do nothing, just to get the status
byte
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Preamble And SFD
Preamble IEEE802.15.4 standard: 4 bytes (0x00) Length of preamble is controlled by register: MDMCTRL0 Programmable length from 1 to 16 bytes
For IEEE 802.15.4, it is set to 3 bytes long Don’t set it to less than 3 bytes
Each byte is 2 zero-symbols Each symbol is 16μs
SFD IEEE 802.15.4 standard: 1 byte (0xA7) Programmable by register: SYNCWORD SYNCWORD is two bytes long
When used in IEEE 802.15.4: one byte for preamble, another for SFD
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Frame Length And FCFFrame length field: 7-bit
Frame Control Field (FCF)Compliant to IEEE 802.15.4
Reserved Frame length
BIT 7 BIT 6:0Frame length
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Frame Control Field
If set to 1 means: I have another packet to send to you after this packet
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Frame Check SequenceCC2420 can do auto CRC check
Always enable this functionFrame Check Sequence: 2 bytes
In transmit mode CRC is auto calculated and append to the transmit packet
In receive mode CRC is verified by hardware Frame check sequence contain
RSSI
BIT 7:0CRC OK(1)/CRC not OK (0) LQI
BIT 7 BIT 6:0
LQI - Link Quality Indication
RSSI - Receive Signal Strength Indicator
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Address Recognition And ACKHardware address recognition
Enable/disable by ADR_DECODE bit in MDMCTRL0 registerCC2420 will perform a sequence of address checking when it is
enable If address recognition fail, CC2420 will reject the frameCheck datasheet for further detail
Acknowledge framesHardware support auto acknowledgeEnable/disable by AUTOACK bit in MDMCTRL0 register If
Auto ack enabled Incoming frames pass address recognition and CRC checking Acknowledge requested in FCF
CC2420 will automatically send an acknowledge back to the sender
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RSSIReceive Signal Strength Indicator
Indicate how strong the RF signal isAveraged over 8 symbol periods (128 μs)
RSSI_VALID status bit indicates when the RSSI value is validReceiver has been enabled for at least 8 symbol periods
power P at the RF Pins
RSSI_OFFSET is found empirically during system development
RSSI_OFFSET is approximately –45
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CCAClear channel assessment
Check if the channel is clear Based on the measured RSSI value and a programmable threshold
Threshold level Programmed by registers: RSSI
3 CCA modes Programmed by registers: MDMCTRL0
CCA output pin indicates the channel is cleal or not High: channel is clear Low: channel is not clear
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Frequency and Channel ProgrammingOperating frequency is set by FSCTRL register
Last 10 bit Operating frequency Fc
IEEE 802.15.416 channels within the 2.4 GHz band, in 5 MHz stepsnumbered 11 through 26
There for
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Output Power ProgrammingControlled by the TXCTRL register
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Receive Mode SFD pin goes high after the start of frame delimiter (SFD) field has been
completely received. If address recognition is disabled or is successful,
the SFD pin goes low again only after the last byte of the MPDU hasbeen received.
Error state SFD goes high immediately Fig 12 FIFO is high as long as is one or more data bytes in the RXFIFO.
FIFO pin then remains high until the RXFIFO is empty
We use FIFOP to indicate the receive of valid packet Enable FIFOP interrupt
RXFIFO overflow FIFO pin goes low and FIFOP pin goes high indicate a RXFIFO overflow You must send a SFLUSHRX command to CC2420 if RXFIFO overflow
occurred
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Receive Mode
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Transmit ModeFIFO and FIFOP pins are still only related to the
RXFIFO. SFD pin goes high when the SFD field has been
completely transmittedTXFIFO underflow
Not enough bytes write to the TXFIFOIndicate in TX_UNDERFLOW bit in status byte
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Transmit Mode
Timer captureTimestamp value
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Strobe command
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Configuration registers write and read operations via SPI
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Packet TypeAcknowledge packet
Data Packet
5 bytes
Preamble SFD Frame Length
FCF Seq. number
PAN ID Destination address
Source address
Payload FCS
Bytes:
4~17
4~17
1 1 2 1 2 2 2 20~116
Minimum: 11 bytes
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cc2420
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Applications
2.4 GHz IEEE 802.15.4 systems
ZigBee systems
Home/building automation
Industrial Control
Wireless sensor networks
PC peripherals
Consumer Electronics
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Description
CC2420 is a true single-chip 2.4 GHz IEEE 802.15.4 compliant RF transceiver
designed for low-power and low-voltage wireless applications
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What are the benefits of cc2420?
Provides extensive hardware support for
Packet handling,
Data buffering,
Burst transmissions,
Data encryption, data authentication,
Clear channel assessment, link quality indicationand packet timing information
These reduce the load on the host controller and allow CC2420 to interface low-cost microcontrollers.
The configuration interface and transmit/receive FIFOs of CC2420 are accessed via an SPI interface
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Features(1):2400 – 2483.5 MHz RF Transceiver
Direct Sequence Spread Spectrum (DSSS) transceiver
250 kbps data rate, 2 MChip/s chip rate
O-QPSK with half sine pulse shaping modulation
Very low current consumption (RX: 19.7 mA, TX: 17.4 mA)
High sensitivity (-94 dBm)
High adjacent channel rejection(39 dB)
High alternate channel rejection(55 dB)
On-chip VCO, LNA and PA
Low supply voltage (2.1 – 3.6 V)with on-chip voltage regulator
Programmable output power
I/Q low-IF soft decision receiver
I/Q direct up-conversion transmitter
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Features (2)
Separate transmit and receive FIFOs
128 byte transmit data FIFO
128 byte receive data FIFO
Very few external components
Easy configuration interface
4-wire SPI interface
Up to 10 MHz serial clock
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Features (3)-802.15.4 MAC hardware support:
Automatic preamble generator
Synchronisation word insertion/detection
CRC-16 computation and checking over the MAC payload
Clear Channel Assessment
Energy detection / digital RSSI
Link Quality Indication
Full automatic MAC security(CTR, CBC-MAC, CCM)
Automated Hardware security
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Circuit Description
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Circuit Description(2)-receiver
The received signal is
amplified by Low noise amplifier and
Down-converted in to the immediate frequency
At IF(2 MHz), the complex I/Q signal is filtered and amplified,
And then digitized by the ADCs.
Automatic gain control, final channel filtering, despreading, symbol correlation and byte synchronization are performed digitally
When the SFD pin goes high
This indicates that a start of frame delimiter has beendetected
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Circuit Description(3)-receiver
CC2420 buffers the received data in a 128 byte receive FIFO.
The user may read the FIFO through an SPI interface.CRC is verified in hardware.
RSSI and correlation values are appended to the frame.
CCA is available on a pin in receive mode.
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Circuit Description(4)-transmitter
The CC2420 transmitter is based on direct up-conversion.
The data is buffered in a 128 byte transmit FIFO (separate from thereceive FIFO).
The preamble and start of frame delimiter are generated by hardware.
Each symbol (4 bits) is spread using the IEEE 802.15.4 spreadingsequence to 32 chips and
output to the digital-to-analog converters (DACs).
An analog lowpass filter passes the signalto the quadrature (I and Q) upconversion mixers.
The RF signal is amplified in the power amplifier (PA) and
fed to the antenna
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IEEE 802.15.4 Modulation Format
Each byte is divided into two symbols, 4 bits each
Least significant symbol is transmitted first
Each symbol is mapped to one out of 16 pseudo-random sequences, 32 chipseach
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IEEE 802.15.4 Modulation Format
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6. PHY specification
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Responsibility
Activation and deactivation of the radio transceiver
ED within the current channel
LQI for received packet
CCA for CSMA-CA
Channel frequency selection
Data transmission and reception
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6.1 General requirements and definitions
Compliant device shall operate in one or several frequency bands using the modulation and spreadingformats summarized