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OPB Multi Channel HDLC Interface (v2.01a)
DS438 December 1, 2005 0 0 Product Specification
IntroductionThis specification defines the architecture and interface requirements to this module, including registers that the user must initialize for proper operation. The Xilinx HDLC design allows the customer to tailor the HDLC to suit their application by setting certain parameters to enable/disable features. The parameterizable features of the design are discussed in HDLC Design Parameters.
Features Support for one to eight independent full duplex
HDLC channels.
Each independent channel may have 1 to 32 TDM sub-channels.
Receive FIFO buffer of selectable depth.
Transmit FIFO buffer of selectable depth.
Support for Packets larger than FIFO depth.
Selectable 8/16 bit address receive address detection.
Selectable receive frame address discard.
Selectable receive broadcast address detection. Broadcast address = 0xFF.
Selectable FCS 16 bit (CRC-CCITT) or 32 bit (CRC-32)
CRC error counter, with rollover interrupt
Aborted frame counter, with rollover interrupt
Multiple Events/Interrupts including:
- Rx FCS error interrupt
- Rx frame alignment error interrupt
- Memory buffer overrun/underrun interrupts
LogiCORE Facts
Core Specifics
Supported Device Family
QPro-R Virtex-II, QPro Virtex-II, Spartan-3, Spartan-3E, Virtex, Virtex-II,
Virtex-II Pro, Virtex-4
Resources Used (minimum settings)
I/O LUTs FFsBlock RAMs
6 1203 604 2
Version of Core opb_hdlc_v2_01_a
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template
N/A
Reference Designs & application notes
N/A
Additional Items N/A
Design Tool Requirements
Xilinx Implementation Tools
ISE 6.1i or later
with latest EDK
Verification ModelSim PE 5.7d
Simulation ModelSim PE 5.7d
Synthesis XST - ISE 6.1i
Support
Support provided by Xilinx, Inc.
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2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen-tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple-mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
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Features (contd) Tx frame abort control
Memory mapped direct I/O interface to registers and memory buffers.
Flag sharing between back to back frames
Independent Rx and Tx data rates for each physical channel. The OPB_CLK must be at least 1.1x higher frequency than the Rx or Tx data rate when a single sub channel is selected or 3x higher when more than one sub channel is selected.
Evaluation VersionThe HDLC LogiCORE is delivered with a hardware evaluation license. When programmed into a Xilinx device, the core will function in hardware for about 8 hours at the typical frequency of operation. To use the HDLC LogiCORE without this timeout limitation, a full license must be purchased.
HDLC Protocol
HDLC exists in layer 2 of the OSI model which is the data link layer. HDLC uses transparency to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore relies on the physical layer to provide a method of clocking and synchronizing the transmission and reception of frames. The control and data are not used by the hardware for any type of configuration or control.
An example of an HDLC frame that may contain no address or an 8-bit or 16-bit address is shown below.
Figure 1: HDLC Frame Example with no Address, 8-bit, or 16-bit Address
Figure Top x-ref 1
OpeningFlag
01111110
Address(if used)8 bits or 16 bits
ControlData
8*n-bits
FCSCRC - CCITTor CRC - 32
ClosingFlag
01111110
hdlc_frame_none_8or16_bit_addr.eps
Transparency
Transparency is the process of preventing the Flag pattern from occurring in the address, data or FCS fields. A zero bit is inserted, by the transmitter, any time a sequence of five consecutive ones has occurred. This will make the HDLC transparent to any type of data because any bit stream may exist between the opening and closing Flags. The receiver must remove the zero bit insertion to recover the original data sent.
An original bit pattern of:
11111110 01111111 01111101
Will become after bit stuffing:
111110110 011111011 011111001
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Flag Field
Each frame starts and stops with the flag sequence as shown above. The 0x7E flag is used for frame synchronization. Only one flag sequence is required to be between frames. The closing flag shown above could also be the opening flag for the next frame. A back to back flag sequence is an empty frame.
An empty frame is not counted as an FCS error. The flag bytes are not stored in the receive buffer. When the transmitter is enabled and there is no data to transmit, the transmitter will continuously send flags.
Address Field
The address field is typically 8 bits, however it can be 0 bits in a point to point or extended to 16 bits. The address identifies the secondary station that will receive the frame or transmit the frame. An address of all ones, 0xFF, is interpreted as an all stations address. This allows a broadcast frame to be received by all secondary stations.
Control Field
The 8 or 16 bit control field provides a flow control number and defines the frame type (control or data). The exact use and structure of this field depends upon the protocol using the frame. An integer number, including 0, of octets must be contained in this field to prevent an alignment error.
Information/Data Field
Data is transmitted in the information/data field, which can vary in length depending upon the protocol using the frame. An integer number, including 0, of octets must be contained in this field to prevent an alignment error.
Frame Check Sequence (FCS) Field
Error Control is implemented by appending a cyclic redundancy check (CRC) to the frame, which is 16 bits (CRC-CCITT) or 32 bits (CRC-32) long. The flag bits are not used in calculating the CRC. The FCS is stored in the receive buffer.
HDLC Design ParametersThe OPB Multi Channel HDLC design is user configurable via a set of design parameters implemented as VHDL input generics. The generics for the OPB Multi Channel HDLC are listed in Table 1.
Table 1: HDLC Design Parameters
GenericFeature /
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
HDLC Features
G1Number of Physical HDLC Channels
C_NUM_CHANNELS 1 - 8 1 Integer
G2Number of TDM sub-channels per Physical Channel 0
C_NUM_SUB_CHANNELS_0 0 - 32 1 Integer
G3Number of TDM sub-channels per Physical Channel 1
C_NUM_SUB_CHANNELS_1 0 - 32 0 Integer
G4Number of TDM sub-channels per Physical Channel 2
C_NUM_SUB_CHANNELS_2 0 - 32 0 Integer
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G5Number of TDM sub-channels per Physical Channel 3
C_NUM_SUB_CHANNELS_3 0 - 32 0 Integer
G6Number of TDM sub-channels per Physical Channel 4
C_NUM_SUB_CHANNELS_4 0 - 32 0 Integer
G7Number of TDM sub-channels per Physical Channel 5
C_NUM_SUB_CHANNELS_5 0 - 32 0 Integer
G8Number of TDM sub-channels per Physical Channel 6
C_NUM_SUB_CHANNELS_6 0 - 32 0 Integer
G9Number of TDM sub-channels per Physical Channel 7
C_NUM_SUB_CHANNELS_7 0 - 32 0 Integer
OPB/IPIF Interface
G20OPB Clock period in pico-seconds
C_OPB_CLK_PERIOD_PS
The period of the OPB bus
clock in pico-seconds
10000 Integer
G21 Device Block ID C_DEV_BLK_ID See note 5. 0 Integer
G22Module Identification Register Enable
C_DEV_MIR_ENABLE See note 5. 0 Integer
G23 OPB High Address C_HIGHADDR
Address range must
be a power of 2 and can
vary with the number of
HDLC channels(4)
None(2,3)std_logic_vector
G24Location of the first IPIF register.
C_BASEADDRValid Address
Range(4)None(2,3)
std_logic_vector
G25 OPB Address Bus Width C_OPB_AWIDTH 32 32 integer
G26 OPB Data Bus Width C_OPB_DWIDTH 32 32 integer
G27FPGA Device Family Type
C_FAMILY
spartan2
spartan2e
spartan3virtex
virtexe
virtex2
virtex2pqvirtex2
qrvirtex2
virtex2p string
Table 1: HDLC Design Parameters (Contd)
GenericFeature /
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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G28 DMA Present C_DMA_PRESENT(2)
1 = No DMA is used and
normal IPIF is used
2 = DMA with Scatter/Gather is used and normal IPIF
1 integer
Channel FIFO
G30Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_0(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
2048 Integer
G31Receive FIFO Memory Depth in bytes(7)
C_RX_MEM_DEPTH_0(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
2048 Integer
G32Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_1(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G33Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_1(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G34Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_2(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G35Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_2(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G36Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_3(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G37Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_3(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G38Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_4(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
Table 1: HDLC Design Parameters (Contd)
GenericFeature /
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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G39Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_4(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G40Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_5(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G41Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_5(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G42Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_6(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G43Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_6(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G44Transmit FIFO Depth in bytes(6)
C_TX_MEM_DEPTH_7(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
G45Receive Buffer Memory Depth in bytes(7)
C_RX_MEM_DEPTH_7(6, 7, 8, 9)
1 BRAM Minimum(8)
32 BRAMs Maximum(9)
0 Integer
HDLC I/O
G90Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_BITS_0
1 - log2(C_NUM_SUB_CHAN
NELS(0))
1 integer
G91Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL _BITS_1
1 - log2(C_NUM_SUB_CHAN
NELS(1))
0 integer
G92Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_ BITS_2
1 - log2(C_NUM_SUB_CHAN
NELS(2))
0 integer
G93Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_ BITS_3
1 - log2(C_NUM_SUB_CHAN
NELS(3))
0 integer
Table 1: HDLC Design Parameters (Contd)
GenericFeature /
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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Allowable Parameter Combinations
The address range specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and C_HIGHADDR must be at least 0x3FFFF. For example, if C_BASEADDR = 0x60100000 C_HIGHADDR must be at least = 0x6013FFFF.
G94Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_ BITS_4
1 - log2(C_NUM_SUB_CHAN
NELS(4))
0 integer
G95Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_ BITS_5
1 - log2(C_NUM_SUB_CHAN
NELS(5))
0 integer
G96Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_ BITS_6
1 - log2(C_NUM_SUB_CHAN
NELS(6))
0 integer
G97Number of bits required to encode the number of sub-channels
C_NUM_SUB_CHANNEL_ BITS_7
1 - log2(C_NUM_SUB_CHAN
NELS(7))
0 integer
Notes: 1. Each physical channel may have an independent serial transmit and serial receive clock inputs.2. Anytime DMA is present, interrupt coalescing is enabled3. For example, C_BASEADDR = 0x60100000, C_HIGHADDR = 0x6013FFFF 4. Address range specified by C_BASEADDR and C_HIGHADDR must be at least 0X3FFFF and must be a
power of 2. C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BASEADDR +1.
5. For a Virtex-II Pro a single BRAM is 2048 bytes and 32 Brams is 65536 bytes. 6. Both the receive and transmit FIFO is equally divided in powers of 2 among all the sub-channels.7. For example a transmit FIFO of 2048 bytes (1 BRAM) and 24 sub-channels would cause a transmit FIFO depth
of 60 bytes for each individual sub-channel, (2048/(32)) - 4. 2048 is the memory depth, 32 is the next power of two equal to or larger than 24, and 4 bytes are used by each sub channel in the FIFO to maintain status.
8. It is possible to specify a FIFO depth smaller than 1 BRAM, however 1 BRAM will be used and the unused memory is not available.
9. The maximum size for a sub channel FIFO is 16384 bytes. If two sub channels are specified on a single physical channel, the maximum FIFO size is 32768. If three sub channels are specified on a single physical channel the maximum FIFO depth is 49152.
Table 1: HDLC Design Parameters (Contd)
GenericFeature /
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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HDLC I/O SignalsThe I/O signals for the HDLC are listed in Table 2.
Table 2: HDLC I/O Signals
Port Signal Name Interface I/OInitial State
Description
HDLC Signals
P1 RXD(0 to C_NUM_CHANNELS - 1) System I HDLC Serial Data Input
P2 TXD(0 to C_NUM_CHANNELS - 1) System O 0 HDLC Serial Data Output
P3 RXden(0 to C_NUM_CHANNELS - 1) 1 System I HDLC RX data enable
P4 TXden(0 to C_NUM_CHANNELS - 1) 1 System I HDLC TX data enable
P5 RXCLK(0 to C_NUM_CHANNELS - 1) 1 System IHDLC Serial Receive Clock Input
P6 TXCLK(0 to C_NUM_CHANNELS - 1) 1 System IHDLC Serial Transmit Clock Input
P7
Rx_Chnl_Sel(0 to C_NUM_SUB_CHANNEL_BITS_0 + C_NUM_SUB_CHANNEL_BITS_1 + C_NUM_SUB_CHANNEL_BITS_2 + C_NUM_SUB_CHANNEL_BITS_3 + C_NUM_SUB_CHANNEL_BITS_4 + C_NUM_SUB_CHANNEL_BITS_5 + C_NUM_SUB_CHANNEL_BITS_6 + C_NUM_SUB_CHANNEL_BITS_7) 2, 3
System IHDLC receive sub-channel select input
P8
Tx_Chnl_Sel(0 to C_NUM_SUB_CHANNEL_BITS_0 + C_NUM_SUB_CHANNEL_BITS_1 + C_NUM_SUB_CHANNEL_BITS_2 + C_NUM_SUB_CHANNEL_BITS_3 + C_NUM_SUB_CHANNEL_BITS_4 + C_NUM_SUB_CHANNEL_BITS_5 + C_NUM_SUB_CHANNEL_BITS_6 + C_NUM_SUB_CHANNEL_BITS_7) 2, 3
System O 0HDLC transmit sub-channel select output
OPB Signals
P17 Sln_DBus(0:C_OPB_DWIDTH-1) IPIF O 0 HDLC output data bus
P18 Sln_xferAck IPIF O 0 HDLC transfer acknowledge
P19 Sln_Retry IPIF O 0 HDLC retry
P20 Sln_ToutSup IPIF O 0 HDLC timeout suppress
P21 Sln_ErrAck IPIF O 0 HDLC error acknowledge
P22 OPB_ABus(0:C_OPB_AWIDTH-1) IPIF I OPB address bus
P23 OPB_BE(0:C_OPB_DWIDTH/8-1) IPIF I OPB byte enables
P24 OPB_DBus(0:C_OPB_DWIDTH-1) IPIF I OPB data bus
P25 OPB_RNW IPIF IRead not Write (OR of all master RNW signals)
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HDLC Port DependenciesThe width of some of the HDLC signals depends on parameters selected in the design. The dependencies between the HDLC design parameters and I/O signals are shown in Table 3.
P26 OPB_select IPIF IMaster has taken control of the bus (OR of all master selects)
P27 OPB_seqAddr IPIF I OPB sequential address
P28 OPB_errAck IPIF I OPB error acknowledge
P29 OPB_MGrant IPIF I OPB master bus grant
P30 OPB_retry IPIF I OPB retry
P31 OPB_timeout IPIF I OPB timeout error
P32 OPB_xferAck IPIF I OPB transfer acknowledge
P33 Mn_request IPIF O 0 HDLC master bus request
P34 Mn_busLock IPIF O 0HDLC master bus arbitration lock
P35 Mn_select IPIF O 0 HDLC master select
P36 Mn_RNW IPIF O 0 HDLC master Read not Write
P37 Mn_BE(0:C_OPB_DWIDTH/8-1) IPIF O 0 HDLC master byte enables
P38 Mn_seqAddr IPIF O 0HDLC master sequential address
P39 Mn_ABus(0:C_OPB_ABUS_WIDTH-1) IPIF O 0 HDLC master address bus
System
P40 OPB_Clk System I System clock
P41 OPB_Rst System I System Reset (active high)
P42 IP2INTC_Irpt System O System Interrupt
P43 Freeze System I System Freeze Input
Notes: 1. The OPB_CLK must be at least 1.1x faster than the Rx or Tx data rate for a physical channel with one sub
channel, the OPB_CLK must be at least 3x faster than Rx or Tx data rates for a physical channel with more than one sub channel. The Rx data rate is controlled by the RXCLK and RXden, the Tx data rate is controlled by TXCLK and TXden.
2. If a no TDM sub-channels exist on any of the physical channels then this signal is undefined, but the vector will exist and be of length one (0 to 0). If any of the physical channels have more than one TDM sub-channel then this vector will be the concatenation of all the physical channels. For example if physical channel one has 24 sub-channels and physical channel two has 32 sub-channels and physical channel three has two sub-channels, then the vector is divided as follows, (0 to 4) physical channel one, (5 to 9) physical channel two, (10) physical channel three.
3. This vector will always be one larger than necessary. The top bit is to be ignored.
Table 2: HDLC I/O Signals (Contd)
Port Signal Name Interface I/OInitial State
Description
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Table 3: HDLC Parameter Port Dependencies
Generic or Port
Name Affects Depends Relationship Description
Design Parameters
G1 C_NUM_CHANNELSP1, P2, P3, P4, P5, P6
Specifies the number of physical channels
G2 C_NUM_SUB_CHANNELS_0 P7, P8Specifies the number of sub-channels for Physical Channel 0
G3 C_NUM_SUB_CHANNELS_1 P7, P8Specifies the number of sub-channels for Physical Channel 1
G4 C_NUM_SUB_CHANNELS_2 P7, P8Specifies the number of sub-channels for Physical Channel 2
G5 C_NUM_SUB_CHANNELS_3 P7, P8Specifies the number of sub-channels for Physical Channel 3
G6 C_NUM_SUB_CHANNELS_4 P7, P8Specifies the number of sub-channels for Physical Channel 4
G7 C_NUM_SUB_CHANNELS_5 P7, P8Specifies the number of sub-channels for Physical Channel 5
G8 C_NUM_SUB_CHANNELS_6 P7, P8Specifies the number of sub-channels for Physical Channel 6
G9 C_NUM_SUB_CHANNELS_7 P7, P8Specifies the number of sub-channels for Physical Channel 7
G28 C_OPB_DWIDTHP17, P23, P24
Specifies the OPB Data Bus width
G27 C_OPB_AWIDTHP22, P39
Specifies the OPB Address Bus width
I/O Signals
P1 RXD(0 to C_NUM_CHANNELS - 1) G1Width varies with the number of channels.
P2 TXD(0 to C_NUM_CHANNELS - 1) G1Width varies with the number of channels.
P3 RXden(0 to C_NUM_CHANNELS - 1) G1Width varies with the number of channels.
P4 TXden(0 to C_NUM_CHANNELS - 1) G1Width varies with the number of channels.
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HDLC Register DescriptionsThe HDLC contains addressable registers for read/write operations as shown in Table 4, Table 5, Table 6, Table 7 and Table 9 The base address for these registers is set in the parameter C_BASEADDR. C_BASEADDR + 0x1000 represents the address of the first register in the HDLC - in this case, the HDLC Status FIFO (SF). The address of each register is then calculated by an offset to the base address plus the physical channel offset plus the sub-channel offset.
The registers in Table 4 are contained in the IPIF module and are included for completeness of this specification. Please refer to the Processor IP Reference Guide under Part 1: Embedded Processor IP, under IPIF, under OPB IPIF Architecture, under OPB IPIF Register Descriptions for a complete description of these registers.
P5RXCLK(0 to log2(C_NUM_CHANNELS) - 1)
G1Width varies with the number of channels.
P6TXCLK(0 to log2(C_NUM_CHANNELS) - 1)
G1Width varies with the number of channels.
P7
Rx_Chnl_Sel(0 to C_NUM_SUB_CHANNEL_BITS_0 + C_NUM_SUB_CHANNEL_BITS_1 + C_NUM_SUB_CHANNEL_BITS_2 + C_NUM_SUB_CHANNEL_BITS_3 + C_NUM_SUB_CHANNEL_BITS_4 + C_NUM_SUB_CHANNEL_BITS_5 + C_NUM_SUB_CHANNEL_BITS_6 + C_NUM_SUB_CHANNEL_BITS_7)
G1, G2Width varies with the number of channels. Width varies with the number of sub-channels.
P8
Tx_Chnl_Sel(0 to C_NUM_SUB_CHANNEL_BITS_0 + C_NUM_SUB_CHANNEL_BITS_1 + C_NUM_SUB_CHANNEL_BITS_2 + C_NUM_SUB_CHANNEL_BITS_3 + C_NUM_SUB_CHANNEL_BITS_4 + C_NUM_SUB_CHANNEL_BITS_5 + C_NUM_SUB_CHANNEL_BITS_6 + C_NUM_SUB_CHANNEL_BITS_7)
G1, G2Width varies with the number of channels. Width varies with the number of sub-channels.
P17 Sln_DBus(0:C_OPB_DWIDTH-1) G28 Width varies with the size of the OPB Data bus.
P22 OPB_ABus(0:C_OPB_AWIDTH-1) G27Width varies with the size of the OPB Address bus.
P23 OPB_BE(0:C_OPB_DWIDTH/8-1) G28Width varies with the size of the OPB Data bus.
P24 OPB_DBus(0:C_OPB_DWIDTH-1) G28Width varies with the size of the OPB Data bus.
P39M_ABus(0:C_OPB_ABUS_WIDTH-1)
G27Width varies with the size of the OPB Data bus.
Table 3: HDLC Parameter Port Dependencies (Contd)
Generic or Port
Name Affects Depends Relationship Description
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IPIF Registers used by the HDLC
Table 4: HDLC IPIF Registers
Register Name OPB ADDRESS Access
Device Interrupt Status Register C_BASEADDR + 0x0000 Read/Write
Device Interrupt Pending Register C_BASEADDR + 0x0004 Read/Write
Device Interrupt Enable Register C_BASEADDR + 0x0008 Read/Write
Device Interrupt Identification Register C_BASEADDR + 0x0018 Read/Write
Device Global Interrupt Enable C_BASEADDR + 0x001C Read/Write
IP Interrupt Status Register C_BASEADDR + 0x0020 Read/Write
IP Interrupt Enable Register C_BASEADDR + 0x0028 Read/Write
Device Software Reset (write) Module Identification (read) Register
C_BASEADDR + 0x0040 Read/Write
DMA Module Identification Register(1) C_BASEADDR + 0x1010 Read
DMA Global CSR(1) C_BASEADDR + 0x1014 Read/Write
DMA Event FIFO(1) C_BASEADDR + 0x1018 Read
DMA Reserved for system(1,2) C_BASEADDR + dmasg_chan*0X20 + 0x10000 none
DMA Control Register(1,2) C_BASEADDR + dmasg_chan*0X20 + 0x10004 Read/Write
DMA Source Address(1,2) C_BASEADDR + dmasg_chan*0X20 + 0x10008 Read/Write
DMA Destination Address(1,2)C_BASEADDR + dmasg_chan*0X20 +
0x1000CRead/Write
DMA Length(1,2) C_BASEADDR + dmasg_chan*0X20 + 0x10010 Read/Write
DMA Status Register(1,2) C_BASEADDR + dmasg_chan*0X20 + 0x10014 Read
DMA Buffer Descriptor Address(1,2) C_BASEADDR + dmasg_chan*0X20 + 0x10018 Read/Write
DMA Software Control Register(1,2)C_BASEADDR + dmasg_chan*0X20 +
0x1001CRead/Write
Notes: 1. These registers are available only if C_DMA_PRESENT = 2.2. These 8 registers are repeated for every DMA channel. A DMA channel is a half duplex channel, so a single
channel HDLC which is full duplex contains 2 DMA channels one for Tx and one for Rx.
HDLC Registers
Table 5, Table 6, and Table 7 shows the HDLC registers and addresses, the physical channel offset, and the sub-channel offset. Table 8 and Table 9 show the address offsets for the channel FIFOs.
Table 5: HDLC Registers
Register Name OPB Address Access
Status FIFO (SF) C_BASEADDR + 0x1000 Read
Device Control Register (MSCR) C_BASEADDR + 0x1100 Read/Write
TX Event FIFO (TXEF) C_BASEADDR + 0x1104 Read
RX Event FIFO (RXEF) C_BASEADDR + 0x1108 Read
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Physical Channel 0 Control Register (PCCR(0)) C_BASEADDR + 0x1110 Read/Write
Number of Aborted Frames per physical channel 0 (ABRT(0)) C_BASEADDR + 0x1114 Read/Write
Number of CRC Errors per physical channel 0 (CRCE(0)) C_BASEADDR + 0x1118 Read/Write
Physical Channel 1 Control Register (PCCR(1))1 C_BASEADDR + 0x1120 Read/Write
Number of Aborted Frames per physical channel 1 (ABRT(1))1
C_BASEADDR + 0x1124 Read/Write
Number of CRC Errors per physical channel 1 (CRCE(1))1 C_BASEADDR + 0x1128 Read/Write
Physical Channel 2 Control Register (PCCR(2))1 C_BASEADDR + 0x1130 Read/Write
Number of Aborted Frames per physical channel 2 (ABRT(2))1
C_BASEADDR + 0x1134 Read/Write
Number of CRC Errors per physical channel 2 (CRCE(2))1 C_BASEADDR + 0x1138 Read/Write
Physical Channel 3 Control Register (PCCR(3))1 C_BASEADDR + 0x1140 Read/Write
Number of Aborted Frames per physical channel 3 (ABRT(3))1
C_BASEADDR + 0x1144 Read/Write
Number of CRC Errors per physical channel 3 (CRCE(3))1 C_BASEADDR + 0x1148 Read/Write
Physical Channel 4 Control Register (PCCR(4))1 C_BASEADDR + 0x1150 Read/Write
Number of Aborted Frames per physical channel 4 (ABRT(4))1
C_BASEADDR + 0x1154 Read/Write
Number of CRC Errors per physical channel 4 (CRCE(4))1 C_BASEADDR + 0x1158 Read/Write
Physical Channel 5 Control Register (PCCR(5))1 C_BASEADDR + 0x1160 Read/Write
Number of Aborted Frames per physical channel 5 (ABRT(5))1
C_BASEADDR + 0x1164 Read/Write
Number of CRC Errors per physical channel 5 (CRCE(5))1 C_BASEADDR + 0x1168 Read/Write
Physical Channel 6 Control Register (PCCR(6))1 C_BASEADDR + 0x1170 Read/Write
Number of Aborted Frames per physical channel 6 (ABRT(6))1
C_BASEADDR + 0x1174 Read/Write
Number of CRC Errors per physical channel 6 (CRCE(6))1 C_BASEADDR + 0x1178 Read/Write
Physical Channel 7 Control Register (PCCR(7))1 C_BASEADDR + 0x1180 Read/Write
Number of Aborted Frames per physical channel 7 (ABRT(7))1
C_BASEADDR + 0x1184 Read/Write
Number of CRC Errors per physical channel 7 (CRCE(7))1 C_BASEADDR + 0x1188 Read/Write
TX Sub channel Control (TXCR)(2)C_BASEADDR + Physical Offset(3) + Sub-Channel
Offset(4)Read/Write
RX Sub channel Control, Address (RXCA)(2)C_BASEADDR + Physical Offset(3) + Sub-Channel
Offset(4) + 0x800Read/Write
Table 5: HDLC Registers (Contd)
Register Name OPB Address Access
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TX DATA FIFO STATUS (TXDFS)C_BASEADDR + FIFO
Offset(5) + FIFO Sub-channel Offset(6)
Read
TX DATA FIFO (TXDF)C_BASEADDR + FIFO
Offset(5) + FIFO Sub-channel Offset(6)
Write
RX DATA FIFO STATUS (RXDFS)C_BASEADDR + FIFO
Offset(5) + FIFO Sub-channel Offset(6) + 0x2000
Read
RX DATA FIFO (RXDF)C_BASEADDR + FIFO
Offset(5) + FIFO Sub-channel Offset(6) + 0x2004
Read
Notes: 1. The availability of these registers depends on C_NUM_CHANNELS.2. If more than one sub channel is specified these registers are stored in BRAM. After a reset the entire Tx and
Rx BRAM must be initialized to zeros. This includes all the address space between each control register.3. The Physical Offset values are listed in Table 6.4. The Sub-channel Offset values are listed in Table 7.5. The FIFO Offset values are listed in Table 8.6. The FIFO Sub-channel Offset values are listed in Table 9.
Table 6: HDLC Physical Channel Control Registers Offset Values
Register Name Offset Value
Physical Channel 0, Sub-Channel 0 0x18000
Physical Channel 1, Sub-Channel 0 0x19000
Physical Channel 2, Sub-Channel 0 0x1A000
Physical Channel 3, Sub-Channel 0 0x1B000
Physical Channel 4, Sub-Channel 0 0x1C000
Physical Channel 5, Sub-Channel 0 0x1D000
Physical Channel 6, Sub-Channel 0 0x1E000
Physical Channel 7, Sub-Channel 0 0x1F000
Table 7: HDLC Sub-channel Control Registers Offset Values
Register Name Offset Value
Sub-Channel 0 0x0000
Sub-Channel 1 0x0020
Sub-Channel 2 0x0040
Sub-Channel 3 0x0060
Sub-Channel 4 0x0080
Table 5: HDLC Registers (Contd)
Register Name OPB Address Access
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Sub-Channel 5 0x00A0
Sub-Channel 6 0x00C0
Sub-Channel 7 0x00E0
Sub-Channel 8 0x0100
Sub-Channel 9 0x0120
Sub-Channel 10 0x0140
Sub-Channel 11 0x0160
Sub-Channel 12 0x0180
Sub-Channel 13 0x01A0
Sub-Channel 14 0x01C0
Sub-Channel 15 0x01E0
Sub-Channel 16 0x0200
Sub-Channel 17 0x0220
Sub-Channel 18 0x0240
Sub-Channel 19 0x0260
Sub-Channel 20 0x0280
Sub-Channel 21 0x02A0
Sub-Channel 22 0x02C0
Sub-Channel 23 0x02E0
Sub-Channel 24 0x0300
Sub-Channel 25 0x0320
Sub-Channel 26 0x0340
Sub-Channel 27 0x0360
Sub-Channel 28 0x0380
Sub-Channel 29 0x03A0
Sub-Channel 30 0x03C0
Sub-Channel 31 0x03E0
Table 8: HDLC FIFO Offset Values
Register Name Offset Value
Physical Channel 0, Sub-Channel 0 0x20000
Physical Channel 1, Sub-Channel 0 0x24000
Physical Channel 2, Sub-Channel 0 0x28000
Table 7: HDLC Sub-channel Control Registers Offset Values (Contd)
Register Name Offset Value
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Physical Channel 3, Sub-Channel 0 0x2C000
Physical Channel 4, Sub-Channel 0 0x30000
Physical Channel 5, Sub-Channel 0 0x34000
Physical Channel 6, Sub-Channel 0 0x38000
Physical Channel 7, Sub-Channel 0 0x3C000
Table 9: HDLC FIFO Sub Channel Offset Values
Register Name Offset Value
FIFO Sub-Channel 0 0x0000
FIFO Sub-Channel 1 0x0080
FIFO Sub-Channel 2 0x0100
FIFO Sub-Channel 3 0x0180
FIFO Sub-Channel 4 0x0200
FIFO Sub-Channel 5 0x0280
FIFO Sub-Channel 6 0x0300
FIFO Sub-Channel 7 0x0380
FIFO Sub-Channel 8 0x0400
FIFO Sub-Channel 9 0x0480
FIFO Sub-Channel 10 0x0500
FIFO Sub-Channel 11 0x0580
FIFO Sub-Channel 12 0x0600
FIFO Sub-Channel 13 0x0680
FIFO Sub-Channel 14 0x0700
FIFO Sub-Channel 15 0x0780
FIFO Sub-Channel 16 0x0800
FIFO Sub-Channel 17 0x0880
FIFO Sub-Channel 18 0x0900
FIFO Sub-Channel 19 0x0980
FIFO Sub-Channel 20 0x0A00
FIFO Sub-Channel 21 0x0A80
FIFO Sub-Channel 22 0x0B00
FIFO Sub-Channel 23 0x0B80
FIFO Sub-Channel 24 0x0C00
Table 8: HDLC FIFO Offset Values
Register Name Offset Value
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Address Bus Usage for Channel FIFOs
Figure 2: Address Bus Usage for Channel FIFOs
Figure Top x-ref 2
addr_bus_usage_channel_fifos.eps
0 13 14 17 18 27 2825 26 29 30 31
Device Address FIFO Sub-channel Tag(1)
FIFO Phy Channel Tag(0) Tag(2) Zero
Tag(3)
Tag Bits(0 to 3), Address bits(26 to 29)
Tag bits make use of the extra data bits that exist in a BRAM. By placing the tag bits in the address space, sixteen extra address ranges are used for each FIFO. This allows the processor to write 36 bits of data to each FIFO, 32 bits of data are written on the data bus as normal, then depending upon which address is written to the tag bits are set as shown in Table 10
FIFO Sub-Channel 25 0x0C80
FIFO Sub-Channel 26 0x0D00
FIFO Sub-Channel 27 0x0D80
FIFO Sub-Channel 28 0x0E00
FIFO Sub-Channel 29 0x0E80
FIFO Sub-Channel 30 0x0F00
FIFO Sub-Channel 31 0x0F80
Table 10: Address Usage for Channel FIFO
Address Tag Value Tag Bit Meaning
0b 0000 0000 0000 001x xxxx xxxx xx00 0000+ C_BASEADDR
Tag(0 to 3) = 0x0Normal Data4 bytes to TX, not EOP
0b 0000 0000 0000 001x xxxx xxxx xx00 0100+ C_BASEADDR
Tag(0 to 3) = 0x1 Undefined
0b 0000 0000 0000 001x xxxx xxxx xx00 1000+ C_BASEADDR
Tag(0 to 3) = 0x2 Undefined
0b 0000 0000 0000 001x xxxx xxxx xx00 1100+ C_BASEADDR
Tag(0 to 3) = 0x3 Undefined
0b 0000 0000 0000 001x xxxx xxxx xx01 0000+ C_BASEADDR
Tag(0 to 3) = 0x4End of packet (EOP)4 bytes valid
0b 0000 0000 0000 001x xxxx xxxx xx01 0100+ C_BASEADDR
Tag(0 to 3) = 0x5End of packet (EOP) 1 byte valid
0b 0000 0000 0000 001x xxxx xxxx xx01 1000+ C_BASEADDR
Tag(0 to 3) = 0x6End of packet (EOP) 2 bytes valid
0b 0000 0000 0000 001x xxxx xxxx xx01 1100+ C_BASEADDR
Tag(0 to 3) = 0x7End of packet (EOP) 3 bytes valid
Table 9: HDLC FIFO Sub Channel Offset Values (Contd)
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FIFO Sub-channel(0 to 7) Address Bits(18 to 25)
FIFO sub-channel(0 to 7) 0 is the MSB (address bit 18) and 7 is the LSB (address bit 25). The MSB is used to select between either a Tx channel (MSB = 0) or a Rx channel (MSB = 1). The remainder of the bits in this range are used to select a sub-channel.
FIFO Phy channel(0 to 3) Address Bits(14 to 17)
Each physical HDLC interface contains an independent Tx Channel FIFO and independent Rx Channel FIFO.
Example Memory Map
This example is based upon a system that contains eight physical channels 32 sub-channels and a receive and transmit memory depth of 2048 for each physical channel. Only two physical and two sub-channels are shown in Table 11.
0b 0000 0000 0000 001x xxxx xxxx xx10 0000+ C_BASEADDR
Tag(0 to 3) = 0x8 Undefined
0b 0000 0000 0000 001x xxxx xxxx xx10 0100+ C_BASEADDR
Tag(0 to 3) = 0x9 Undefined
0b 0000 0000 0000 001x xxxx xxxx xx10 1000+ C_BASEADDR
Tag(0 to 3) = 0xA Undefined
0b 0000 0000 0000 001x xxxx xxxx xx10 1100+ C_BASEADDR
Tag(0 to 3) = 0xB Undefined
0b 0000 0000 0000 001x xxxx xxxx xx11 0000+ C_BASEADDR
Tag(0 to 3) = 0xC Undefined
0b 0000 0000 0000 001x xxxx xxxx xx11 0100+ C_BASEADDR
Tag(0 to 3) = 0xD Undefined
0b 0000 0000 0000 001x xxxx xxxx xx11 1000+ C_BASEADDR
Tag(0 to 3) = 0xE Undefined
0b 0000 0000 0000 001x xxxx xxxx xx11 1100+ C_BASEADDR
Tag(0 to 3) = 0xF Undefined
Table 11: Example Memory Map Consisting of 8 Physical Channels, 32 sub-channels 2048 bytes Rx and Tx Memory depth for all physical channels
Category Relative Absolute Description
HDLC Device
+ 0x0000 + 0x0000 IPIF Registers
+ 0x1000 + 0x1000 Status FIFO
+ 0x1100 + 0x1100 Device Control Register
+ 0x1104 + 0x1104 Tx Event FIFO
+ 0x1108 + 0x1108 Rx Event FIFO
Table 10: Address Usage for Channel FIFO (Contd)
Address Tag Value Tag Bit Meaning
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Physical Channel 0
+ 0x1110 + 0x1110 Physical Channel 0 Control Register
+ 0x1114 + 0x1114 Aborted Frame Counter
+ 0x1118 + 0x1118 CRC Error Counter
Physical Channel 1
+ 0x1120 + 0x1120 Physical Channel 1 Control Register
+ 0x1124 + 0x1124 Aborted Frame Counter
+ 0x1128 + 0x1128 CRC Error Counter
Physical Channel 0
Sub-channel 0+ 0x18000 (Physical Offset)+ 0x00000 (Sub Channel Offset)
+ 0x18000 Tx Control (TXCR(0,0))
Physical Channel 0 Sub-channel 1
+ 0x18000 (Physical Offset)+ 0x00020 (Sub Channel Offset)
+ 0x18020 Tx Control (TXCR(0,1))
Physical Channel 0Sub-channel 0
+ 0x18000 (Physical Offset)+ 0x00000 (Sub Channel Offset) + 0x00800 (Constant Offset)
+ 0x18800 Rx Control (RXCA(0,0))
Physical Channel 0 Sub-channel 1
+ 0x18000 (Physical Offset)+ 0x00020 (Sub Channel Offset)+ 0x00800 (Constant Offset)
+ 0x18820 Rx Control RXCA(0,1))
Physical Channel 0
Sub-channel 0
+ 0x20000 (FIFO Offset)+ 0x00000 (FIFO Sub Offset)+ 0x00000 (Tag Offset)
+ 0x20000
Write - TXDF(0,0) normal Tx data as defined in Table 10Read - TXDFS(0,0) Tx Data FIFO Status
Physical Channel 0
Sub-channel 0
+ 0x20000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x00004 - 0x0003C (Tag Offset)
+ 0x20004 through
+ 0x2003C
Write - TXDF(0,0) as defined in Table 10Read - undefined
Physical Channel 0Sub-channel 0
+ 0x20000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x02000 (Constant Offset)
+ 0x22000Write - UndefinedRead - RXDFS(0,0) Rx Data FIFO Status
Physical Channel 0Sub-channel 0
+ 0x20000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x02004 (Constant Offset)
+ 0x22004Write - UndefinedRead - RXDF(0,0) Rx Data FIFO
Physical Channel 0 Sub-channel 1
+ 0x20000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x00000 (Tag Offset)
+ 0x20080
Write - TXDF(0,1) normal Tx data as defined in Table 10Read - TXDFS(0,1) Tx Data FIFO Status
Physical Channel 0 Sub-channel 1
+ 0x20000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x00004 - 0x0003C (Tag Offset)
+ 0x20084 through
+ 0x200BC
Write - TXDF(0,1) as defined in Table 10Read - undefined
Physical Channel 0 Sub-channel 1
+ 0x20000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x02000 (Constant Offset)
+ 0x22080Write - UndefinedRead - RXDFS(0,1) Rx Data FIFO Status
Table 11: Example Memory Map Consisting of 8 Physical Channels, 32 sub-channels 2048 bytes Rx and Tx Memory depth for all physical channels (Contd)
Category Relative Absolute Description
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Physical Channel 0Sub-channel 1
+ 0x20000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x02004 (Constant Offset)
+ 0x22084Write - UndefinedRead - RXDF(0,1) Rx Data FIFO
Physical Channel 1
Sub-channel 0+ 0x19000 (Physical Offset)+ 0x00000 (Sub Channel Offset)
+ 0x19000 Tx Control (TXCR(1,0))
Physical Channel 1 Sub-channel 1
+ 0x19000 (Physical Offset)+ 0x00020 (Sub Channel Offset)
+ 0x19020 Tx Control TXCR(1,1))
Physical Channel 1Sub-channel 0
+ 0x19000 (Physical Offset)+ 0x00000 (Sub Channel Offset)+ 0x00800 (Constant Offset)
+ 0x19800 Rx Control (RXCA(1,0))
Physical Channel 1 Sub-channel 1
+ 0x19000 (Physical Offset)+ 0x00020 (Sub Channel Offset)+ 0x00800 (Constant Offset)
+ 0x19820 Rx Control (RXCA(1,1))
Physical Channel 1
Sub-channel 0
+ 0x24000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x00000 (Tag Offset)
+ 0x24000
Write - TXDF(1,0) normal Tx data as defined in Table 10Read - TXDFS(1,0)Tx Data FIFO Status
Physical Channel 1Sub-channel 0
+ 0x24000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x00004 - 0x0003C (Tag Offset)
+ 0x24004
through
+ 0x2403C
Write - TXDF(1,0) as defined in Table 10Read - undefined
Physical Channel 1
Sub-channel 0
+ 0x24000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x02000 (Constant Offset)
+ 0x26000Write - UndefinedRead - RXDFS(1,0) Rx Data FIFO Status
Physical Channel 1
Sub-channel 0
+ 0x24000 (Physical Offset)+ 0x00000 (FIFO Sub Offset)+ 0x02004 (Constant Offset)
+ 0x26004Write - UndefinedRead - RXDF(1,0) Rx Data FIFO
Physical Channel 1 Sub-channel 1
+ 0x24000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x00000 (Tag Offset)
+ 0x24080
Write - TXDF(1,1) normal Tx data as defined in Table 10Read - TXDFS(1,1) Tx Data FIFO Status
Physical Channel 1 Sub-channel 1
+ 0x24000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x00004 - 0x0003C (Tag Offset)
+ 0x24084
through
+ 0x240B4
Write - TXDF(1,1) as defined in Table 10Read - undefined
Physical Channel 1 Sub-channel 1
+ 0x24000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x02000 (Constant Offset)
+ 0x26080Write - UndefinedRead - RXDFS(1,1) Rx Data FIFO Status
Physical Channel 1Sub-channel 1
+ 0x24000 (Physical Offset)+ 0x00080 (FIFO Sub Offset)+ 0x02004 (Constant Offset)
+ 0x26084Write - UndefinedRead - RXDF(1,1) Rx Data FIFO
Table 11: Example Memory Map Consisting of 8 Physical Channels, 32 sub-channels 2048 bytes Rx and Tx Memory depth for all physical channels (Contd)
Category Relative Absolute Description
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HDLC Device Control Register (MSCR), C_BASE_ADDR + 0x1100
There is one HDLC Device Control Register for the entire HDLC device, regardless of the number of physical channels or sub-channels specified. The bit definitions are shown in Table 12.
Figure 3: HDLC Device Control Register Bit Mapping
Figure Top x-ref 3
addr_bus_usage_channel_fifos.eps
0 3 4 3029 31
MSB LSB Unused
Number of Physical
Channels - 1
MSEN
TXSEN
Table 12: HDLC Device Control Register Bit Definitions
Bit(s) Name Access Reset Value Description
0 - 3 NPC ReadC_NUM_
CHANNELS - 1
Number of Physical Channels - 1.This is the generic C_NUM_CHANNELS - 1 that is a read only. Writing to these bits is ignored and has no effect.
4-29 Unused Undefined Reserved
30 TXSEN Read/Write 0
Transmit Status Write Enable.Setting this bit to a 0 prevents all transmit status from being written into the Status FIFO. All receive status will still be written to the Status FIFO.Setting this bit to a 1 is required to use DMA and allows transmit status and transmit data length to be written into the Status FIFO.
31 MSEN Read/Write 0
Master Enable.Setting this bit to a 0 prevents the HDLC from receiving or transmitting any data. All registers should be initialized prior to setting this bit to a 1
Status FIFO (SF) C_BASE_ADDR + 0x1000
There is one Status FIFO for the entire HDLC device, regardless of the number of physical channels or sub-channels specified. This FIFO is 16 locations deep and is read only. The The Status FIFO bit mapping is shown in Figure 4, while the bit definitions are listed in Table 13.
Figure 4: Status FIFO Bit Mapping
Figure Top x-ref 4
0 3 4 98 10 23 24 25 31
Length
EOPTx - 0Rx - 1
Sub-Channel Status
status_fifo_bit_mapping.epsPhysical Channel
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Table 13: HDLC Status FIFO Bit Definitions
Bit(s) Name Access Reset Value Description
0-3Physical Channel
Read UndefinedPhysical Channel Number.This field contains the binary encoding of the Physical Channel number. Data Bit 0 is the MSB
4 - 8Sub-
channelRead Undefined
Sub-Channel Number.This field contains the binary encoding of the Sub-Channel number. Data Bit 4 is the MSB.
9 RxTx Read UndefinedRxTx.Tx = 0Rx = 1
10 - 23 Length Read UndefinedThis is the number of bytes of data that has been written to the Rx Channel FIFO, or the number of bytes of data that has been read from Tx Channel FIFO.
24 EOP Read UndefinedEnd of Packet. This bit will be set high to indicate that the final byte has been received. This bit is undefined for transmit status.
25 - 27 Status(1) Read Undefined Reserved Status Bits
28 RXFA(1) Read UndefinedRX Frame Aborted. This bit will be set to a 1 when the last frame was aborted. This bit is cleared upon receiving the end flag of a complete frame.
29 RXFCS(1) Read UndefinedRX FCS Error. The last received frame contained an error. This bit will be set to a 1 once the end flag has been received if the frame contained an error.
30 RXAE(1) Read UndefinedRX Alignment Error. This bit is set to a 1 whenever the receiver did not receive an integer number of bytes.
31 RXBA(1) Read UndefinedBroadcast Address Received. This bit is set high when a transmitter has issued a broadcast address and the broadcast address match bit is set high, RXCA(30) = 1.
Notes: 1. The HDLC only returns a receive status, these bits are undefined and unused for a transmit status
HDLC Events
The HDLC events are converted into interrupts by the IPIF interrupt register set. The HDLC has multiple Transmit (Tx) and Receive (Rx) events. These Tx and Rx events are stored in separate event FIFOs. The event FIFOs are 16 locations deep and are read only. The following six events are managed by the IP Interrupt Source Controller Function which is contained in the IPIF module. This interface provides many of the features commonly provided for interrupt handling. The IPIER and IPISR contain the bit mapping as shown in Figure 5. Please refer to the Processor IP Reference Guide under Part 1: Embedded Processor IP, under IPIF, under OPB IPIF Architecture, under OPB IPIF Interrupt for a complete description of the IPIF interrupt processing including the GIE, IPISR and IPIER. The number in the parenthesis is the IPIF interrupt bit number. The bit definitions are described below.
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Figure 5: HDLC Event Mapping
Figure Top x-ref 5
26250 27 28 29 30 31
Event(4)
Event(2)
Event(0)
Event(5)
Event(3)
Event(1)
Unused
hdlc_event_mapping.eps
Event(0) -- Tx Event FIFO not empty
This event indicates that one or more of the events listed in Table 14 has occurred. The Tx event FIFO must be read to determine the physical channel and sub-channel number and the event condition. This event will remain active until the Tx event FIFO is empty.
Event(1) -- Tx Event FIFO Full
This event indicates that one or more of the events listed in Table 14 occurred, but that the Tx event FIFO was full and unable to store the latest event. This indicates that information has been lost and the recommended approach to recover from this condition is that the HDLC device transmit channels, both the physical and sub-channels, should be reset to initial conditions.
Event(2) -- Rx Event FIFO not empty
This event indicates that one or more of the events listed in Table 15 has occurred. The Rx event FIFO must be read to determine the physical channel and sub-channel number and the event condition. This event will remain active until the Rx event FIFO is empty.
Event(3) -- Rx Event FIFO Full
This event indicates that one or more of the events listed in Table 15 occurred, but that the Rx event FIFO was full and unable to store the latest event. This indicates that information has been lost and the recommended approach to recover from this condition is that the HDLC device receive channels, both the physical and sub-channels, should be reset to initial conditions.
Event(4) -- HDLC Status FIFO not empty
This event indicates that data exists in the HDLC Status FIFO.
Event (5) -- HDLC Status FIFO Full
Indicates that the HDLC Status FIFO became full during the reception or transmission of a packet and data was lost. This indicates that information has been lost and the recommended approach to recover from this condition is that the HDLC, both physical and sub-channels, should be reset to initial conditions.
HDLC Tx Event FIFO (TXEF) C_BASE_ADDR + 0x1104
There is one HDLC Tx Event FIFO for the device. This FIFO is 16 location deep and is read only. The HDLC Tx Event FIFO bit mapping is shown inFigure 6, while the bit definitions are shown in Table 14.
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Figure 6: HDLC Tx Event FIFO Bit Mapping
Figure Top x-ref 6
2928 30 31
Tx_Event(1)
Tx_Event(2)Tx_Event(0)
UnusedReserved
PhysicalChannel Sub-Channel
hdlc_tx_event_fifo_bit_mapping.eps
30 4 76 11 12
Table 14: HDLC Tx Event FIFO
Bit(s) Name AccessReset Value
Description
0 - 3Physical Channel
Read 0Physical Channel NumberBit 0 is the MSB of the Physical Channel Number.
4 - 6 Reserved Read 0Reserved.Reserved for future sub channel growth.
7 - 11 Sub-Channel Read 0Sub Channel NumberBit 7 is the MSB of the Sub-Channel Number.
12 - 28
Unused Undefined Reserved
29 Tx_Event (2) Read 0
Tx_Event (2) -- Tx Channel FIFO Half EmptyIndicates that the Tx channel FIFO is half empty. This event is only caused by the Tx channel FIFO transitioning from less than half empty to more than half empty.
30 Tx_Even t(1) Read 0Tx_Event (1) -- Tx dual port underrunIndicates that a Tx dual port underrun occurred. This event occurs if the Tx data rate is to high relative to the OPB_CLK.
31 Tx_Event (0) Read 0
Tx_Event (0) -- Transmit CompleteEvent(0) is the transmit complete. This event will occur as the last byte of data is being transmitted, prior to the transmission of the CRC or the ending flag. This event is a pulse and there is no action required by software to clear this event condition.
HDLC Rx Event FIFO (RXEF) C_BASE_ADDR + 0x1108
There is one HDLC Rx Event FIFO for the device. This FIFO is 16 location deep and is read only. The HDLC Rx Event FIFO bit mapping is shown in Figure 7, while the bit definitions are shown in Table 15.
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Figure 7: HDLC Rx Event FIFO Bit Mapping
Figure Top x-ref 7
2928 30 31
Rx_Event(1)
Rx_Event(2)Rx_Event(0)
UnusedReserved
PhysicalChannel Sub-Channel
hdlc_rx_event_fifo_bit_mapping.eps
30 4 76 11 12
Table 15: HDLC Rx Event FIFO
Bit(s) Name AccessReset Value
Description
0 - 3Physical Channel
Read 0Physical Channel NumberBit 0 is the MSB of the Physical Channel Number.
4 - 6 Reserved Read 0Reserved.Reserved for future sub channel growth.
7 - 11Sub-
ChannelRead 0
Sub Channel NumberBit 7 is the MSB of the Sub-Channel Number.
12 - 28 Unused Undefined Reserved
29 Rx_Event (2) Read 0Rx_Event (2) -- Rx dual port overrunIndicates that an Rx dual port overrun occurred. This event occurs if the Rx data rate is to high relative to the OPB_CLK.
30 Rx_Event (1) Read 0
Rx_Event (1) -- CRC counter or Aborted frames counter rollover eventIndicates that either the CRC counter incremented from 65535 to 0 or the aborted frames counter incremented from 65535 to 0.
31 Rx_Event (0) Read 0
Rx_Event (0) -- Receive Data FIFO Overrun eventIndicates that the receive data FIFO became full during the reception of a packet and data was lost. Receive packets stored in the FIFO should be processed to free up more locations. This event occurs every time an attempt to write data to the FIFO and the FIFO is full.
HDLC Physical Control Register (PCCR) C_BASE_ADDR + 0x1110, 0x1120, 0x1130, ...
There will be one HDLC Physical Control Register for each physical channel. The HDLC Physical Control Register bit mapping is shown in Figure 8, while the bit definitions are shown in Table 16.
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Figure 8: HDLC Physical Control Register Bit Mapping
Figure Top x-ref 8
2928 30 31
LoopRXEN
TXEN
Number of Sub-Channels - 1
MSB LSB Unused
hdlc_phy_control_register_bit_mapping.eps
0 7 8
Table 16: HDLC Physical Control Register Bit Definitions
Bit(s) Name Access Reset Value Description
0 - 7 NSC ReadC_NUM_SUB_CHANNELS - 1
Number of Sub-Channels - 1.This is the generic C_NUM_SUB_CHANNELS - 1 that is a read only. Writing to these bits is ignored and has no effect.
8-28 Unused Undefined Reserved
29 RXEN Read/Write 0
HDLC Receiver Enable. This bit must be set before any of the RXCA bits have an effect.1 enables the HDLC RX controller.0 disables the HDLC RX controller.
30 TXEN Read/Write 0
HDLC Transmitter Enable. This bit must be set before any of the TXCR bits have an effect. 1 enables the HDLC TX controller. 0 disables the HDLC TX controller.
31 LOOP Read/Write 0
Loop Back Test. Note that when toggling this bit, it is best if the receiver is disabled (RXEN = 0) to prevent any spurious events from occurring. Loop Back Test is not supported with DMA.1 - Loop Back Test is enabled0 - Loop Back Test is disabled
Number of Aborted Frames (ABRT) C_BASE_ADDR + 0x1114, 0x1124, 0x1134, ...
This field contains the number of aborted frames received per physical channel. The value will count to 65535, then rollover to 0, and continue counting. A write of any value will reset this value. The bit mapping for this field is shown in Figure 9, while the Aborted Frame Counter bit definitions are listed inTable 17.
Figure 9: HDLC Number of Aborted Frames Bit Mapping
Figure Top x-ref 9
31
AFC_EN
Unused Rx Aborted Frame Count
hdlc_number_aborted_frames_bit_mapping.eps
15140 16
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Table 17: Aborted Frame Counter
Bit(s) Name Access Reset Value Description
0-14 Unused Undefined Reserved
15 AFC_EN Read/Write 0
Setting this bit to a 0 will disable event (9), counter rollover, from occurring.Setting this bit to a 1 will allow event (9), counter rollover, to be passed to the Rx Event FIFO and then to the IPIF for interrupt processing.
16-31Rx Aborted
Frame CountRead/Write 0x0000 This register is cleared to 0x00 with every write.
Number of CRC Errors (CRCE) C_BASE_ADDR + 0x1118, 0x1128, 0x1138, ...
This field contains the number of CRC errors received per physical channel. The value will count to 65535, then rollover to 0, and continue counting. A write of any value will reset this value. The bit mapping for this field is shown in Figure 10, while the bit description is listed in Table 18.
Figure 10: HDLC Number of CRC Errors Bit Mapping
Figure Top x-ref 10
31
CCT_EN
Unused Rx CRC Error Count
hdlc_number_crc_errors_bit_mapping.eps
15140 16
Table 18: FCS Error Counter
Bit(s) Name AccessReset Value
Description
0-14 Unused Undefined Reserved
15 CCT_EN Read/Write 0
Setting this bit to a 0 will disable event (9), counter rollover, from occurring.Setting this bit to a 1 will allow event (9), counter rollover, to be passed to the IPIF for interrupt processing.
16-31Rx CRC
Error Count
Read/Write 0x0000 This register is cleared to 0x00 with every write.
HDLC RX Sub-channel Control and Address (RXCA)
There is one HDLC RX Sub-channel Control and Address register for each sub-channel. The HDLC RX Control and Address Bit Mapping register is shown in Figure 11, while the bit mapping for this register is listed in Table 19.
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Figure 11: HDLC Rx Sub-channel Control and Address Bit MappingFigure Top x-ref 11
hdlc_rx_subchan_control_addr_bit_mapping.eps
0 7 8 1615 17 27 282625 29 30 31
High Byte of Slave Address Rx_Event(0)EN Unused ADSIZE RXSEN
Low Byte of Slave Address CRC ADREC BAMEN
RMADDR
Table 19: HDLC RX Control and Address Bit Definitions
Bit(s) Name AccessReset Value
Description
0-7High Byte of
Slave Address
Read/Read Modify Write
UndefinedAddress used by the OPB HDLC RX Interface for 16 bit addresses
8-15Low Byte of
Slave Address
Read/Read Modify Write
UndefinedAddress used by the OPB HDLC RX Interface for 8 or 16 bit addresses
16Rx_Event
(0)_EnRead/Read Modify Write
Undefined
Rx_Event(0)_En. Receive Data FIFO Overrun enable. Setting this bit to a 0 will disable the Receive Data FIFO Overrun RX_Event(1). Setting this bit to a 1 will allow the Receive Data FIFO Overrun RX_Event(1) to be passed to the IPIF for further interrupt processing.
17 - 25 ReservedRead/Read Modify Write
Undefined Reserved
26 CRCRead/Read Modify Write
UndefinedCRC select. 1 - CRC-32 is used for the FCS field0 - CRC-CCITT is used for the FCS fields.
27 ADSIZERead/Read Modify Write
UndefinedAddress Size. 1 - 16 bits of address are used for address recognition.0 - 8 bit of address are used for address recognition.
28 ADRECRead/Read Modify Write
Undefined
Address Recognition. 1 Address and data is written to the receive memory buffer when the address received matches the address stored in the address register(s).0 All addresses and data is written to the receive memory buffer
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HDLC TX Sub-channel Control Register (TXCR)
The HDLC TX Sub-channel Control Register is shown in Figure 12, while the bit definitions for the register are listed Table 20.
Figure 12: HDLC Tx Sub-channel Control Register Bit Mapping
Figure Top x-ref 12
hdlc_tx_subchan_control_register_bit_mapping.eps
0 171615 18 2827 29 30 31
Unused Tx_Event(2)EN Unused DISCRC TXFA
Tx_Event(0)EN TXCRC TXSEN
29 RMADRRead/Read Modify Write
Undefined
Address Field Removed. Note that when the Address Recognition is set to 0 the address field is written to the receive buffer regardless of this bit setting.1 The address field is not written to the receive memory buffer0 The address field is written to the receive memory buffer
30 BAMENRead/Read Modify Write
Undefined
Broadcast address match. This bit will determine if the receiver responds to a broadcast address.1 Receiver does respond to an 8 bit broadcast address (0XFF).0 Receiver does not respond to a broadcast address.
31 RXSENRead/Read Modify Write
Undefined
HDLC Receiver Sub-channel Enable. This bit must be set before any other CR bits have any effect.1 enables the HDLC RX controller.0 resets and disables the HDLC RX controller.
Table 20: HDLC TX Control Register Bit Definitions
Bit(s) Name Access Reset Value Description
0-15 Reserved Undefined Reserved.
16Transmit Complete
Event(0) EnableRead/Write
Undefined
Transmit Event(0) Enable. Setting this bit to a 0 will disable the Transmit Complete Event(0). Setting this bit to a 1 will allow the Transmit Complete Event(0) to be passed to the IPIF for further interrupt processing.
17Transmit Complete
Event(2) EnableRead/Write Undefined
Transmit Event(2) Enable. Setting this bit to a 0 will disable the Transmit Complete Event(2). Setting this bit to a 1 will allow the Transmit Complete Event(2) to be passed to the IPIF for further interrupt processing.
18 - 27 Reserved Undefined Reserved.
Table 19: HDLC RX Control and Address Bit Definitions (Contd)
Bit(s) Name AccessReset Value
Description
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Receive (read) Data Channel FIFO Status (RXDFS)
There is one Receive Data Channel FIFO Status for each sub-channel. The register bit mapping is shown in , while the bit definitions are described in Table 21.
Figure 13: HDLC Receive Data Channel FIFO Status Bit Mapping
Figure Top x-ref 13
hdlc_rec_data_chan_fifo_stat_bit_mapping.eps
0 2 31 31
Almost Empty Occupancy
Empty HalfEmpty
28 DISCRCRead/Write
Undefined
Disable CRC Generation.1 = A CRC value of all zeros will generated and appended on to the transmitted data.0 = CRC will be generated and appended on to the transmitted data.
29 TXCRC Read/Write UndefinedTX CRC size. 1 = CRC-32 is used for the FCS field0 = CRC-CCITT is used for the FCS field
30 TXFA Read/Write1 Undefined
TX Frame Abort. Setting this bit to a 1 will cause the transmitter to initiate a frame abort sequence. Abort flags will be sent as long as this bit is set to a 1.
31 TXSEN Read/Write Undefined
HDLC Transmitter Sub-channel Enable. This bit must be set before any other TXCR bits have any effect. 1 enables the HDLC transmitter to read data, if present, from the transmit channel FIFO. 0 prevents the HDLC transmitter from reading data out of the transmit channel FIFO. This does not prevent any data currently in the 32 shift register or the CRC or idle flags from being transmitted.
Notes: 1. The abort flag must occur between a start flag and an ending flag for the receiver to detect and report the abort
condition. The transmitter will transmit all data remaining in the packet before generating the abort flag.
Table 21: Receive Data Channel FIFO Status
Bit(s) Name Access Reset Value Description
0 Empty ReadRXDFS Empty -- Please refer to the Xilinx Channel FIFO for the complete specification of the receive channel FIFO status
1Almost Empty
ReadRXDFS Almost Empty -- Please refer to the Xilinx Channel FIFO for the complete specification of the receive channel FIFO status
Table 20: HDLC TX Control Register Bit Definitions (Contd)
Bit(s) Name Access Reset Value Description
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Receive (read) Data Channel FIFO (RXDF)
This field contains data received from the HDLC. See Figure 14 and Table 22.
Figure 14: HDLC Receive Data
Figure Top x-ref 14
hdlc_receive_data.eps
0 31
Rx Data
Table 22: Receive Memory Buffer
Bit(s) Name Access Reset Value Description
0-31 RXDF ReadReceived Data is buffered in this FIFO prior to either a DMA or software transfer.(1,2)
Notes: 1. For example if a Virtex-II is chosen and the receive memory depth is set for 65536 bytes (32 BRAMs will be
used) and 24 sub-channels is selected, then each sub channel will have 2048 bytes of buffering, ((65536/32) - 4). 65536 is the receive memory depth, 32 is the next power of two equal to or greater than the number of sub-channels, and 4 bytes are used for sub channel FIFO status.
2. Please refer to the Xilinx Channel FIFO for the complete specification of the receive (read) channel FIFO data.
Transmit (write) Data Channel FIFO Status (TXDFS)
There is one Transmit Data Channel FIFO Status for each sub-channel. See Figure 15and Table 23.
Figure 15: HDLC Transmit Data Channel FIFO Status Bit Mapping
Figure Top x-ref 15
hdlc_trans_data_chan_fifo_stat_bit_mapping.eps
0 2 3 41 31
AlmostFull Empty Vacancy
HalfFull
Full
2Half
EmptyRead
RXDFS Half Empty -- Please refer to the Xilinx Channel FIFO for the complete specification of the receive channel FIFO status
3-31 RXDFS ReadRXDFS Occupancy -- Please refer to the Xilinx Channel FIFO for the complete specification of the receive channel FIFO status
Table 21: Receive Data Channel FIFO Status
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Table 23: Transmit Data Channel FIFO Status
Bit(s) Name Access Reset Value Description
0 Full ReadTXDFS Full -- Please refer to the Xilinx Channel FIFO for the complete specification of the transmit (write) channel FIFO status
1Almost
FullRead
TXDFS Almost Full -- Please refer to the Xilinx Channel FIFO for the complete specification of the transmit (write) channel FIFO status
2 Half Full ReadTXDFS Half Full -- Please refer to the Xilinx Channel FIFO for the complete specification of the transmit (write) channel FIFO status
3 Empty ReadTXDFS Empty -- Please refer to the Xilinx Channel FIFO for the complete specification of the transmit (write) channel FIFO status
4-31 Vacancy ReadTXDFS Vacancy -- Please refer to the Xilinx Channel FIFO for the complete specification of the transmit (write) channel FIFO status
Transmit (write) Channel FIFO (TXDF)
This field contains the data to be transmitted on the HDLC. See Figure 16 and Table 24.
Figure 16: HDLC Transmit Data
Figure Top x-ref 16
hdlc_transmit_data.eps
0 31
Tx Data
Table 24: Transmit Memory Buffer
Bit(s) Name Access Reset Value Description
0-31 TXDF Write UndefinedTransmit Data is buffered in this FIFO prior to the HDLC
transmitting this data.(1,2)
Notes: 1. For example if a Virtex-II is chosen and the receive memory depth is set for 65536 bytes (32 BRAMs will be
used) and 5 sub-channels is selected then each sub channel will have 8188 bytes of buffering, ((65536/8) - 4). 65536 is the transmit memory depth, 8 is the next power of two equal to or greater than the number of sub-channels, 4 bytes are used for each sub-channel FIFO status
2. Please refer to the Xilinx Channel FIFO for the complete specification of the transmit (write) channel FIFO data.
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HDLC Block DiagramFigure 17 shows the top-level block diagram for the single channel HDLC.
Figure 17: HDLC Module Block Diagram
Figure Top x-ref 17
ByteCount
CRCCheck
ZeroDelete
RagMatch
AddrDetect
CRCE
ABRT
PhysicalChannel
PCCR
ByteCount
CRCGen
ZeroInsert
RagGen
Rx LengthFIFO
Rx StatusFIFO
Rx FrameControl
Rx Controland Status
Tx LengthFIFO
Tx StatusFIFO
Tx FrameControl
Tx Controland Status
BRAM Contex Storagesub-channel registers
Rx Channel FIFO1 BRAM minimum
32 BRAM maximum
Rx Channel FIFO1 BRAM minimum
32 BRAM maximum
DualPortFIFO
rxd
OPB_CLK
DualPortFIFO
txd
OPB_CLK
LoopBackDualPortFIFO
txd
OPB_CLK
rxcl loop back
HDLC #1 1-32 TDM Sub Channels
RXDO
RXCLK0
TXCLK0
RXDEN0
TXDEN0
TXD0
RX_CHN_SEL0
TX_CHN_SEL0
RXD1
RXCLK1
TXCLK1
RXDEN1
TXDEN1
TXD1
RX_CHN_SEL1
TX_CHN_SEL1
RXD7
RXCLK7
TXCLK7
RXDEN7
TXDEN7
TXD7
RX_CHN_SEL7
TX_CHN_SEL7
ByteCount
CRCCheck
ZeroDelete
RagMatch
AddrDetect
OCRE
ABRT
PhysicalChannel
POOR
ByteCount
CRCGen
ZeroInsert
RagGen
Rx LengthFIFO
Rx StatusFIFO
Rx FrameControl
Rx Controland Status
Tx LengthFIFO
Tx StatusFIFO
Tx FrameControl
Tx Controland Status
BRAM Contex Storagesub-channel registers
Rx Channel FIFO1 BRAM minimum
32 BRAM maximum
Rx Channel FIFO1 BRAM minimum
32 BRAM maximum
DualPortFIFO
rxcl
OPB_CLK
DualPortFIFO
rxcl
OPB_CLK
LoopBackDualPortFIFO
rxcl
OPB_CLK
rxcl loop back
HDLC #2 1-32 TDM Sub Channels
ByteCount
CRCCheck
ZeroDelete
RagMatch
AddrDetect
OCRE
ABRT
PhysicalChannel
POOR
ByteCount
CRCGen
ZeroInsert
RagGen
Rx LengthFIFO
Rx StatusFIFO
Rx FrameControl
Rx Controland Status
Tx LengthFIFO
Tx StatusFIFO
Tx FrameControl
Tx Controland Status
BRAM Contex Storagesub-channel registers
Rx Channel FIFO1 BRAM minimum
32 BRAM maximum
Rx Channel FIFO1 BRAM minimum
32 BRAM maximum
DualPortFIFO
rxcl
OPB_CLK
DualPortFIFO
rxcl
OPB_CLK
LoopBackDualPortFIFO
rxcl
OPB_CLK
rxcl loop back
HDLC #3 1-32 TDM Sub Channels
DeviceRegisterInterface
StatusFIFO
Event 4 & 5
Tx EventFIFO
Event 0 &1
MSCR
Rx EventFIFO
Event 2 & 3
IPIFRegister Set
Containing a256 Channel
DMA Controller
IPIF
hdlc_multichan_if_block_diagram.eps
Frame Check Sequence (FCS)
This block provides a CRC generation. The block is preset to force the registers to a 1 (and hence comply to CCITT specifications). The CRC Calculator generates a CRC code from the following polynomials.
CRC-CCITT shown in Figure 18 uses the following polynomial.
G(x) = x16 + x12 + x5 + 1.
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Figure 18: CRC - CCITT Code Generation
Figure Top x-ref 18
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DataOutData In
Clock In
crc_code_generation.eps
CRC-32, shown in Figure 19 uses the following polynomial.
G(x)=x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Figure 19: CRC-32 Code Generation
Figure Top x-ref 19
0 2 31
1716 18 19 20 2928 30 3122
12 13 14 154 5 6 7 8 9 1110
Data Out
Data In
Clock In
crc32_code_generation.eps
2423 25 272621
Time Division Multiplexing (TDM)
The HDLC can support 1 to 32 TDM channels on a single physical channel.
If a physical channel is configured to have one sub channel then this physical channel does not implement any TDM functions. The transmit or receive data rate must be at least 10% slower than the OPB_CLK, a 100MHz OPB_CLK requires the Rx/Tx data rate to be less than or equal to 90MHz. The transmit data rate is determined by TxClk and Txden. The receive data rate is determine by RxClk and Rxden. There is a small asynchronous dual port FIFO that will buffer the Tx and Rx data. An overrun or under run of these FIFO is an error condition and is reported through the Tx or Rx Event FIFOs. This error condition indicates that the data rate is higher than the HDLC can handle.
If a physical channel has two or more sub channels configured than the TDM function is implemented. The transmit or receive data rates must be less the 1/3 the OPB_CLK, a 100MHz OPB_CLK requires the Tx/Rx data rate to be less than or equal to 33.3MHz. The TDM function uses internal BRAM to context switch the state of each sub channel, the current sub channel state is stored and the next sub channel state is retrieved. Figure 21 shows the timing for three different configurations of a physical channel, no TDM, TDM with two sub channels and TDM with 32 sub channels.
The transmit TDM will always start at sub channel zero and transmit 8 bits and then increment to sub channel 1 and transmit 8 bits. The sub channel will increment through the number of sub channels configured for this physical channel and then return to sub-channel zero. The Tx_Chnl_Sel indicates which sub channel the data bit is being transmitted to. The Txden and/or the TxClk can be used to control the data output from the Tx channel.
The receive TDM channel is controlled by the Rx_Chnl_Sel input. Every time a change is detected on the Rx_Chnl_Sel a context switch occurs and processing on the new sub channel continues until a new sub channel is detected. It is possible to change sub channels with every RxClk, however a context switch requires up to 14 OPB_CLKs to perform the context switch so the Rx data rate must be less than or equal to 1/14 the OPB_CLK.
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Figure 20: Timing Information
Figure Top x-ref 20
Tx Channel 0 Tx Channel 1 Tx Channel 0 Tx Channel 1 Tx Channel 0 Tx Channel 1 Tx Channel 00 7 0 7 0 7 0 7 0 7 0 7 0 7 0
Tx Clock
Tx Clock
Tx Data Tx Data
Tx Channel 0 Tx Channel 1 Tx Channel 2 Tx Channel 3 Tx Channel 30 Tx Channel 31 Tx Channel 00 7 0 6 0 7 0 7 0 7 0 7 0 7
Tx Clock
1 2 3 4 5 6 1 2 3 4 5 6
Txden
Txden
1 2 3 4 5 7 0 71 2 3 4 5 6
Txden
Tx Data Tx Data
32 Sub Channels configured
2 Sub Channels configured
Single Sub Channel configured
Figure 21: I/O Timing
Figure Top x-ref 21
TxClk
TxDen
TxD
Tx_Chnl_Sel
RxClk
RxDen
Rx_Chnl_Sel
RxD
Eighth bit of Chnl 0 First bit of Chnl 1 Second Bit of Chnl 1
Channel 0 Channel 1
Tsu
Th
Tsu
Th
Tsu
Th
Tsu
Th
Clk_to_Q Clk_to_Q Clk_to_Q
Tsu
Tsu
Th
Th
Clk_to_Q
Tsu
Tsu
Th
Th
Clk_to_Q
Tsu
Th
Tsu
Tsu
Th
Th
Clk_to_Q
Design Implementation
Design Tools
Xilinxs XST is the synthesis tool used for synthesizing the HDLC.
Target Technology
The intended target technology is a Virtex-II Pro FPGA.
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Device Utilization and Performance Benchmarks
Because the HDLC is a module that will be used with other design pieces in the FPGA, the utilization and timing numbers reported in this section are just estimates. As the HDLC is combined with other pieces of the FPGA design, the utilization of FPGA resources and timing of the HDLC design will vary from the results reported here.
In order to analyze the HDLC timing within the FPGA, a design was created that instantiated the HDLC with the following parameters set.
The HDLC benchmarks are shown in Table 25 for a Virtex-II XC2V6000-6 FPGA, using Design Manager release version 6.2.01i application version G.29.
Table 25: OPB HDLC Interface FPGA Performance and Resource Utilization Benchmarks (Virtex-II XC2V6000-6)
Parameter Values Device Resources fMAX
C_D
MA
_PR
ES
EN
T
C_N
UM
_CH
AN
NE
LS
C_N
UM
_SU
B_C
HA
NN
ELS
_0
C_N
UM
_SU
B_C
HA
NN
ELS
_1
C_N
UM
_SU
B_C
HA
NN
ELS
_2
C_N
UM
_SU
B_C
HA
NN
ELS
_3
C_N
UM
_SU
B_C
HA
NN
ELS
_4
C_N
UM
_SU
B_C
HA
NN
ELS
_5
C_N
UM
_SU
B_C
HA
NN
ELS
_6
C_N
UM
_SU
B_C
HA
NN
ELS
_7
C_T
X_M
EM
_DE
PT
H(4
)
C_R
X_M
EM
_DE
PT
H(4
)
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_0
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_1
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_2
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_3
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_4
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_5
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_6
C_N
UM
_SU
B_C
HA
NN
EL_
BIT
SS
_7
Slic
es
Slic
e F
lip-F
lops
4-in
put L
UT
s
BR
AM
s
GC
LKs
MH
z
IPIF
Rem
oved
NA 1 1 0 0 0 0 0 0 0
2048
2048 1 0 0 0 0 0 0 0 743
604
1078 2 1(3)
151
NA 1 1 1 0 0 0 0 0 0 0
2048
2048 1 0 0 0 0 0 0 0 860
794
1203 2 1(3)
151
NA 2 1 1 0 0 0 0 0 0 0
2048
2048 1 0 0 0 0 0 0 0
1614
1246
2513 3 1(3)
100
NA 1 1 2 0 0 0 0 0 0 0
2048
2048 1 0 0 0 0 0 0 0
1172
864
1942 4 1(3)
144
NA 2 1 2 0 0 0 0 0 0 0
2048
2048 1 0 0 0 0 0 0 0
1939
1319
3256 5 1(3)
100
NA 1 1 2 0 0 0 0 0 0 0
4096
4096 1 0 0 0 0 0 0 0
1176
874
1955 6 1(3)
117
NA 1 1 4 0 0 0 0 0 0 0
2048
2048 2 0 0 0 0 0 0 0
1151
852
1903 4 1(3)
119
NA 1 1 8 0 0 0 0 0 0 0
2048
2048 3 0 0 0 0 0 0 0
1143
845
1893 4 1(3)
119
NA 1 1 16 0 0 0 0 0 0 0 2048
2048 4 0 0 0 0 0 0 0
1143
838
1874 4 1(3)
115
NA 1 1 24 0 0 0 0 0 0 0 2048
2048 5 0 0 0 0 0 0 0
1142
834
1879 4 1(3)
116
NA 1 1 24 0 0 0 0 0 0 0
6553
6
6553
6
5 0 0 0 0 0 0 0
1267
921
2062 74 1(3)
99
NA 1 1 32 0 0 0 0 0 0 0 2048
2048 5 0 0 0 0 0 0 0
1135
837
1862 4 1(3)
122
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OPB Multi Channel HDLC Interface (v2.01a)
DS438 DecProduct Sp
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Specification Exceptions
Exceptions to the HDLC specification
There are currently no known exceptions.
Reference DocumentsThe the International Telecommunication Union ITU-T Q.921 (09/97) reference document to gain a greater understanding of the OPB HDLC Interface design.
NA 2 1 32 0 0 0 0 0 0 0 2048
2048 5 0 0 0 0 0 0 0
1929
1302
3215 5 1(3)
100
NA 1 2 1 1 0 0 0 0 0 0
2048
2048 1 1 0 0 0 0 0 0
1541
1414
2091 4 1(3)
119
NA 1 2 1 2 0 0 0 0 0 0
4096
2048 1 1 0 0 0 0 0 0
1841
1504
2868 8 1(3)
119
NA 1 2 2 2 0 0 0 0 0 0
2048
2048 1 1 0 0 0 0 0 0
2156
1554
3638 8 1(3)
118
NA 1 2 32 32 0 0 0 0 0 0 2048
2048 5 5 0 0 0 0 0 0
2089
1496
3475 8 1(3)
108
NA 1 2 32 32 0 0 0 0 0 0
3276
8
3276
8
5 5 0 0 0 0 0 0
2279
1621
3817 76 1(3)
98
NA 1 4 1 1 1 1 0 0 0 0
2048
2048 1 1 1 1 0 0 0 0
2886
2648
3909 8 1(3)
125
NA 1 4 32 32 32 32 0 0 0 0 2048
2048 5 5 5 5 0 0 0 0
4047
2813
6703 16 1(3)
104
NA 1 8 1 1 1 1 1 1 1 1
2048
2048 1 1 1 1 1 1 1 1
5687
5116
7645 16 1(3)
104
NA 1 8 32 32 32 32 32 32 32 32 2048
2048 5 5 5 5 5 5 5 5
7887
5442
1318
4
32 1(3)
103
Notes: 1. These benchmark designs contain only the HDLC without any additional logic. Benchmark numbers approach the performance ceiling rather than
representing performance under typical user conditions. ISE version 6.1 was used for synthesis, map and PAR. The design was targeted into a Virtex-II Pro XC2vP20-fg676-6
2. The C_OPB_CLK_PERIOD_PS is set to 10000 for the above examples.3. It is preferable to use a global clock buffer for the Receive Clock and Transmit Clock. If global clock buffers are not used, care must be taken to ensure
the setup and hold times of the inputs are met.4. To reduce the complexity of this table all physical channels had the same value for C_TX_MEM_DEPTH, and for C_RX_MEM_DEPTH. This is not a
requirement for the design, but an attempt to make this table more readable.
Table 25: OPB HDLC Interface FPGA Performance and Resource Utilization Benchmarks (Virtex-II XC2V6000-6)
ember 1, 2005 www.xilinx.com 37ecification
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OPB Multi Channel HDLC Interface (v2.01a)
38
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Revision History
Date Version Revision
05/01/03 2.0 Initial Xilinx release.
05/21/03 2.1 Update to current template; update for EDK minor SP2
07/15/03 2.2 Update for EDK Granite
3/29/04 2.3 Updates for DMA and Write Channel FIFO
5/1/04 2.4 Updated to new hardware version V2.01a
8/19/04 2.5 Updated for Gmm; updated trademarks and supported device family listing.
9/22/04 2.5.1In Table 16, added Loop Back Test is not supported with DMA to Description column for LOOP signal.
3/18/05 2.6Converted to new DS template; updated figures to Xilinx graphic standards; revised text for HDLC Design Parameters; added Figure 20; made other minor content edits; added Spartan-3E to supported device family listing.
12/1/05 2.7 Added Spartan-3E to supported device listing.
www.xilinx.com DS438 December 1, 2005Product Specification
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OPB Multi Channel HDLC Interface (v2.01a)IntroductionFeaturesEvaluation VersionHDLC ProtocolHDLC Design ParametersAllowable Parameter CombinationsHDLC I/O SignalsHDLC Port DependenciesHDLC Register DescriptionsIPIF Registers used by the HDLCHDLC RegistersExample Memory MapHDLC Device Control Register (MSCR), C_BASE_ADDR + 0x1100Status FIFO (SF) C_BASE_ADDR + 0x1000HDLC EventsHDLC Tx Event FIFO (TXEF) C_BASE_ADDR + 0x1104HDLC Rx Event FIFO (RXEF) C_BASE_ADDR + 0x1108HDLC Physical Control Register (PCCR) C_BASE_ADDR + 0x1110, 0x1120, 0x1130, ...Number of Aborted Frames (ABRT) C_BASE_ADDR + 0x1114, 0x1124, 0x1134, ...Number of CRC Errors (CRCE) C_BASE_ADDR + 0x1118, 0x1128, 0x1138, ...HDLC RX Sub-channel Control and Address (RXCA)HDLC TX Sub-channel Control Register (TXCR)Receive (read) Data Channel FIFO Status (RXDFS)Receive (read) Data Channel FIFO (RXDF)Transmit (write) Data Channel FIFO Status (TXDFS)Transmit (write) Channel FIFO (TXDF)HDLC Block DiagramFrame Check Sequence (FCS)Time Division Multiplexing (TDM)Design ImplementationDesign ToolsTarget TechnologyDevice Utilization and Performance BenchmarksSpecification ExceptionsExceptions to the HDLC specificationReference DocumentsRevision History