dr. cu 2.0: a scalable detailed routing framework with ... · multi-threaded maze routing...
TRANSCRIPT
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Dr. CU 2.0: A Scalable Detailed Routing Frameworkwith Correct-by-Construction Design Rule Satisfaction∗
Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen,Evangeline F. Y. Young
∗Source code is available at h�ps://github.com/cuhk-eda/dr-cu.1 / 26
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Outline
Introduction
Preliminary
Algorithms
Experimental Results
Conclusion
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Outline
Introduction
Preliminary
Algorithms
Experimental Results
Conclusion
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Detailed Routing
Figure 1: �ad-Core Design [Liu et al. 2019].
I 1M nets in 20K × 20K × 10 grid points, hardlyrouted by ILP-based a or SAT-based b methods.
I Complicated design rules:I Parallel run length (PRL) spacing c.I End-of-line (EOL) spacing.I EOL spacing with parallel edges d.I Corner-to-corner (C2C) spacing e.
a[Kahng, Wang, and Xu 2018]b[Park et al. 2019]c[Qi, Cai, and Zhou 2015]d[Yu et al. 2015]e[Côté, Pierrat, and Hurat 2004]
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Problem Formulation
GivenI technology node and design rules,I placement result with netlist,I routing tracks and blockages, andI route guides generated from global routing,
route all nets minimizing a weighted sum ofI total wire-length and via count,I out-of-guide, o�-track, wrong-way usage, andI design rule violations.
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Contributions
For Each Rip-up and Reroute Iteration
Access Point Assignment
Multi-threaded Maze Routing
Multi-threaded Via Selection
Post-routing Refinement
Figure 2: Detailed Routing Flow.
I Compute valid access points of each pin andcreate o�-track vias if no same-layer accesspoint is valid.
I Handle end-of-line spacing with parallel edgesin a correct-by-construction manner.
I Fix corner-to-corner spacing violations inpost-processing.
I Develop a lookup-table-based via insertionmethod and select violation-free via types fromthe cell library.
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Outline
Introduction
Preliminary
Algorithms
Experimental Results
Conclusion
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Two-Level Sparse Data Structures
routing region of a net routing topologylocal grid graph
global grid graph
record
edge
usage
maze
route
querycache
Figure 3: Global and Local Grid Graph.
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Parallel Run Length Spacing
R1
R2
R2
R2
w2
w1
lt
lb
sb
smst
Figure 4: Parallel Run Length Spacing.
The parallel run length (PRL)spacing requirements between twowires of di�erent nets depend onboth width and PRL of the twowires.
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End-of-line Spacing
Figure 5: Example of Triple Pa�erning Layout Decomposition †.
eolWithin
eolWidth
eolSpace
Metal
EOL Spacing
Figure 6: EOL Spacing without Parallel Edges.
eolWithin
eolWidth
eolSpace
Metal
EOL Spacing
parSpace
eolWithin parWithin
Parallel Edge Region
Figure 7: EOL Spacing with Parallel Edges.
†[Yu et al. 2015] 8 / 26
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Corner-to-Corner Spacing
w eolWidth<latexit sha1_base64="Xjl2NlYS/IYscB7kNQ47CiBlpoA=">AAAB+XicbVBNS8NAEN34WetX1KOXxVbwVJJe7LHgxWMF+wFtKJvNpF262Q27m0oJ/SdePCji1X/izX/jts1BWx8MPN6bYWZemHKmjed9O1vbO7t7+6WD8uHR8cmpe3be0TJTFNpUcql6IdHAmYC2YYZDL1VAkpBDN5zcLfzuFJRmUjyaWQpBQkaCxYwSY6Wh61af8IADBsm7LDLj6tCteDVvCbxJ/IJUUIHW0P0aRJJmCQhDOdG673upCXKiDKMc5uVBpiEldEJG0LdUkAR0kC8vn+Nrq0Q4lsqWMHip/p7ISaL1LAltZ0LMWK97C/E/r5+ZuBHkTKSZAUFXi+KMYyPxIgYcMQXU8JklhCpmb8V0TBShxoZVtiH46y9vkk695ns1/6FeaTaKOEroEl2hG+SjW9RE96iF2oiiKXpGr+jNyZ0X5935WLVuOcXMBfoD5/MHLd6Sqw==</latexit><latexit sha1_base64="Xjl2NlYS/IYscB7kNQ47CiBlpoA=">AAAB+XicbVBNS8NAEN34WetX1KOXxVbwVJJe7LHgxWMF+wFtKJvNpF262Q27m0oJ/SdePCji1X/izX/jts1BWx8MPN6bYWZemHKmjed9O1vbO7t7+6WD8uHR8cmpe3be0TJTFNpUcql6IdHAmYC2YYZDL1VAkpBDN5zcLfzuFJRmUjyaWQpBQkaCxYwSY6Wh61af8IADBsm7LDLj6tCteDVvCbxJ/IJUUIHW0P0aRJJmCQhDOdG673upCXKiDKMc5uVBpiEldEJG0LdUkAR0kC8vn+Nrq0Q4lsqWMHip/p7ISaL1LAltZ0LMWK97C/E/r5+ZuBHkTKSZAUFXi+KMYyPxIgYcMQXU8JklhCpmb8V0TBShxoZVtiH46y9vkk695ns1/6FeaTaKOEroEl2hG+SjW9RE96iF2oiiKXpGr+jNyZ0X5935WLVuOcXMBfoD5/MHLd6Sqw==</latexit>
w eolWidth<latexit sha1_base64="Xjl2NlYS/IYscB7kNQ47CiBlpoA=">AAAB+XicbVBNS8NAEN34WetX1KOXxVbwVJJe7LHgxWMF+wFtKJvNpF262Q27m0oJ/SdePCji1X/izX/jts1BWx8MPN6bYWZemHKmjed9O1vbO7t7+6WD8uHR8cmpe3be0TJTFNpUcql6IdHAmYC2YYZDL1VAkpBDN5zcLfzuFJRmUjyaWQpBQkaCxYwSY6Wh61af8IADBsm7LDLj6tCteDVvCbxJ/IJUUIHW0P0aRJJmCQhDOdG673upCXKiDKMc5uVBpiEldEJG0LdUkAR0kC8vn+Nrq0Q4lsqWMHip/p7ISaL1LAltZ0LMWK97C/E/r5+ZuBHkTKSZAUFXi+KMYyPxIgYcMQXU8JklhCpmb8V0TBShxoZVtiH46y9vkk695ns1/6FeaTaKOEroEl2hG+SjW9RE96iF2oiiKXpGr+jNyZ0X5935WLVuOcXMBfoD5/MHLd6Sqw==</latexit><latexit sha1_base64="Xjl2NlYS/IYscB7kNQ47CiBlpoA=">AAAB+XicbVBNS8NAEN34WetX1KOXxVbwVJJe7LHgxWMF+wFtKJvNpF262Q27m0oJ/SdePCji1X/izX/jts1BWx8MPN6bYWZemHKmjed9O1vbO7t7+6WD8uHR8cmpe3be0TJTFNpUcql6IdHAmYC2YYZDL1VAkpBDN5zcLfzuFJRmUjyaWQpBQkaCxYwSY6Wh61af8IADBsm7LDLj6tCteDVvCbxJ/IJUUIHW0P0aRJJmCQhDOdG673upCXKiDKMc5uVBpiEldEJG0LdUkAR0kC8vn+Nrq0Q4lsqWMHip/p7ISaL1LAltZ0LMWK97C/E/r5+ZuBHkTKSZAUFXi+KMYyPxIgYcMQXU8JklhCpmb8V0TBShxoZVtiH46y9vkk695ns1/6FeaTaKOEroEl2hG+SjW9RE96iF2oiiKXpGr+jNyZ0X5935WLVuOcXMBfoD5/MHLd6Sqw==</latexit>
Figure 8: C2C spacing does not apply.
w > eolWidth<latexit sha1_base64="ttTCwZFMox0LwI3sFQk9NA4SxyU=">AAAB9XicbVA9SwNBEN3zM8avqKXNYiJYhbs0ppKAjWUE8wHJGfb25pIle7vH7p4hHPkfNhaK2Ppf7Pw3bpIrNPHBwOO9GWbmBQln2rjut7OxubW9s1vYK+4fHB4dl05O21qmikKLSi5VNyAaOBPQMsxw6CYKSBxw6ATj27nfeQKlmRQPZpqAH5OhYBGjxFjpsTLBNxgk77DQjCqDUtmtugvgdeLlpIxyNAelr34oaRqDMJQTrXuemxg/I8owymFW7KcaEkLHZAg9SwWJQfvZ4uoZvrRKiCOpbAmDF+rviYzEWk/jwHbGxIz0qjcX//N6qYnqfsZEkhoQdLkoSjk2Es8jwCFTQA2fWkKoYvZWTEdEEWpsUEUbgrf68jpp16qeW/Xua+VGPY+jgM7RBbpCHrpGDXSHmqiFKFLoGb2iN2fivDjvzseydcPJZ87QHzifP/WzkXc=</latexit><latexit sha1_base64="ttTCwZFMox0LwI3sFQk9NA4SxyU=">AAAB9XicbVA9SwNBEN3zM8avqKXNYiJYhbs0ppKAjWUE8wHJGfb25pIle7vH7p4hHPkfNhaK2Ppf7Pw3bpIrNPHBwOO9GWbmBQln2rjut7OxubW9s1vYK+4fHB4dl05O21qmikKLSi5VNyAaOBPQMsxw6CYKSBxw6ATj27nfeQKlmRQPZpqAH5OhYBGjxFjpsTLBNxgk77DQjCqDUtmtugvgdeLlpIxyNAelr34oaRqDMJQTrXuemxg/I8owymFW7KcaEkLHZAg9SwWJQfvZ4uoZvrRKiCOpbAmDF+rviYzEWk/jwHbGxIz0qjcX//N6qYnqfsZEkhoQdLkoSjk2Es8jwCFTQA2fWkKoYvZWTEdEEWpsUEUbgrf68jpp16qeW/Xua+VGPY+jgM7RBbpCHrpGDXSHmqiFKFLoGb2iN2fivDjvzseydcPJZ87QHzifP/WzkXc=</latexit>
w > eolWidth<latexit sha1_base64="ttTCwZFMox0LwI3sFQk9NA4SxyU=">AAAB9XicbVA9SwNBEN3zM8avqKXNYiJYhbs0ppKAjWUE8wHJGfb25pIle7vH7p4hHPkfNhaK2Ppf7Pw3bpIrNPHBwOO9GWbmBQln2rjut7OxubW9s1vYK+4fHB4dl05O21qmikKLSi5VNyAaOBPQMsxw6CYKSBxw6ATj27nfeQKlmRQPZpqAH5OhYBGjxFjpsTLBNxgk77DQjCqDUtmtugvgdeLlpIxyNAelr34oaRqDMJQTrXuemxg/I8owymFW7KcaEkLHZAg9SwWJQfvZ4uoZvrRKiCOpbAmDF+rviYzEWk/jwHbGxIz0qjcX//N6qYnqfsZEkhoQdLkoSjk2Es8jwCFTQA2fWkKoYvZWTEdEEWpsUEUbgrf68jpp16qeW/Xua+VGPY+jgM7RBbpCHrpGDXSHmqiFKFLoGb2iN2fivDjvzseydcPJZ87QHzifP/WzkXc=</latexit><latexit sha1_base64="ttTCwZFMox0LwI3sFQk9NA4SxyU=">AAAB9XicbVA9SwNBEN3zM8avqKXNYiJYhbs0ppKAjWUE8wHJGfb25pIle7vH7p4hHPkfNhaK2Ppf7Pw3bpIrNPHBwOO9GWbmBQln2rjut7OxubW9s1vYK+4fHB4dl05O21qmikKLSi5VNyAaOBPQMsxw6CYKSBxw6ATj27nfeQKlmRQPZpqAH5OhYBGjxFjpsTLBNxgk77DQjCqDUtmtugvgdeLlpIxyNAelr34oaRqDMJQTrXuemxg/I8owymFW7KcaEkLHZAg9SwWJQfvZ4uoZvrRKiCOpbAmDF+rviYzEWk/jwHbGxIz0qjcX//N6qYnqfsZEkhoQdLkoSjk2Es8jwCFTQA2fWkKoYvZWTEdEEWpsUEUbgrf68jpp16qeW/Xua+VGPY+jgM7RBbpCHrpGDXSHmqiFKFLoGb2iN2fivDjvzseydcPJZ87QHzifP/WzkXc=</latexit>
Figure 9: C2C spacing applies.
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Outline
Introduction
Preliminary
Algorithms
Experimental Results
Conclusion
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Local Grid Graph Construction
Metal 1 Metal 2
(a) Before Expansion. (b) A�er Expansion.
Figure 10: Unconnected Route Guides.
I Expand route guides in preferredrouting direction for full connections.
I Expand in x- and y-direction for eachrip-up-and-reroute iteration.
I Extend to adjacent layers if thenumbers of violations exceed athreshold.
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Pin Access
I Assign same-layer surrounding grid points as access points by default.I Use di�-layer access points by an o�-track via if no valid same-layer access points.I Penalize other nets for using grid points above/below it before it is connected.
DSI
SE
OBS
Figure 11: No valid same-layer access point.
DSI
SE
OBS
Figure 12: Use o�-track via
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Via Type Selection Flow
For Each Rip-up and Reroute Iteration
LUT Construction
Multi-threaded Via Locationing
Multi-threaded Type Selection
Post-routing Type Selection
Figure 13: Detailed Routing Flow.
I Construct via conflict lookup tables (LUTs).I Determine via locations and generate routing
topology for a net.I Perform via type selection for the net.I Finally decide via type globally in a post
refinement stage.
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Via Conflict Lookup Table
I Via-pin/obstacle conflicts.I Via-wire conflicts.I Via-via conflicts.
M3 track
M4 track
candidate via using via type 1
conflict w.r.t. neighboring via
using via type 2
violation-free locations
forbidden locations/region
neighboring via using via type 2
Figure 14: Via-via LUT.
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Pessimistic Lookup Table
I Checking every via-typeduring routing istime-consuming.
I Merged LUTs records allsuspicious conflicts.
I Suspicious conflicts can beverified when the via typesare determined.
M3 track
M4 track
candidate via using via type 1
conflict w.r.t. via using via type 1
conflict w.r.t. via using via type 2
conflict w.r.t. via using via type 3
violation-free locations
forbidden regions union
Figure 15: Merged Via-via LUT.
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Parallel Run Length Spacing Handling
R1
R2
R2
R2
w2
w1
lt
lb
sb
smst
Figure 16: Parallel Run Length Spacing.
Figure 17: Spacing Table
Parallel Run Length0.00 0.22 0.47 0.63 1.50
Wid
th
0.00 0.05 0.05 0.05 0.05 0.050.09 0.05 0.06 0.06 0.06 0.060.16 0.05 0.10 0.10 0.10 0.100.47 0.05 0.10 0.13 0.13 0.130.63 0.05 0.10 0.13 0.15 0.151.50 0.05 0.10 0.13 0.15 0.50
Penalize some tracks along power and ground rails.
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End-of-line Spacing Handling
Assume that a parallel edge exist to avoid blocking neighboring tracks.
eolWithin
eolWidth
eolSpace
Metal
EOL Spacing
Figure 18: EOL Spacing without Parallel Edges.
eolWithin
eolWidth
eolSpace
Metal
EOL Spacing
parSpace
eolWithin parWithin
Parallel Edge Region
Figure 19: EOL Spacing with Parallel Edges.
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Corner-to-Corner Spacing HandlingSlightly extend an on-track wire segment that connects a wrong-way wire segment.
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(a)
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(b) (c) (d)
Figure 20: (a) Via applied to C2C. (b) Via not applied to C2C. (c) Wrong-way wire applied to C2C.(d) Wrong-way wire not applied to C2C.
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Outline
Introduction
Preliminary
Algorithms
Experimental Results
Conclusion
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Comparison with 1st in ISPD 2019 Contest ‡
0 0.5 1 1.5
# Short
# PRL
Score
Time
1
1
1
1
1.37
1.08
1.02
0.67
Average Ratio
1stOurs
0 1 2·108
9t1
9t2
9t3
9t4
9t5
9t6
9t7
9t8
9t9
9t10
Score
1stOurs
‡[Liu et al. 2019] 18 / 26
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Comparison with 1st in ISPD 2019 Contest §
0 2,000 4,000 6,000 8,000
9t1
9t2
9t3
9t4
9t5
9t6
9t7
9t8
9t9
9t10
Number of Shorts
1stOurs
0 1 2·104
9t1
9t2
9t3
9t4
9t5
9t6
9t7
9t8
9t9
9t10
Number of PRLs
1stOurs
§[Liu et al. 2019]19 / 26
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Comparison with [Chen et al. 2019]
0 1 2
Score
Time
1
1
1.69
0.85
Average Ratio
ChenOurs
0 0.5 1·108
8t1
8t2
8t3
8t4
8t5
8t6
8t7
8t8
8t9
8t10
Score
ChenOurs
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Comparison with [Chen et al. 2019]
0 0.5 1 1.5·105
8t1
8t2
8t3
8t4
8t5
8t6
8t7
8t8
8t9
8t10
Short Area
ChenOurs
0 1 2·104
8t1
8t2
8t3
8t4
8t5
8t6
8t7
8t8
8t9
8t10
Number of Spacing Violations
ChenOurs
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Comparison between Di�erent Se�ings
0 100 200
9t1
9t2
9t3
9t4
9t5
9t6
9t7
9t8
9t9
9t10
ISPD’19 �ality Score (×106)
(a) Upper-layer Access Points with O�-track Vias.
wo/ upper accessw/ upper access
0 100 200
9t1
9t2
9t3
9t4
9t5
9t6
9t7
9t8
9t9
9t10
ISPD’19 �ality Score (×106)
(b) Layer Expansion of Local Grid Graphs.
wo/ layer expansionw/ layer expansion
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Outline
Introduction
Preliminary
Algorithms
Experimental Results
Conclusion
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Conclusion
I Compute valid access points of each pin and create o�-track vias.
I Handle end-of-line spacing with parallel edges during routing.
I Fix corner-to-corner spacing violations in post-processing.
I Develop a lookup-table-based via insertion method.
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Thanks!
�estions?
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References I
Chen, Gengjie, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, andEvangeline FY Young (2019). “Detailed routing by sparse grid graph andminimum-area-captured path search”. In: Proceedings of the 24th Asia and SouthPacific Design Automation Conference. ACM, pp. 754–760.
Côté, Michel Luc, Christophe Pierrat, and Philippe Hurat (Oct. 2004). Accelerated layoutprocessing using OPC pre-processing. US Patent 6,807,663.
Kahng, Andrew B, Lutong Wang, and Bangqi Xu (2018). “TritonRoute: an initial detailedrouter for advanced VLSI technologies”. In: IEEE/ACM International Conference onComputer-Aided Design (ICCAD). IEEE, pp. 1–8.
Liu, Wen-Hao, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, andGracieli Posser (2019). “ISPD 2019 Initial Detailed Routing Contest and Benchmarkwith Advanced Routing Rules”. In: Proceedings of the 2019 International Symposium onPhysical Design. ACM, pp. 147–151.
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References II
Park, Dongwon, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, andChung-Kuan Cheng (2019). “ROAD: Routability Analysis and Diagnosis FrameworkBased on SAT Techniques.”. In: ACM International Symposium on Physical Design(ISPD), pp. 65–72.
Qi, Zhong-Dong, Yi-Ci Cai, and Qiang Zhou (2015). “Design-Rule-Aware CongestionModel with Explicit Modeling of Vias and Local Pin Access Paths”. In: Journal ofComputer Science and Technology 30.3, pp. 614–628.
Yu, Bei, Kun Yuan, Duo Ding, and David Z. Pan (Mar. 2015). “Layout Decomposition forTriple Pa�erning Lithography”. In: IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems (TCAD) 34.3, pp. 433–446.
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