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General DescriptionThe MAX8710/MAX8711/MAX8712/MAX8761 offer com-plete linear-regulator power-supply solutions for thin-filmtransistor (TFT) liquid-crystal-display (LCD) panels usedin LCD monitors and LCD TVs. All four devices include ahigh-performance AVDD linear regulator, a positive

charge-pump regulator, a negative charge-pump regula-tor, and built-in power-up sequence control. TheMAX8710/MAX8711/MAX8761 also include a high-cur-rent operational amplifier. Additionally, the MAX8710/MAX8761 provide logic-controlled high-voltage switchesto control the positive charge-pump output.

The linear regulator directly steps down the input voltageto generate the supply voltage for the source-driver ICs(AVDD ). The two built-in charge-pump regulatorsare used to generate the TFT gate-on and gate-off sup-

plies. The high-current operational amplifier is typicallyused to drive the LCD backplane (VCOM) and featureshigh output current (150mA), fast slew rate (12V/s), andwide bandwidth (12MHz). Its rail-to-rail inputs and outputmaximize flexibility.

The MAX8710/MAX8761 are available in a 24-pin thinQFN package, the MAX8711 is available in a 16-pin thinQFN package, and the MAX8712 is available in a 12-pinthin QFN package. All three packages are 4mm x 4mmwith a maximum thickness of 0.8mm for ultra-thin LCD

panel design The MAX8710/MAX8711/MAX8712 operC C

Features High-Performance Linear Regulator

1.6% Output AccuracyWorks with Small Ceramic Output CapacitorsFast Transient ResponseFoldback Current Limit

50mA Negative Regulated Charge Pump

20mA Positive Regulated Charge Pump withAdjustable Delay

Built-In Power-Up Sequence High-Current Operational Amplifier

(MAX8710/MAX8711/MAX8761)150mA Output Short-Circuit Current12V/s Slew Rate12MHz, -3dB BandwidthRail-to-Rail Inputs/Output

Dual-Mode High-Voltage Switches

(MAX8710/MAX8761) Thermal Protection Latched Fault Protection with Timer

MAX8

710/MAX8

711/MAX87

Low-Cost, Linear-Regulator

LCD Panel Power Supplies

Ordering Information

PART TEMP RANGE PIN-PACKAGE PKG

CODE

MAX8710ETG+ -40C to +100C24 Thin QFN

4mm x 4mmT2444-4

MAX8711ETE+ 40C to +100C16 Thin QFN

4mm x 4mm T2444 4

19-3174; Rev 1; 10/05

EVALUATIO

NKIT

AVAILABLE

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MAX8711/MA

X8712/MA

X8761



ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA= 0C to +85C. Typical values are at TA =+25C, unless otherwise noted.)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

CTL, FBL, FBP, FBN, SHDN, REF, THR to GND........-0.3V to +6VMODE, DLP to GND......................................-0.3V to VREF + 0.3VIN, INL to GND.........................................................-0.3V to +28VSUPCP, SUPB to GND.............................................-0.3V to +14VOUTL (MAX8710/MAX8761) -0.3V to +28VOUTL (MAX8711/MAX8712) -0.3V to +14V

POSB, OUTB, NEGB to GND.....................-0.3V to VSUPB + 0.3VDRVN, DRVP (MAX8710/MAX8761) .......-0.3V to (VSUPCP - 0.3V)DRVN, DRVP (MAX8711/MAX8712)...............-0.3V to (VIN - 0.3V)SRC to GND .............................................................-0.3V to +30VGON, DRN to GND.......................................-0.3V to VSRC + 0.3VDRN to GON .............................................................-30V to +30V

OUTB Maximum Continuous Output Current.....................75mADRVP RMS Output Current...................................................90mADRVN RMS Output Current ...............................................-150mAContinuous Power Dissipation (TA = +70C)

24-, 16-, and 12-Pin Thin QFN 4mm x 4mm(derate 16.9mW/C above +70C) ..............................1349mW

Operating Temperature RangeMAX8710/MAX8711/MAX8712 .......................-40C to +100CMAX8761...........................................................-40C to +85C

Junction Temperature........................................................+150CStorage Temperature Range ..............................-65C to +160CLead Temperature (soldering, 10s)...................................+300C

PARAMETER CONDITIONS MIN TYP MAX UNITS

IN Operating Supply Range 8 28 V

SHDN= GND 0.2 0.4IN Quiescent Current

SHDN= 3.3V 2.5mA

Duration to Trigger Fault Condition 216 oscillator clock cycles 44 msREF Output Voltage -10A < IREF < 1mA (excluding internal load) 4.9 5.0 5.1 V

SUPCP I S l R V

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MAX8

710/MAX8711/MAX87



ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA= 0C to +85C. Typical values are at TA =+25C, unless otherwise noted.)


OPERATIONAL AMPLIFIER (MAX8710/MAX8711/MAX8761)

SUPB Supply Operating Range 4.5 13.2 V

SUPB Supply Current Buffer configuration, VPOSB = 4V, no load 0.7 1.0 mA

Input Offset Voltage (VNEGB, VPOSB) = VSUPB/ 2, TA= +25C 0 12 mV

Input Bias Current (VNEGB, VPOSB) = VSUPB/ 2 -50 +1 +50 nA

Common-Mode Input Range VNEGB, VPOSB 0 VSUPB V

Common-Mode Rejection Ratio 0 (VNEGB, VPOSB) < VSUPB 50 90 dB

Open-Loop Gain 125 dB

IOUTB = 100AVSUPB -

15

VSUPB -

2

Output Voltage Swing HighIOUTB = 5mA

VSUPB -

150

VSUPB -

80

mV

IOUTB = -100A 2 15Output Voltage Swing LowIOUTB = -5mA 80 150

mV

Short to VSUPB/ 2, sourcing 50 150Short-Circuit Current

Short to VSUPB/ 2, sinking 50 140mA

Output CurrentBuffer configuration, VPOSB = 4V,

VOUTBerror < 10mV40 mA

P S l R j ti R ti 6V V 13 2V DC (V V ) V / 2 60 100 dB

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MAX8711/MA

X8712/MA

X8761



ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA= 0C to +85C. Typical values are at TA =+25C, unless otherwise noted.)


VFBN = 350mV 3 6 DRVN n-Channel On-ResistanceVFBN = 150mV 20 k

FBN Fault Trip Level Rising edge 700 mVNegative Charge-Pump Soft-StartPeriod

212 oscillator clock cycles in a 7-bit DAC 2.73 msSEQUENCE CONTROL

SHDNInput Low Voltage 0.6 V

SHDNInput High Voltage 2.0 V

SHDNInput Current 1 A

DLP Capacitor Charge Current During startup, VDLP= 1.0V 4 5 6 A

DLP Turn-On Threshold 2.375 2.5 2.625 VSHDN= low or fault tripped; DLP, FBP, FBN to GND 10

Pin Discharge Switch On-Resistance SHDN= low or fault tripped;

MODE, OUTL, OUTB to GND

MAX8710, SHDN= low or fault trip; GON to GND

1 k

POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES (MAX8710/MAX8761)

CTL Input Low Voltage 0.6 V

CTL Input High Voltage 2.0 V

CTL Input Leakage Current 1 +1 A

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MAX8

710/MAX8711/MAX87



ELECTRICAL CHARACTERISTICS(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = -40C to +100C (-40C to 85C forMAX8761), unless otherwise noted.) (Note 1)


REF Output Voltage -10A < IREF < 1mA (excluding internal load) 4.9 5.1 V

SUPCP Input Supply Range 2.7 13.2 V

Charge-Pump Regulators Operating

Frequency1200 1850 kHz

LINEAR REGULATOR

IOUTL = 50mA (MAX8710/MAX8711/MAX8712) 300Dropout Voltage

IOUTL = 200mA (MAX8761) 400mV

FBL Regulation Voltage IOUTL = 50mA 2.455 2.545 V

FBL Fault Trip Level Falling edge 1.96 2.04 V

FBL Line-Regulation ErrorVINL = VIN = 10.8V~13.2V, VOUTL = 10V,

IOUTL = 50mA15 mV

VFBL= 2.4V (MAX8710/MAX8711/MAX8712) 300Maximum OUTL Current

VFBL= 2.4V (MAX8761) 500mA

VIN = 12V, 5mA < IOUT < 300mA

(MAX8710/MAX8711/MAX8712)2

OUTL Load Regulation

VIN = 12V, 5mA < IOUT < 500mA (MAX8761) 2

%

OPERATIONAL AMPLIFIER (MAX8710/MAX8711/MAX8761)

SUPB Supply Current Buffer configuration, VPOSB = 4V, no load 1.0 mA

Input Offset Voltage (VNEGB, VPOSB) = VSUPB/ 2 14 mV

I 100 A VSUPB

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MAX8711/MA

X8712/MA

X8761



Note 1: Specifications to -40C and +85C are guaranteed by design, not production tested.

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA= -40C to +100C, (-40C to +85C forMAX8761), unless otherwise noted.) (Note 1)


VFBN = 350mV 6 DRVN n-Channel On-ResistanceVFBN = 150mV 20 k

SEQUENCE CONTROL

SHDNInput Low Voltage 0.6 V

MAX8710/MAX8711/MAX8712 2.0SHDNInput High Voltage

MAX8761 2.05V

DLP Capacitor Charge Current During startup, VDLP= 1.0V 4 6 ADLP Turn-On Threshold 2.375 2.625 VPOSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES (MAX8710/MAX8761)

SRC Input Current VMODE = VREF, VDLP= 3V, CTL = high 250 A

DRN Input Current VMODE = VREF, VDRN= 8V, VDLP= 3V, VCTL= 0V 40 A

SRC Switch On-Resistance VMODE=VREF, VDLP= 3V, CTL = high 40

Mode 2 MODE Capacitor Charge

CurrentVMODE < MODE current-source stop voltage threshold 42 64 A

MODE Voltage Threshold for

Enabling DRN Switch Control in

Mode 2

2.3 2.7 V

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MAX8

710/MAX8711/MAX87



MAX8761LINEAR-REGULATOR LOAD REGULATION

OUTPUT-VOLTAGEERROR(%)

MAX8710/11/12/61toc04

0 100 200 300 400 500-2.0

-1.6

-1.2

-0.8

-0.4

0

0.4

LOAD CURRENT (mA)

VOUTL= 10V

VINL= 12V

MAX8710/MAX8711/MAX8712 LINEAR-REGULATOR LOAD TRANSIENT RESPONSE

MAX8710/11/12/61 toc05

20s/div

A

10V

B

0mA

A: VOUTL, 50mV/div, AC-COUPLEDB: IOUTL, 200mA/div

MAX8761 LINEAR-REGULATOR LOADTRANSIENT RESPONSE

MAX8710/11/12/61 toc06

40s

A

B

A: IOUTL, 200mA/divB: VOUTL, AC-COUPLED, 20mV/div

MAX8710/MAX8711/MAX8712 LINEAR-REGULATOR PULSED LOAD-TRANSIENT

RESPONSEMAX8710/11/12/61 toc07

A

10V

MAX8761 LINEAR-REGULATORPULSED LOAD TRANSIENT RESPONSE

MAX8710/11/12/61 toc08

A

MAX8710/MAX8711/MAX8712 LINEAR-

REGULATOR OVERCURRENT PROTECTIONMAX8710/11/12/61 toc09

A

Typical Operating Characteristics (continued)(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0C to +85C. Typical values are at TA =

+25C, unless otherwise noted.)

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MAX8711/MA

X8712/MA

X8761





POSITIVE CHARGE-PUMPLINE REGULATION

MAX8710/11/12/61toc13

INPUT VOLTAGE (V)


131211

-0.8

-0.6

-0.4

-0.2

0

0.2

-1.010 14

20mA LOAD CURRENT

NEGATIVE CHARGE-PUMP LOADREGULATION

MAX8710/11/12toc14

LOAD CURRENT (mA)


60 8020 40

-1.00

-0.75

-0.50

-0.25

0.25

0

-1.250 100

VGOFF= -5VINPUT = 12V

NEGATIVE CHARGE-PUMP LINEREGULATION

MAX8710/11/12/61toc15

INPUT VOLTAGE (V)


1312111098

-0.8

-0.6

-0.4

-0.2

0

0.2

-1.07 14

VGOFF= -5VIGOFF= 50mA

POWER-UP SEQUENCEMAX8710/11/12/61 toc16

A

0V

0V

B

MAX8710/MAX8761 SWITCH CONTROLFUNCTION (MODE 1)

MAX8710/11/12/61 toc17

A

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MAX8

710/MAX8711/MAX87



MAX8710/MAX8711/MAX8761 SUPB SUPPLYCURRENT vs. SUPB VOLTAGE

MAX8710/11/12/61toc

21

SUPB VOLTAGE (V)

SUPBSUPPLYCURRENT(mA)

121086

0.2

0.4

0.6

0.8

1.0

04 14

BUFFER CONFIGURATION

VOUTB= 0.5 x VPOSB

MAX8710/MAX8711/MAX8761 OPERATIONAL-AMPLIFIER SMALL-SIGNAL STEP RESPONSE

(BUFFER CONFIGURATION)MAX8710/11/12/61 toc22

400ns/div

A

B

0V

0V

A: VPOSB, 50mV/div, AC-COUPLEDB: VOUTB, 50mV/div, AC-COUPLED

MAX8710/MAX8711/MAX8761 OPERATIONAL-

AMPLIFIER LARGE-SIGNAL STEPRESPONSE (BUFFER CONFIGURATION)

MAX8710/11/12/61 toc23

MAX8710/MAX8711/MAX8761 OPERATIONAL-AMPLIFIER LOAD TRANSIENT

RESPONSE (BUFFER CONFIGURATION)MAX8710/11/12/61 toc24

MAX8710/MAX8711/MAX8761 OPERATIONAL-

AMPLIFIER RAIL-TO-RAIL I/OMAX8710/11/12/61 toc25



REFERENCE vs. TEMPERATURE

MAX8710/11/12/91toc

20

TEMPERATURE (C)

REFVOLTAGEERROR(%)

806040200-20

-0.4

-0.2

0

0.2

-0.6-40 100

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MAX8711/MAX8712/MA

X8761



PIN

MAX8710/

MAX8761 MAX8711 MAX8712

NAME FUNCTION

1 GON

Internal High-Voltage MOSFET Switch Common Terminal. GON is the output of the

high-voltage switch-control block. GON is internally pulled to GND by a 1kresistor inshutdown for the MAX8710. GON is not pulled to GND for the MAX8761.

2 DRNSwitch Input. Drain of the internal high-voltage back-to-back p-channel

MOSFETs connected to GON.

3 1 1 REFReference Output. Connect a 0.22F capacitor from REF to GND. REF remains

on in shutdown.

4 2 POSB Operational-Amplifier Noninverting Input

5 3 2 INL Linear-Regulator Supply Input

6 4 NEGB Operational-Amplifier Inverting Input

7 5 3 IN IC Supply Input. Bypass IN to GND with a 0.1F capacitor.

8 6 4 OUTL

Linear-Regulator Output. OUTL is internally pulled to GND by a 1kresistor inshutdown. For the MAX8711/MAX8712, OUTL is also the supply input for the

charge-pump regulators.

9 SUPCPSupply Input for the Charge-Pump Regulators. Connect a 0.1F capacitor from

SUPCP to GND.

10 7 5 DRVN

Negative Charge-Pump Driver Output. Output high level is VSUPCP, and output

l l l i GND DRVN i i t ll ll d hi h t SUPCP h th ti

Pin Description

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MAX8

710/MAX8711/MAX87



PIN

MAX8710/

MAX8761 MAX8711 MAX8712

NAME FUNCTION

18 13 9 SHDN

Active-Low Shutdown Control Input. Pull SHDNlow to turn off all sections of the

device except REF. Pull SHDNhigh to enable the device. Cycle SHDNto resetthe device after a fault.

19 CTLHigh-Voltage Switch-Control Block Timing Control Input. See the Switch Control

(MAX8710/MAX8761)section for details.

20 14 10 FBL

Linear-Regulator Feedback Input. Connect FBL to the center of a resistive

voltage-divider between the linear-regulator output and GND to set the linear-

regulator output voltage. Place the divider within 5mm of FBL.

21 MODE

High-Voltage Switch-Control Block-Mode Selection Input and Timing-Adjustment

Input. See the Switch Control (MAX8710/MAX8761)section for details. MODE ishigh impedance when it is connected to REF. MODE is internally pulled to GND

by a 1kresistor during REF UVLO, when VDLP< 2.5V, or in shutdown.

22 15 11 DLP

Positive Charge-Pump Startup Delay and High-Voltage Switch Delay Input.

Connect a capacitor from DLP to GND to set the delay time. A 5A current

source charges CDLP. DLP is internally pulled to GND by a 10resistor inshutdown.

23 16 12 FBN

Negative Charge-Pump Feedback Input. Connect FBN to the center of a

resistive voltage-divider between the negative output and REF to set the output

l Pl h di id i hi 5 f FBN FBN i i ll ll d GND

Pin Description (continued)

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MAX8711/MAX8712/MA

X8761



POSB

AVDD

OUTB

120k

MMBD4148SE(FAIRCHILD)



0.22F

1F

R5

100k

OUTB

DRVN

NEGB

OUTL

AVDD10V

300mA/500mA(MAX8710/MAX8761)

VP

IN

GND

GND IN10.8V TO 13.2V

IN

0.1F 10F

4.7F/10F(MAX8710/MAX8761)

0.1F

0.1F

0.1F

0.1F

0.1F

0.1F

C147pF/22pF

(MAX8710/MAX8761)

R233.2k

1%

R1100k

1%

GOFF

5V/50 A

SUPB

MAX8710

MAX8761

N.C. INL

DRVP

SUPCP

FBL

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MAX8

710/MAX8711/MAX87



POSB

AVDD

OUTB

120k


MMBD4148

0.22F

100k

OUTB

NEGB

OUTL

AVDD10V/300mA

GND


IN

0.1

F 10F

4.7F

0.1F

0.1F

0.1F

C147pF

R233.2k

1%

R1100k

1%

SUPB

MAX8711

INL

DRVP

FBL

1F

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AX8711/MAX8712/MA

X8761




MMBD4148

2x MMBD4148SE(FAIRCHILD)

0.22F

0.47F

1FR5

110k1%

R6100k

1%

DRVN

FBN

OUTL

AVDD10V/300mA

GON27V/20mA

GND


IN

0.1F 10F

4.7F

1F

0.1F

0.1F

0.1F

C147pF

R233.2k

1%

R1100k

1%

GOFF-5V/50mA

REF5V/1mA

MAX8712

INL

REF

DLP

DRVP

FBL

1F

0.1F

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MAX8710/MAX8711/MAX87



FBN

DRVN

DLP

POSB

SUPB

REF

VGOFF

AVDD

AVDD

VINSUPCP

AVDD

VP

IN

GND

IN

REFREF

MAX8710

MAX8761

SHDN

DRVP

FBP

SEQ

OSC

INL

OUTL

FBL

LINEARREG

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AX8711/MAX8712/MA

X8761


LCD Panel Power SuppliesThe linear regulator is enabled whenever REF is in regula-tion and SHDN is logic high. Each time it is enabled, thelinear regulator goes through a soft-start routine by ramp-ing up its internal reference voltage from 0 to 2.5V in 128steps. The soft-start period is 2.73ms (typ), and FBL faultdetection is disabled during this period. This soft-startfeature effectively limits the inrush current during startup.

The linear-regulator current-limit circuitry monitors thecurrent flowing through the internal pass transistor. Theinternal current limit is approximately 800mA (1.1A forthe MAX8761). The linear-regulator output declines whenit is not able to supply the load current. If the FBL voltagedrops below 0.75V, the current limit folds back toapproximately 180mA (250mA for the MAX8761).

The MAX8710/MAX8711/MAX8712/MAX8761 monitor theFBL voltage for undervoltage conditions. If VFBL is contin-uously below 2V (typ) for approximately 44ms, the devicelatches off. The foldback current-limit circuit, in conjunc-tion with the output undervoltage fault latch and thermal-overload protection, protects the output load and theinternal pass transistor against short circuits or overloads.

Positive Charge-Pump RegulatorThe positive charge-pump regulator is typically used togenerate the positive supply rail for the TFT LCD gate-dri-

ver ICs. The output voltage is set with an external resistivevoltage-divider from its output to GND with the midpointconnected to FBP. The number of charge-pump stagesand the setting of the feedback divider determine the out-put voltage of the positive charge-pump regulator. Thecharge-pump driver includes a high-side p-channelMOSFET (P1) and a low-side n-channel MOSFET (N1) to

control the power transfer as shown in Figure 5. TheMOSFETs switch at a constant frequency of 1.5MHz.

During the first half-cycle, N1 turns on and allows VINPUT(VSUPCP, MAX8710/MAX8761 or VOUTL, MAX8711/MAX8712) to charge up the flying capacitor CX(POS)through diode D1. The amount of charge transferredfrom VINPUT to CX(POS) is determined by the on-resis-tance of N1, which varies according to the output of thefeedback error amplifier. The error amplifier comparesthe feedback signal (FBP) with a 2.5V internal reference

and amplifies the difference. If the feedback signal isbelow the reference, the error-amplifier output increasesthe supply voltage of N1s gate driver, lowering the on-resistance. Similarly, if the feedback signal is above thereference, the error-amplifier output reduces the driversupply voltage, increasing the on-resistance. During thesecond half-cycle, N1 turns off and P1 turns on, levelshifting CX(POS) by VINPUT volts. This connects CX(POS)

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LCD Panel Power Suppliesin parallel with the reservoir capacitor COUT(POS). If thevoltage across COUT(POS) plus a diode drop (VPOS +VDIODE) is smaller than the level-shifted flying-capacitorvoltage (VCX(POS) + VINPUT), charge flows from CX(POS)to COUT(POS) until diode D2 turns off.

The positive charge-pump regulators startup can bedelayed by connecting an external capacitor from DLP

to GND. An internal constant current source beginscharging the DLP capacitor when SHDN is logic highand REF reaches regulation. When the DLP voltageexceeds VREF/ 2, the positive charge-pump regulatoris enabled. Each time it is enabled, the positive charge-pump regulator goes through a soft-start routine byramping up its internal reference voltage from 0 to 2.5Vin 128 steps. The soft-start period is 2.73ms (typ), andFBP fault detection is disabled during this period. Thesoft-start feature effectively limits the inrush current dur-

ing startup. The MAX8710/MAX8711/MAX8712/MAX8761 also monitor the FBP voltage for undervolt-age conditions. If VFBP is continuously below 2V (typ)for approximately 44ms, the device latches off.

Negative Charge-Pump RegulatorThe negative charge-pump regulator is typically used togenerate the negative supply rail for the TFT LCD gate-driver ICs. The output voltage is set with an external resis-tive voltage-divider from its output to REF with the mid-

the error-amplifier output reduces the driver supplyvoltage, increasing the on-resistance.

The negative charge-pump regulator is enabled whenSHDN is logic high and REF reaches regulation. Eachtime it is enabled, the negative charge-pump regulatorgoes through a soft-start routine by ramping down itsinternal reference voltage from 5V to 250mV in 128

steps. The soft-start period is 2.73ms (typ), and FBNfault detection is disabled during this period. The soft-start feature effectively limits the inrush current duringstartup. The MAX8710/MAX8711/MAX8712/MAX8761also monitor the FBN voltage for undervoltage condi-tions. If VFBN is continuously above 700mV (typ) forapproximately 44ms, the device latches off.

Operational Amplifier(MAX8710/MAX8711/MAX8761)

The MAX8710/MAX8711/MAX8761s operational ampli-fier features high output current (150mA), fast slew rate(7.5V/s), and wide bandwidth (12MHz). The opera-tional amplifier is enabled when REF is in regulationand SHDN is logic high. The output of the amplifier(OUTB) is internally pulled to ground through a 1kresistor in shutdown.

The amplifier is typically used to drive the backplane(VCOM) of TFT LCD panels. The LCD backplaneconsists of a distributed series capacitance and resis-

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AX8711/MAX8712/MA

X8761


LCD Panel Power SuppliesPower-Up Sequence and Shutdown ControlWhen the MAX8710/MAX8711/MAX8712/MAX8761 arepowered up, REF rises with the voltage on IN. After REFreaches regulation and if SHDN is logic high, the linearregulator, operational amplifier, and negative charge-pump regulator are enabled and begin their respectivesoft-start routines. After the soft-start routines are com-

pleted, the fault-protection circuits for the linear regulatorand the negative charge-pump regulator are activated.

When the linear regulator is enabled, the positivecharge-pump-regulator delay block is enabled. Aninternal current source starts charging the DLP capaci-tor. The voltage on DLP linearly rises because of theconstant charging current. When VDLP goes aboveVREF/ 2, the switch control block is enabled, and thepositive charge-pump regulator begins its soft-start.After the positive charge-pump regulators soft-start is

completed, the fault protection of the positive charge-pump regulator is also enabled.

The MAX8710/MAX8711/MAX8712/MAX8761 enter intoshutdown when SHDN is pulled low or REF falls below4.5V. In shutdown, OUTL and OUTB are internallypulled to ground with 1k resistors, FBN and FBP areinternally pulled to ground with 10 resistors, and DLPis pulled to GND through a 10 resistor, dischargingCDLP . In the MAX8710 only, GON is pulled to GNDthrough a 1k resistor. REF remains on in shutdown.

Thermal-Overload ProtectionThe thermal-overload protection prevents excessivepower dissipation from overheating the IC. When thejunction temperature exceeds +160C, a thermal sensorimmediately activates the fault protection, which shutsdown all the outputs except the reference, allowing thedevice to cool down. Once the device cools down by

approximately 15C, the IC restarts automatically.Switch Control (MAX8710/MAX8761)

The MAX8710/MAX8761s' switch-control block (Figures6 and 7) consists of a high-voltage p-channel MOSFETQ1 between SRC and GON, and a common-source-con-nected p-channel MOSFET pair Q2 between GON andDRN. The MAX8710 switch control block is enabledwhen VDLP goes above VREF/ 2 and for MAX8761 VDLPhas no control on switch control block. Both theMAX8710 and MAX8761 have two different modes ofoperation.

Activate the first mode by connecting MODE to REF.When CTL is logic high, Q1 turns on and Q2 turns off,connecting GON to SRC. When CTL is logic low, Q1turns off and Q2 turns on, connecting GON to DRN.GON can then be discharged through a resistor con-nected between DRN and GND or OUTL. Q2 turns offand stops discharging GON when VGON reaches 10times the voltage on THR.

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REF

1k9R

RQ3

Q2

SRC

GON

DRN

THR

Q1

5A

50AREF

R

Q4

0.5 x VREF

DLP

FAULTSHDNREF OK

MAX8710

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AX8711/MAX8712/MA

X8761



9R

RQ2

SRC

GON

DRN

THR

Q1

50AREF

R

4R

5R1k

MODE

FAULT

REF OK

MAX8761

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LCD Panel Power SuppliesDesign Procedure

Linear Regulator

Output-Voltage SelectionAdjust the linear-regulator output voltage by connectinga resistive voltage-divider from the linear-regulator out-put AVDD to GND with the center tap connected to FBL

(Figure 1). Select the lower resistor of divider R2 in the10k to 50k range. Calculate upper resistor R1 withthe following equation:

where VFBL = 2.5V (typ) is the regulation point of thelinear regulator.

Input-Capacitor SelectionThe linear regulators output stage consists of a pnp passtransistor. Rapid movements of the input voltage must beavoided since the movement can be coupled into thebase of the transistor through the base-to-emitter junctioncapacitance. The input capacitor reduces the currentpeaks drawn from the input supply and slows down theinput voltage movement. One 10F ceramic capacitor isused in the Typical Operating Circuits(Figures 1, 2, and3) because of the high source impedance seen in typical

where IPULSE is the height of the pulse load, and tPULSEis the pulse width. Higher capacitance and lower ESRresult in less voltage dip. The ESR dip can be ignoredwhen using ceramic output capacitors. Calculate theminimum required capacitance for the maximum alloweddip using:

The above equations are worst case and assume thatthe linear regulator does not react to correct the outputvoltage during the load pulse. In fact, the regulator isfast enough to partially correct the output voltage, sothe actual dip may be smaller, or a smaller capacitormay be acceptable. For the typical load pulsedescribed above, assuming the voltage dip must belimited to 150mV, the minimum output capacitor is:

A s 1 1

CI t

VOUT MIN

PULSE PULSE

DIP MAX( )

( )

V V V

V I R

VI t

C

DIP DIP ESR DIP C

DIP ESR PULSE ESR

DIP CPULSE PULSE

OUT

( ) ( )

( )

( )

= +

=

R RV

VAVDD

FBL1 2 1=

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AX8711/MAX8712/MAX8761



where R1 is the upper resistor of the feedback dividerand fu is the unity gain frequency. The unity gain fre-quency (fu) for the MAX8710/MAX8711/MAX8712 is

approximately 80kHz; for MAX8761, fu is approximately160kHz. The value of R1 was calculated in the Output-Voltage Selection section to set VOUTL. Use the valuefor unity gain frequency (fu), the ratio between VOUTLand VFBL, and R1 to calculate the value of C1.

Charge-Pump Regulators

Number of Charge-Pump StagesFor highest efficiency, always choose the lowest num-ber of charge-pump stages that meets the output

requirement.The number of positive charge-pump stages is given by:

where nPOS is the number of positive charge-pumpstages, VP is the positive charge-pump regulator output,VINPUT is the supply voltage for the charge-pump regula-tors (V , MAX8710/MAX8761 or V , MAX8711/

Output-Voltage SelectionAdjust the positive charge-pump-regulator output volt-age by connecting a resistive voltage-divider from theregulator output VP to GND with the center tap connect-ed to FBP (Figure 1). Select the lower resistor of dividerR4 in the range of 10k to 50k. Calculate upper resistorR3 with the following equation:

where VFBP = 2.5V (typ) is the regulation point of thepositive charge-pump regulator.

Adjust the negative charge-pump-regulator output volt-age by connecting a resistive voltage-divider from thenegative charge-pump output VGOFF to REF with thecenter tap connected to FBN (Figure 1). Select R6 inthe 20k to 100k range. Calculate R5 with the follow-ing equation:

where VREF = 5V and VFBN = 250mV is the regulationpoint of the negative charge-pump regulator.

Flying Capacitor

R RV V

V VFBN GOFF

REF FBN5 6=

R RV

VP

FBP3 4 1=

nV V V

V VPOS

P SWITCH SUPCP

INPUT DIODE

= +

2

= =

ZEROU

OUTL FBLR C V V

1

2 1 1 /

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MAX8710/MAX87

11/MAX87


LCD Panel Power SuppliesCharge-Pump Output Capacitor

Increasing the output capacitance or decreasing theESR reduces the output ripple voltage and the peak-to-peak transient voltage. With ceramic capacitors, theoutput voltage ripple is dominated by the capacitancevalue. Use the following equation to approximate therequired capacitor value:

where COUT_CP is the output capacitor of the chargepump, ILOAD_CP is the load current of the chargepump, and VRIPPLE_CP is the desired peak-to-peakvalue of the output ripple.

Charge-Pump Rectifier Diode

Use low-cost silicon switching diodes with a current rat-ing equal to or greater than two times the averagecharge-pump input current. If it helps avoid an extrastage, some or all of the diodes can be replaced withSchottky diodes with an equivalent current rating.

Applications Information

External Transistor for Higher Currentor Power Dissipation

The load current and the voltage difference between

CI

f VOUT CP

LOAD CP

OSC RIPPLE CP_

_

_

2

MAX8710

MAX8711

MAX8712

MAX8761

LINEARREGULATOR

4.7F

4.7F

INL

OUTL

FBL

VIN= 19V

KSB834W(FAIRCHILD)

AVDD = 10V

51

140k

20k

Figure 8. High-Power Linear Regulator

MAX8710

MAX8711

MAX8761

REF

VDDOUTL

0.47F

4.7FMAX1512

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AX8711/MAX8712/MAX8761


LCD Panel Power SuppliesPC Board Layout Guidelines

Careful PC board layout is important for proper opera-tion. Use the following guidelines for good PC boardlayout:

1) Create a power ground island consisting of the lin-ear-regulator input and output-capacitor groundconnections, the GND pin, and the capacitorground connections for the charge-pump regula-tors. Connect all these together with short, widetraces or a small ground plane. Maximizing thewidth of the power ground traces improves efficien-cy. Create an analog ground island consisting of allthe feedback-divider ground connections, the oper-ational-amplifier divider ground connection, the REFcapacitor ground connection, the MODE capacitorground connection, the DLP capacitor ground con-nection, and the devices exposed backside pad.Connect the analog ground island and the powerground island by connecting the GND pin directly tothe exposed backside pad. Make no other connec-tions between these separate ground islands.

2) Place all feedback voltage-divider resistors as closeto their respective feedback pins as possible. Thedividers center trace should be kept short. Placingthe resistors far away causes their FB traces tobecome antennas that can pick up noise from the

Pin Configurations (continued)

16

1 2 3 4

12 11 10 9

15

14

13

5

6

7

8

FBN

DRVPFBL

DLP

FBL

SHDN

FBP

SUPB

OUTB

GND

POSB

INL

NEGB

IN

OUTL

DRVN

DRVP

REF

TOP VIEW

THIN QFN 4mm x 4mm

10

+

6

9 8 7

FBP

SHDN

GND

MAX8711

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MAX8710/MAX87

11/MAX87


LCD Panel Power SuppliesPackage Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

24LQ

FNT

HIN.EPS

PACKAGE OUTLINE,

21-0139 21

E

12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm

ENGLISH ???? ??? ???

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WH AT' S NEW PRODUCTS SOLUTIONS DESIGN A PPNOTES SUPPORT BU Y COMPA NY MEMBERS

M A X 8 7 1 1

P ar t N um be r T ab le

N o t e s :

S e e t h e M A X 8 7 1 1 Q u i c k V i e w D a t a S h e e t f o r f u r t h e r i n f o r m a t i o n o n t h i s p r o d u c t f a m i l y o r d o w n l o a d t h eM A X 8 7 1 1 f u l l d a t a s h e e t ( P D F , 6 2 4 k B ) .

1.

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D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l yw i t h i n o n e b u s i n e s s d a y .

3.

P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e :S e e f u l l d a t a s h e e t or P a r t N a m i n g C o n v e n t i o n s .

4.

* S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e

p r o d u c t u s e s .

5.

P a r t Nu m b e r F re e

S a m p l e

Buy

D i r e c t

P a c k a g e : T Y P E P I N S S I Z E

DRA WI NG CODE /VA R *

T e m p R o H S / L e a d - F r e e ?

M a t e r i a l s A n a l y s i s

M A X 8 7 1 1 E T E T H I N Q F N ; 1 6 p i n ; 4 X 4 X 0 . 8 m m

D w g : 2 1 - 0 1 3 9 E ( P D F )U s e p k g c o d e / v a r i a t i o n : T 1 6 4 4 - 4 *

- 4 0C t o + 8 5C R o H S/ L ea d -F r e e: No

M a t e r i a l s A n a l y s i s

M A X 8 7 1 1 E T E - T T H I N Q F N ; 1 6 p i n ; 4 X 4 X 0 . 8 m mD w g : 2 1 - 0 1 3 9 E ( P D F )

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D i d n ' t F i n d W h a t Y o u N e e d ?

C O N T A C T U S : S E N D U S A N E M A I L

C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s Se m i c o n d u c t o r L e g a l N o t i c e s P r i v a c y P o l i c y

dsa 00427225

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