dsd 12 synchronous design

7/27/2019 DSD 12 Synchronous Design

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Impediments to SynchronousDesign

Impediments to Synchronous Design

Clock skew

Asynchronous inputs

2EC6101 Digital System Design - Monsoon 2012

Clock Skew

Clock signal may not reach all flip-flops

simultaneously.

Output changes of flipflops receiving

early clock may reach D inputs of flip-

flops with late clock too soon.

Reasons for slowness:

(a) wiring delays

(b) capacitance

(c) incorrect design3

EC6101 Digital System Design - Monsoon 2012

Clock Skew - Example

4

Difference between arrival

times of the clock at different

devices is called clock skew

For proper operation,


Detailed Timing Diagram

5EC6101 Digital System Design - Monsoon 2012 EC6101 Digital System Design - Monsoon 2012

6

tclk-tffpd-tcomb>tsetup

Timing Margins indicate how much worse than worst-case

the individual components of a circuit can be without causing a

circuit to fail

For proper circuit operation,

tclk-tffpd(max)-tcomb(max)-tsetup

Setup time margin is given by,

Hold time margin is given by,

tffpd(min)+tcomb(min)-thold


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Bufferingtheclock


Excessive clock skew Controllable clock skew

ExcessiveskewinPCBorASIC


A clock signal path leading to excessive skew in PCB or ASIC

ExcessiveskewinPCBor

ASIC


Clock signal routing to minimize skew

Gatingtheclock


Gatingtheclock


1. If CLKEN is a state-machine output or other signal produced by a

register clocked by CLOCK, then CLKEN changes some time afterCLOCK has already gone HIGH. As shown in (b) this produces

glitches on GCLK, and false clocking of the registers controlled by

GCLK.

2. Even if CLKEN is somehow produced well in advance ofCLOCKs

rising edge (e.g., using a register clocked with the falling edge of

CLOCK, an especially nasty kludge), the AND-gate delay gives

GCLK excessive clock skew, which causes more problems all around.

Acceptablewaytogatethe

clock



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Asynchronous Inputs

AsynchronousInputsto

SynchronousSystems

Many synchronous systems need to

interface to asynchronous input signals:Consider a computer system running at some

clock frequency, say 1GHz with:

Interrupts from I/O devices, keystrokes, etc.

Data transfers from devices with their own clocks

Ethernet has its own 100MHz clock

PCI bus transfers, 66MHz standard clock.

These signals could have no known timing

relationship with the system clock of the CPU.EC6101 Digital System Design - Monsoon 2012

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Synchronizer Circuit

For a single asynchronous input, we use a simple flip-flop

to bring the external input signal into the timing domain of

the system clock:


Synchronizer Circuit

The D flip-flop samples the asynchronous input at

each cycle and produces a synchronous output that

meets the setup time of the next stage.

It is essential for asynchronous inputs to be

synchronized at only one place.


Only ONE synchronizer per input


Two flip-flops may not receive the clock and input signals at precisely

the same time (clockand data skew).

When the asynchronous input changes near the clock edge, one flip-flop

may sample input as 1 and the other as 0.

Even worse


Combinational delays to the two synchronizers are likely to be different


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The way to do it


One synchronizer per input

Carefully locate the synchronization points in a system.

But still a problem -- the synchronizer output may become

metastable when setup and hold time are not met.

MetastabilityResolutionTime

It denotes the maximum time that the output

can remain metastable without causingsynchronizer (and system) failure.


tr= tclk-tcomb-tsetup

Recommendedsynchronizer

design

Hope that FF1 settles down before META issampled.

In this case, SYNCIN is valid for almost a full

clock period. Can calculate the probability of synchronizer failure

(FF1 still metastable when META sampled)EC6101 Digital System Design - Monsoon 2012

21

As long as the clock period is greater than t r

plus the FF2s setup time, SYNCIN

becomes a synchronized copy of the

asynchronous input on the next clock tick.


SynchronizerFailure

Synchronizer failure is said to occur if a system

uses a synchronizer output while the output is still

in the metastable state.

The way to avoid synchronizer failure is to ensure

that the system waits longenough before using a

synchronizers output.


SynchronizerFailure

There are two ways to get a flip-flop out of

the metastable state:

1.Force the flip-flop into a valid logic state using

input signals that meet the published specifications

for minimum pulse width, setup time, and so on.

2.Wait longenough, so the flip-flop comes out of

metastability on its own.



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Metastable


When FF input changes close to clock edge, the FF may enter the metastablestate: neither a logic 0 nor a logic 1

It may stay in this state an indefinate amount of time, although this is not likely

in real circuits

Small, but non-zero probabilitythat the FF output will get stuck

in an in-between state

Logic 0 Logic 1

SolutionstoSynchronizer

Failure


the probability of failure can never be reduced to 0, but it can be reduced

slow down the system clockthis gives the synchronizer more time to decay into a steady state

synchronizer failure becomes a big problem for very high speed systems

use fastest possible logic in the synchronizerthis makes for a very sharp "peak" upon which to balanceS or AS TTL D-FFs are recommended

cascade two synchronizers

Clk

AsynchronousInput

SynchronizedInput

Synchronous System

D QD Q

Decisionwindow

Interval in which the flip-flop samples its

input and decides to change its output if

necessary.


NormalFFAs long as the D input changes outside the decision window

the manufacturer guarantees that the output will change and

settle to a valid logic state before time tpd.


Metastablebehaviour

If D changes inside the decision window metastability may

occur and persist until time tr


MetastabilityandMTBF


A synchronizer design is characterised by

its Mean Time Between Failure (MTBF)

A failure is declared when the first sync. FF goes

metastable and the output is not resolved before

the 2nd. FF is clocked

Depends on FF setup/hold and prop. times, clock

rate and average rate of input change

Different flip-flops can have greatly different

MTBFs

Even a small change of the clock can be

significant


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MetastabilityMTBF


The MTBF equation is:

Where:

tr= resolution time (clock period - FF setup time)

T0, = flip-flop characteristic constants

f = clock frequency

a = average input rate of change

afT

e)MTBF(t

0

t

r

r

MetastabilityMTBF


For example using a 74LS74 FF (T0 = 0.4,

= 1.5) at a clock rate of 10 MHz and in inputav. rate of change = 100 KHz

tr= 80 ns (100 ns clock period - 20 ns tsu)

MTBF = 3.6 1011 sec.

If we just change the clock to 16 MHz,

things get really strange

tr= 42.5 ns (62.5 ns clock period - 20 ns tsu)

MTBF = 3.1 sec.!

MetastabilityMTBF


We can improve the performance if we

change to a 74ALS74 FF (T0 = 8.7 10-6,

= 1.0)

tr= 52.5 ns (62.5 ns clock period - 10 ns tsu)

MTBF = 4.54 1015 sec.

Reliablesynchronizers

Reliable synchronizers can be build in two

ways

Use faster flip flops.

Increase the value of trin MTBF equation.


Multiple-cyclesynchronizer


Multiple-cyclesynchronizer

Best value that can obtained for tris t

clkif

tsetup is zero.

In Multiple-cycle synchronizer trcan be in

the order of n.tclk

tr=n.tclk-tsetup



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De-skewedmultiple-cycle

synchronizer


Timing Hazards

Timing Hazards

Transient output behavior may not agree

with predicted output due to delay

differences.

A glitch is the presence of extra signal

transitions which are not predicted from the

logic equations.


Static Hazards

A stati c hazardis the possibilityof a glitch

when the output should not change

Static-1

Static-0


Static-1Hazard

A static-1 hazard is a pair of input

combinations that: (a) differ in only one

input variable and (b) both give a 1 output;

such that it is possible for a momentary 0

output to occur during a transition in the

differing input variable.


Static-1Hazard



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Static-0Hazard

A static-0 hazard is a pair of input

combinations that: (a) differ in only oneinput variable and (b) both give a 0 output;

such that it is possible for a momentary 1

output to occur during a transition in the

differing input variable.


Static-0Hazard


Eliminatestatichazardsusing

maps


Static-1hazardeliminated


AnotherExample


DynamicHazards

A dynamic hazard is the possibility of an

output changing more than once as the

result of a single input transition.

Multiple output transitions can occur if

there are multiple paths with different

delays from the changing input to the

changing output.



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DynamicHazards


Reference

Digital Design Principles and Practices , John F. Wakerly, 3 rd Edition

PHI.


dsd 12 synchronous design

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