dsp algorithm on system on chip performed by : einat tevel supervisor : isaschar walter accompanying...
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DSP Algorithm on
System on ChipPerformed by : Performed by :
Einat TevelEinat TevelSupervisor : Supervisor :
Isaschar WalterIsaschar WalterAccompanying engineers : Accompanying engineers :
Emilia Burlak, Golan InbarEmilia Burlak, Golan InbarTechnion - Israel institute of technologydepartment of Electrical Engineering
High speed digital systems laboratory
winter 2003/2004winter 2003/2004With cooperation with RAFAEL
AbstractAbstract
In recent years the world is In recent years the world is progressing towards much more progressing towards much more sophisticated digital systems, which sophisticated digital systems, which integrate both hardware and software. integrate both hardware and software.
These devices are known as "System These devices are known as "System on a Chip" (SoC). on a Chip" (SoC).
This project explores SoCs, in search This project explores SoCs, in search of the best implementation of a given of the best implementation of a given DSP algorithm using a SoC.DSP algorithm using a SoC.
System DescriptionSystem Description
PowerPC 405 Core
I-Cache
D-Cache
CoreConnect Processor Local Bus (PLB)
CIC Filters
External Memory
High Speed Peripherals
CoreConnect On-Chip Peripheral Bus (OPB)
Low Speed
Peripherals
PLB-OPB Bridge
FPGA Block RAM
FPGA Block RAM
Data FlowData Flow
Power PC
Data Processing Core
Input Data
Output Data
1 2
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1. The data is sent to the Power PC Processor.
2. After parsing the data, The Power PC configures the Data Processing Core and the raw data is sent.
3. The processed data is sent back to the Power PC Processor.
4. The output is ready.
Hardware/Software FlowHardware/Software Flow
HW BlockDiagram
HW Description
Synthesize P&R
BIT File/Download
HW Flow
SW Flow Chart
Create SWSource
Compile Simulate
ELF File/Download
SW Flow
ISE
Design Debug (HW and SW)
DATA2BRAM
EDK
SpecificationSpecification
Hardware:Hardware:• Virtex-II Pro FF1152 Development BoardVirtex-II Pro FF1152 Development Board
Enables implementation of embedded Enables implementation of embedded processor based applications usingprocessor based applications using IP cores IP cores and customized modules. Includes two and customized modules. Includes two integrated PowerPC processors, memory integrated PowerPC processors, memory blocks of 8Mx32 SDRAM memory.blocks of 8Mx32 SDRAM memory.
• Development and simulation tools: Development and simulation tools: • EDK – Embedded Development Kit, CoreGen.EDK – Embedded Development Kit, CoreGen.• ISE, ModelSim. ISE, ModelSim.
Software:Software:• MATLAB, Hyper Terminal.MATLAB, Hyper Terminal.
CIC Filters StructureCIC Filters Structure Cascade of Integrators.Cascade of Integrators. Resampling Switch (decimate/expansion).Resampling Switch (decimate/expansion). Cascade of Differentiators. Cascade of Differentiators. Parameters: Number of Stages (N), Rate Parameters: Number of Stages (N), Rate
Change Factor (R), Differential Delay (M).Change Factor (R), Differential Delay (M).
GUI ScreenshotGUI Screenshot