dsp control loop design

8/10/2019 DSP Control Loop Design

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DSP based Digital Control Design

for DC-DC Switch ModePower Converter

Shamim Choudhury

Texas Instruments Inc.


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DC/DC Buck Converter

Vin = 4V ~ 6V, Vo = 1.6V, Io = 16A

L = 1uH, C = 1620uF, ESR = 0.004 ohm

PWM Freq = 250kHz,

Digital Control Loop Sampling Freq, fs = 250kHz,

Voltage Control Loop Bandwidth = 20kHz,

Phase Margin = 45 deg

Settling Time < 75uSec

C RLVin

VoIin

L

Io

Digital Control of DC/DC Converter


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Sample to PWM Update Delay Td = 0.5Ts(Computation Delay)

Sampling Scheme 1

Code

execution

Sampling period (Ts)

N N+1

Context

saveContext

restoreExecute

Controller

Back-groundspare

Int Int

ISR

PWM/

t

PW

M periodn n+1

Update

PWM

ADC conv time

ADC

Sampling Scheme 2

Sample to PWM Update Delay Td = 2.0Ts(Computation Delay)

PWM/ADC

Code

execution

Sampling period (Ts)

ADC conv time

NN+1

tContext

saveContext

restoreExecute

Controller

Back-groundspare

Int Int

ISR

PWM periodn n+1

Update

PWM

Update

PWM

Update

PWM


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CRL

=

d

Vo(s)PG

d

Vo(n)

U(n)Gc(z)

PWMA/D

VrefTMS320F2810

+

E(n)

Vin

VoIin

LVos

Kd

Digital Control of DC/DC ConverterControl Design by Emulation

31)(,1

7

)()(

max

max

maxmax

QinnVforV

KKVFFFFFFh

KVnVKVnV

o

o

ddo

doodoo

==

==

=> Kd=0.5

Vo(n)

0

2V

00000000

7FFFFFFF

Vo

Output Voltage Sensing Gain


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1.62x10-5 s + 2.5

Gp1(s) = ---------------------------------------

1.685x10-9 s2 + 1.648x10-5 s + 1

Vin=5.0, RL=0.1, Kd=0.5,

L=1uH, C=1620uF,

Rc=0.004 ohm,

d

U(n)

Vo

Kd

Gc(z)

Vref

+

Vo(n)

E(n)

Gp(s)

Gc(s) = ?, Gc(z) = ?

Ignore Sample & Hold (S&H) Effect,

PWM Modulator Gain Fm = 1,

Continuous Plant Gp1(s) = Kd.Fm.Gp(s),

Fm

Control Design by Emulation


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Continuous System Bode Plot

14.3 s^2 + 651400 s + 7.2e009

Gc1(s) = ------------------------------------------

s^2 + 125600 s


Use Matlab SISOTOOL for the plant Gp1(s) and design thecontinuous controller Gc1(s)

(Matlab)

s-plane root locus

(Matlab)

Settling Time(1%)

< 45uS

BW = 25kHz, PM = 71 deg


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12.34 z^2 - 22.53 z + 10.28

Gc1(z) = -------------------------------------------

z^2 - 1.605 z + 0.6051

[pole-zero matched,

Ts = 4uSec]


Compute Equivalent Discrete Controller Gc(z)1. Discrete Equivalents via Numerical Integration

1a. Forward rule, s= (z-1)/Ts

2a. Backward rule, s = (z-1)/zTs3a. Trapezoidal/Tustin/Bilinear, s = 2(z-1)/Ts(z+1)

2. Pole-Zero Matching Equivalents, z = esTs

3. Hold Equivalents : zero-order-hold (ZOH), first-order-hold (FOH)

In Matlab, Gc_z = c2d(Gc_s, Ts, 'matched')

12.49 z^2 - 22.81 z + 10.41

Gc1(z) = ------------------------------------

z^2 - 1.598 z + 0.5985

[Tustin, Ts = 4uSec]

In Matlab, Gc_z = c2d(Gc_s, Ts, tustin')


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Discrete System Bode Plot, Pole-Zero Matched Controller,

Discrete System Bode Plot, Tustin Controller,

Control Design by Emulation

(Matlab)

(Matlab)

Gp1(z)*Gc1(z)

BW = 25.2kHz, PM = 53.1 deg, GM = 11.3dB

BW = 25.4kHz, PM = 53.6 deg, GM = 11.2dB

Gp1(z)*Gc1(z)

Transient Response (Fpwm = 250KHz),Pole-Zero Matched Controller

Gp1(z)*Gc1(z)


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Direct Digital Control


d

Vin

U(n)

Vo

Kd

Iin

Gc(z)

D/A(ZOH)

VrefTMS320F2810

LC

RL

+

Vo(n)

E(n)

=

d

Vo(s)PG

Hc

Comp Delay Model

Hc = e-sTd ,Td = Comp Time Delay

Ts


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Direct Digital Control of DC/DC Converter

fs = 250kHz,

f = 125kHz,

additional

phase lag of 90

f = 7.25kHz,

additionalphase lag of 5.2

PM = 33.18 deg

PM = 28 deg

Effect of Sampling & Hold

ZOH = -!Ts/2

= -180f/fs

Ts

Time Delay Ts/2


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Direct Digital Control

1.62x10-5 s + 2.5

Kd.Gp(s) = -------------------------------------

1.685x10-9 s2 + 1.648x10-5 s + 1

Vin=5.0, RL=0.1, Kd=0.5

L=1uH, C=1620uF,

Rc=0.004 ohm

ZOH(s) = (1 e-sTs )/s

Discrete Plant Model,Gp(z) = Z{ZOH(s).Kd.Gp(s).Hc}

d

U(n)

Vo

Kd

Gc(z)

ZOH

Vref

+

Vo(n)

E(n)

Gp(s)

Ts

Gp(z)

Hc


Hc = e-sTd

Gp1(z) = (0.0494z - 0.0261)/(z2 - 1.952 z + 0.962), [Td=0, Hc = 1]


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Discrete System Bode Plot,

2 Pole 2 Zero Type Controller,

Use Matlab SISOTOOL for Gp1(z), and design Gc2(z)

Gp1(z)*Gc2(z)

14.87 z^2 - 26.91 z + 12.16

Gc2(z) = -------------------------------------

z^2 - 1.473 z + 0.4731

BW = 27.9kHz, PM = 61.6 deg, GM = 9dB

(Td=0)

Settling Time(1%) < 56 uSec

Gp1(z)*Gc2(z)


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Direct Digital Control of DC/DC ConverterEffect of Computation Delay

Plant with computation delay [Td = 0.5Ts],

Gp2(z) = (0.022z^2+0.017z - 0.158)/z(z^2 - 1.952 z + 0.962),

Controller with no delay compensation,

Gc2(z)=(14.87 z^2 - 26.91 z + 12.16)/(z^2 - 1.473 z + 0.4731 )

BW = 26.9kHz, PM = 41 deg, GM = 7.46dB

Hc = -!Td= -360fTd

Loss of PM from

(Gp1*Gc2) to (Gp2*Gc2)

= 61.6-41

= 20.6 deg

Hc = 360(26900)(2uS)

= 19.37 deg

Bode Plot (Matlab)

Gp2(z)*Gc2(z)

Phase Lag,


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Bode Plot (Measured)

BW = 22.45kHz, PM = 40 deg, GM = 10.7dB

Gp2(z)*Gc2(z)


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Transient Response (Fpwm

= 250KHz)


Gp2(z)*Gc2(z)


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Plant with increased computation delay [Td = 2.0Ts],

Gp3(z) = (0.022z^2+0.017z - 0.159)/z^2(z^2 - 1.954 z + 0.963),

Direct Digital Control of DC/DC ConverterEffect of Computation Delay

Controller with no delay compensation,

Gc2(z)=(14.87 z^2 - 26.91 z + 12.16)/(z^2 - 1.473 z + 0.4731 )

Hc = -!Td

= -360fTd

Loss of PM from

(Gp1*Gc2) to Gp3*Gc2

= 61.6 (-19)

= 80.6 deg

Hc = 360(27900)2(4uS)

= 80.35 deg

Bode Plot (Matlab)

Gp3(z)*Gc2(z)

2 Pole 2 Zero Type Controller

BW = 27.9kHz, PM = -19.0 deg, GM = -2.22dB,

Unstable Loop.

Phase Lag,


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Unstable System, Uncompensated for Computation DelayTransient Response (Fpwm = 250KHz)

Gp3(z)*Gc2(z)


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Direct Digital Control of DC/DC ConverterRedesigned Controller with Delay Compensation

14.4 z^3 31.1 z^2 + 20.1 z 3.376

Gc3(z)=U/E= -------------------------------------------------

z^3 - 1.235 z^2 + 0.2362 z - 0.00115

Bode plot (Matlab)

BW = 16.1kHz, PM = 46.4 deg, GM = 3.77dB

Gp3(z)*Gc3(z)

3 Pole 3 Zero Type Controller


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Direct Digital Control of DC/DC ConverterRedesigned Controller with Delay Compensation

Bode plot (Measured)

Gp3(z)*Gc3(z)

BW = 15.28kHz, PM = 41.76 deg, GM = 3.4dB


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System Compensated for Computation Delay

Transient Response (Fpwm = 250KHz)

Gp3(z)*Gc3(z)


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Voltage Mode Control: Computation Flow, Benchmark Results

9.962625941300500

21.52655941600250

Number of LoopsCycles/loop

Available

CyclesOverheadCycles

Sampling Freq

(KHz)

TMS320C28x=150MHz

(32-bit implementation)


( ) ( ) ( ) ( ) ( )nEbnEbnEbnUanUanU ++++= 011221122)(

14.87 z2 26.91 z + 12.16 14.87 26.91 z -1 + 12.16 z -2

Gc(z) = U/E = ------------------------------------ = -------------------------------------------

z2 - 1.473 z + 0.4731 1 1.473 z -1 + 0.4731 z -2

PWMPRDnUsatDprdnUnUsat

=

=

)(max)(min)(

Gc(z)Vref

Vo

Dprd


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Hc = -!Td = -360fTd = -360f(kTs) = -360k /(fs/f), [ k = Td /Ts]


Sampling Frequency (fs) Selection

0

20

40

60

80

100

120

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

K

PhaseLag

(Hc)

fs/fc=5

fs/fc=10

fs/fc=12.5

fs/fc=20

fc = crossover frequency

Computation Delay per unit Ts, (Td /Ts)


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Digital Control of DC/DC ConverterSampling Frequency (fs) Selection

fs = 12.5*fc

fs = 20*fc

fs = 30*fc


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PWM Resolution & Limit Cycle

DSP Clock Freq = 150MHz, fpwm = 250kHz,

PWM Duty Ratio Resolution

= 1/(150M/250k) = 1/600 = 0.167%

ADC resolution = 10bits, Vo = 2V (max),

Vo Sensing Resolution "Vad = 2V/1024 = 1.95mV

Sense

circuit

!Vpwm Vo

PWM

Vin

A/D

!Vad

For Vin = 5V, Applied Volt Resolution!Vpwm1 = 5V/600 = 8.33mV,

For Vin = 2V, Applied Volt Resolution "Vpwm2 = 2V/600 = 3.33mV,


"Vpwm1 > "Vad,

=> Limit Cycle

"Vpwm2 #"Vad,

=> Negligible Limit Cyc.

Vin = 2V

Vo = 0.8V

Vin = 5V

Vo = 1.6V

dsp control loop design

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