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DSP handling of Video sources DSP handling of Video sources and Etherenet data flowand Etherenet data flow

SupervisorSupervisor::Moni Orbach Moni Orbach StudentsStudents::

Reuven YogevReuven YogevRaviv ZehuraiRaviv Zehurai

Technion – Israel Institute of TechnologyTechnion – Israel Institute of TechnologyHigh speed Digital LabHigh speed Digital Lab

Project D1722Project D1722 Final PresentationFinal Presentation

24.08.0424.08.04

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System StructureSystem Structure

BridgingBridging

CardCardFIFOFIFO

00100 10100 DSPDSP00011

MemoriesMemories

00100

EthernetEthernet

ControllerController

Evaluation BoardEvaluation Board00100

Video Video SourcesSources

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Hardware Integration – step AHardware Integration – step A

The first stage was to connect the video camera to the bridging card, in order to examine the camera’s operation and our abilities to initialize it.

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Hardware Integration – step AHardware Integration – step A

We received the information from the video camera through connector C2 along with the relevant control signals (as programmed in VHDL).

We used Logic Analyzer to view the signals. This information is later on inserted to the FIFO on the evaluation board.

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Hardware Integration – step BHardware Integration – step B

0xFFFF00000xFFFF00000x000000000x00000000

0x0000FFFF0x0000FFFF

0xFFFFFFFF0xFFFFFFFF

FIFO

The second step was to connect the bridging card to the evaluation board. We disconnected the camera video from the bridging card and it injected Test Pattern to the FIFO, accompanied by appropriate control signals.

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Hardware Integration – step BHardware Integration – step B

The DSP was unable to read the FIFO, because it was burned, therefore we were instructed to move on.

We reduced the signal to a third of its value on the entrance to the FIFO.

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The C6416 DSPThe C6416 DSP

System block diagram

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The main components of the DSPThe main components of the DSP

The main core of the system – CPUThe main core of the system – CPUL1 Program memory – 16KBL1 Program memory – 16KBL1 Data memory – 16KB L1 Data memory – 16KB The Enhanced DMAThe Enhanced DMAL2 memory / cache – 1MBL2 memory / cache – 1MBEMIF A (64 bit) and EMIF B (16 bit)EMIF A (64 bit) and EMIF B (16 bit)McBSPMcBSPTimersTimers

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The EDMA ArchitectureThe EDMA Architecture

The EDMA controls access to resources and The EDMA controls access to resources and arbitrates between concurrent transfers.arbitrates between concurrent transfers.The EDMA includes 64 channels with The EDMA includes 64 channels with programmable priority, and has the ability to programmable priority, and has the ability to link and chain data transfers. link and chain data transfers. Transfer requests originate from many Transfer requests originate from many requestors: the sixty-four programmable requestors: the sixty-four programmable EDMA channels, the level 2 (L2) memory EDMA channels, the level 2 (L2) memory controller, and other master peripherals.controller, and other master peripherals.

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SUBMITTING TRANSFER REQUEST SUBMITTING TRANSFER REQUEST

The transfer request chain The transfer request chain

1111

Assuming each makes a submission on the same cycle, Assuming each makes a submission on the same cycle, the requestor closest to the TC arrives first, and the the requestor closest to the TC arrives first, and the farthest arrives last.farthest arrives last.Once a request is within the request chain, it has priority Once a request is within the request chain, it has priority over new submissions, such that the requests at the end over new submissions, such that the requests at the end of the chain (HPI/PCI) do not get starved for servicing. of the chain (HPI/PCI) do not get starved for servicing. Once a transfer request reaches the end of the request Once a transfer request reaches the end of the request chain, it is sent to the transfer crossbar (TC). Within TC, chain, it is sent to the transfer crossbar (TC). Within TC, the transfer request shifts into one of the transfer the transfer request shifts into one of the transfer request queues to await processing. request queues to await processing. Once the transfer request reaches the head of its queue, Once the transfer request reaches the head of its queue, it is submitted to the address generation/transfer logic it is submitted to the address generation/transfer logic for processing. The address generation/transfer logic for processing. The address generation/transfer logic only services one transfer request from each queue. only services one transfer request from each queue. In order to maximize the data transfer bandwidth in a In order to maximize the data transfer bandwidth in a system, we should utilize all queues.system, we should utilize all queues.

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The EDMA Controller ArchitectureThe EDMA Controller ArchitectureThe EDMA controller block diagramThe EDMA controller block diagram

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The EDMA controller comprises:The EDMA controller comprises:

Event and interrupt processing registersEvent and interrupt processing registers

Event encoderEvent encoder

Parameter RAM (PaRAM)Parameter RAM (PaRAM)

Address generation hardwareAddress generation hardware

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The Mechanism of Data TransferThe Mechanism of Data Transfer The event register captures EDMA events. An The event register captures EDMA events. An

event is a synchronization signal that triggers event is a synchronization signal that triggers an EDMA channel to start a transfer. If events an EDMA channel to start a transfer. If events occuroccur

simultaneously, the event encoder resolves simultaneously, the event encoder resolves them. The transfer parameters corresponding them. The transfer parameters corresponding to this event are stored in the EDMA to this event are stored in the EDMA parameter RAM, and are passed onto the parameter RAM, and are passed onto the address generation hardware, which address address generation hardware, which address the EMIF and/or peripherals to perform the the EMIF and/or peripherals to perform the necessary read and write transactions.necessary read and write transactions.

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The Parameter Ram (PaRAM)The Parameter Ram (PaRAM)The table is a 2K-byte block of internal parameter The table is a 2K-byte block of internal parameter RAM.RAM.The PaRAM table consists of six-word parameter The PaRAM table consists of six-word parameter entries of 24 bytes each, for a total of 85 entries.entries of 24 bytes each, for a total of 85 entries.The contents of the 2K-byte PaRAM include 64 The contents of the 2K-byte PaRAM include 64 transfer parameter entries for the 64 EDMA events.transfer parameter entries for the 64 EDMA events.Remaining parameter entries (21 entries) serve as Remaining parameter entries (21 entries) serve as additional parameter sets used for linking transfers.additional parameter sets used for linking transfers.Once an event is captured, its parameter entries are Once an event is captured, its parameter entries are read from one of the top 64 entries in the PaRAM. read from one of the top 64 entries in the PaRAM. These parameter entries are then sent to the address These parameter entries are then sent to the address generation hardware.generation hardware.

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The Structure of EDMA channel The Structure of EDMA channel parameter entry parameter entry

Each parameter entry of an EDMA event is organized into six 32-bit words or 24 bytes

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EDMA Channel Options Parameter (OPT)EDMA Channel Options Parameter (OPT)

EDMA Channel Source Address Parameter (SRC)

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EDMA Channel Transfer Count EDMA Channel Transfer Count Parameter (CNT)Parameter (CNT)

EDMA Channel Destination Address Parameter (DST)

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EDMA Channel Index Parameter (IDX)EDMA Channel Index Parameter (IDX)

EDMA Channel Count Reload/Link Address Parameter (RLD)

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The Link FeatureThe Link Feature An important capability of the EDMA is that of linking. An important capability of the EDMA is that of linking.

By providing a link address and setting LINK = 1 in the By providing a link address and setting LINK = 1 in the transfer options, an EDMA channel loads a new entry transfer options, an EDMA channel loads a new entry from PaRAM and begins performing the new transfer. from PaRAM and begins performing the new transfer. The linked list is traversed until LINK = 0.The linked list is traversed until LINK = 0.

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The NDKC64x - Network Development The NDKC64x - Network Development Kit for C64xKit for C64x

The main Hardware features of the NDKC64x The main Hardware features of the NDKC64x are:are:

10/100 Mb/s Fast Ethernet controller10/100 Mb/s Fast Ethernet controller

IEEE 802.3u compliant MAC/PHYIEEE 802.3u compliant MAC/PHY

128 KB of on-board memory128 KB of on-board memory

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The Client Project The Client Project

We use the client project as a platform which allow us We use the client project as a platform which allow us to send the image we built through the Ethernet.to send the image we built through the Ethernet.

This client project give us this capability by:This client project give us this capability by: Creating a socketCreating a socket Configuring the Tx and Rx timeoutConfiguring the Tx and Rx timeout Connecting the socket to an addressConnecting the socket to an address Allocate a buffer which will be sent through the Allocate a buffer which will be sent through the Ethernet. In this case, the buffer is our image.Ethernet. In this case, the buffer is our image.Send the buffer and receive it back.Send the buffer and receive it back.