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The ATLAS Liquid Argon Calorimeters Read Out Driver (ROD)

The TMS320C6414 DSP Mezzanine board

Abstract : In this document, a detailed description of the ATLAS Liquid Argon Calorimeters Read Out Drivers prototype mezzanine designed around the TMS320C6414 from Texas Instrument, is given. The document is organized as follows : after an overall presentation of the board, the functionality of the main components are described. The document ends with miscellaneous points as power supply, JTAG, board technical considerations and planned cost.

Author : Julie PRASTWeb page : http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod/index.htmlFile name : pu6414final.docCreated : June 2002.Last updated : 04/09/2002Version : 1.2

The TMS320C6414 Processing Unit 24/05/2023 1/23

1 Table of contents

1 TABLE OF CONTENTS................................................................................................................................2

2 OVERALL PRESENTATION......................................................................................................................3

2.1 INTRODUCTION..........................................................................................................................................32.2 THE TMS320C6414 MEZZANINE FINAL ARCHITECTURE...........................................................................3

3 MAIN COMPONENTS..................................................................................................................................4

3.1 THE INPUT FPGA......................................................................................................................................43.1.1 Parallelisation and control...............................................................................................................43.1.2 Data organization in the internal dual port memory........................................................................53.1.3 DSP interface....................................................................................................................................5

3.2 THE DSP....................................................................................................................................................63.2.1 EMIFA...............................................................................................................................................63.2.2 EMIFB...............................................................................................................................................63.2.3 Host Port Interface (HPI).................................................................................................................63.2.4 McBSP...............................................................................................................................................63.2.5 Interrupts and general purposes Pins...............................................................................................7

3.3 THE OUTPUT FPGA...................................................................................................................................73.3.1 The TTC interface.............................................................................................................................73.3.2 The VME interface............................................................................................................................8

3.4 THE OUTPUT FIFO.....................................................................................................................................9

4 POWER SUPPLY AND JTAG....................................................................................................................10

4.1 POWER-SUPPLY........................................................................................................................................104.2 JTAG CHAIN............................................................................................................................................10

5 MISC..............................................................................................................................................................10

5.1 BOARD TECHNICAL CONSIDERATIONS....................................................................................................105.2 ESTIMATED COST.....................................................................................................................................105.3 AVAILABILITY OF COMPONENTS AND TOOLS..........................................................................................115.4 COMING MILESTONES..............................................................................................................................11

6 REFERENCES..............................................................................................................................................11

7 ABBREVIATION.........................................................................................................................................12

8 ANNEXES......................................................................................................................................................13

8.1 ANNEXE 1 : ADC READ OUT INPUT EVENT FORMAT..............................................................................138.2 Annexe 2 : Schematics, routing and placement.....................................................................................14


2 Overall presentation

2.1 Introduction To assess the feasibility of the project, the ATLAS LAr collaboration has decided in 1999 to make a ROD (Read Out Drivers) demonstrator. The project consisted in the construction of a motherboard (developed by the University of Geneva, Switzerland), into which could be plugged up to 4 daughterboard processing units (PU), each PU treating 64 calorimeter channels (an half FEB). The architecture of the PU was based around a Digital Signal Processor (DSP). Three PU were designed, two based on an integer DSP the TMS320C6202 from Texas Instrument (developed by the CPPM-Marseille-France and Nevis-USA) and the other based on a floating point processor the ADSP21160 from Analog Devices (developed by the LAPP- Annecy- France).The techniques evolution and the arrival of a new powerful DSP opens the possibility to double the system density by handling 128 channels instead of 64 in a single DSP. That’s why in the second half of 2001, an evaluation board based around the TMS320C6414 from Texas Instrument were developed, conjointly by Nevis and LAPP teams. This DSP was finally adopted by the ROD community for the final board last June. The final design consists of 4 daughterboards per ROD module, each daughterboard equipped with two DSP, increasing the ROD density to 8 FEB per DSP, instead of two in the demonstrator. Further more, for financial reasons, the ROD system should provide staging capabilities. In the staging scenario, a daughterboard among two, will be populated on the motherboard at the beginning of the experiment, bringing to 256 the number of channels treated by a single DSP, at the expense of potential loss in performance (reduced trigger rate).This document aims to describe the final daughter board architecture.

2.2 The TMS320C6414 mezzanine final architecture Figure 1 shows the TMS320C6414 mezzanine final architecture :

Figure 1 : TMS320C6414Mezzanine block diagram

The mezzanine is a 120*85 mm board, composed of two 64 pins and one 84 pins connectors that can be plugged on the motherboard. The mezzanine is composed of two processing units (PU), able to treat each up to 128 calorimeter channels (1 FEB) in normal mode and 256 channels (2 FEB) in staging mode. Each PU is composed of an input FPGA (InFPGA), a TMS320C6414 DSP from Texas Instrument and an output FIFO. The mezzanine contains also an output FPGA (OutFPGA) used for the VME and TTC interface.Input FEB data enters the InFPGA where they are formatted and checked as needed for the DSP algorithm. When an event is ready, an interrupt is sent to the DSP which launches a DMA to read the data on the 64-bits


InFPGA config

InFPGA config

EMIFA

EXT_INT

EMIFA

EXT_INT

TMS320C6414

TMS320C6414

Input FPGA

Apex 20k160

FEB1

FEB3

FEB2

FEB4Input FPGA

Apex 20k160

16

16

16

1664

64

FIFO4k*16

FIFO4k*16

16

16

16

JTAG

EMIF B

EMIF B

16

16

BCIDTType

Output FPGAAcex 1k30

McBSP0McBSP1

McBSP0

McBSP1 TTCTTCinterface

16

McBSP2

McBSP2

HPI

HPI

VMEVMEinterface

InFPGA config

InFPGA config

EMIFA

EXT_INT

EMIFA

EXT_INT

TMS320C6414

TMS320C6414

Input FPGA

Apex 20k160

FEB1

FEB3

FEB2

FEB4Input FPGA

Apex 20k160

16

16

16

1664

64 EMIFA

EXT_INT

EMIFA

EXT_INT

TMS320C6414

TMS320C6414

Input FPGA

Apex 20k160

FEB1

FEB3

FEB2

FEB4Input FPGA

Apex 20k160

16

16

16

1664

64Input FPGA

Apex 20k160

FEB1

FEB3

FEB2

FEB4Input FPGA

Apex 20k160

16

16

16

1664

64

FIFO4k*16

FIFO4k*16

16

16

16

JTAG

EMIF B

EMIF B

16

16

BCIDTType

Output FPGAAcex 1k30

McBSP0McBSP1

McBSP0

McBSP1 TTCTTCinterface

16

McBSP2

McBSP2

HPI

HPI

VMEVMEinterface

EMIFA bus. Once the DSP has finished processing an event, it writes the results in the output FIFO through the 16 bits EMIFB bus. The TTC data are received in the OutFPGA and sent to each DSP via 2 serial ports (McBSP). A serial port is for the Trigger type and the other is for the BCID and EventID.

The OutFPGA allows the control of the board by VME, in particular : - DSP boot written and histograms read through the 16-bits Host Port Interface (HPI) of the DSP.- Full duplex serial port (McBSP2) with each DSP (run number written, DSP commands, status read)- InFPGA configuration written (number of samples, number of gains, mode…) and status read

through a serial line.- InFPGA boot.

3 MAIN COMPONENTS

3.1 The input FPGA The InFPGA parallelizes incoming FEB data, verifies their consistency (in particular potential corruption coming from radiation effects, like SEU), and formats the data as needed for the DSP algorithm. The InFPGA is an APEX20k160EBC208-1 from Altera. The choice of this component is described in references [3].The InFPGA has three main parts :

1. Parallelization and control of the incoming data.2. Data organization in the dual port memory.3. DSP interface.

Figure 2 shows the InFPGA architecture in staging mode, ie when treating 2 FEBs:

Figure 2 : Input FPGA architecture (staging mode)

3.1.1 Parallelisation and control The InFPGA receives input data from the mother board through two 80 MHz 16-bits bus. Each 16-bits

bus corresponds to one FEB (128 channels = 16 ADC). In normal mode, the InFPGA treats one FEB, whereas in staging mode, the InFPGA treats two FEBs. The format of the incoming data is described in annexe 1.


16 bits @

80

ADC1 //

ADC16 //

Generation of timing signals +

data and synchro check

MUX

Parallelization of 2 HFEB

16

Data organization

in double port RAM

(64 bits wide)

16

64INT4

DSP Interface

64

CS1

16 bits @

80

ADC1 //

ADC16 //

Generation of timing signals + data and synchro

check

MUX

Parallelization of 2 HFEB

16

Data organization

in double port RAM

(64 bits wide)

16

64

INT5

DSP Interface

CS2

For each FEB, timing signals are generated internally (indication of the data type : header, RADD, data, …)

For each ADC, the InFPGA detects the start of event and does the serial to parallel conversion (2 bits -> 16 bits).

For each word, except the start and end of event, the parity is checked. For each data word, the gain is isolated and compared to the other gains of the same channel. Gains

from 8 channels are grouped in 16 bits data words. Several checks are performed :

Parity check. Start of data alignment to check half-FEB (HFEB) desynchronization. Identical gain for all samples of a given channel. Identical control words and RADD within an HFEB. Identical control words and RADD between two HFEB.

When en error is detected, the InFPGA fills the event status word. This word is interpreted by the DSP in the synchronization task. If the status is different to zero, the DSP will take the appropriate decision, as asking for a FEB reset. The synchronization task is described in more details in reference [10].

The content of the event status word is described below:

31 26 25 24 23 8 7 6 5 4 3 2 1 00 Radds bcids gain or BOF parity ctrl3 gain radd ctrl2 ctrl1 ones

Table 1 : Content of the event status word.

bit 0 ones : The beginning of event is missing in one of the 16 groups of channels.bit 1 ctrl1 : Ctrl1 mismatchbit 2 ctrl2 : Ctrl2 mismatchbit 3 radd : RADD mismatchbit 4 gain : Gain mismatch (the gain bits are not preserved across the time samples, for some channels)bit 5 ctrl3 : CTRL3 mismatch[7..6] parity: Parity errors counts (0 = no error, 1 = 1 error, 2 = 2 errors, 3 = 3 or more errors)[23..8] gain or BOF In case of error in the gain or BOF, precise which group of channels is concerned (bit 8 = ch0)bit 24 bcids comparison between BCID of channels 0-63 versus channels 64-128bit 25 radds comparison between RADD of channels 0-63 versus channels 64-128

3.1.2 Data organization in the internal dual port memory Data is then organized in a dual port memory as needed to optimize the DSP algorithm. The data format is presented below :

bits [63..48] bits[47..32] bits [31..16] bits[15..0]0 Event status Event status EventID BCID

1 ctrl1 ctrl2 ctrl3 Radd1

2 Radd2 Radd3 Radd4 Radd5

3 C0 Gain C0 S1 C0 S2 C0 S3

4 C0 S4 C0 S5 C1 gain C1 S1

5 C1 S2 C1 S3 C1 S4 C1 S5

6 C2 Gain C2 S1 C2 S2 C2 S3

194 C127 S2 C127 S3 C127 S4 C127 S5Table 2 : Dual port memory organization

The dual port memory of the InFPGA is configured as a dual bank memory. While the DSP is reading a complete event from one bank, a new event can be written into the other bank. Therefore, the minimal size of the InFPGA dual port memory is two events. Please refer to note [3] for more details about the dual port memory organization.

3.1.3 DSP interface When a complete FEB event is stored in the memory, the InFPGA sends an interrupt to the DSP. The DSP then launches a DMA to read the event. The reading is cadenced by the DSP clock. The frequency is configurable,


but it is today foreseen at 100 MHz (CPU/6). From the reading side, the internal dual port memory of the input FPGA is seen by the DSP as a FIFO, implying that the data is read in consecutive addresses. There is one interrupt and DSP chip select per FEB.

3.2 The DSP The DSP is the 600 MHz TMS320C6414GLZ, which is among the latest generation of the Texas Instrument DSP.The DSP receives FEB data on its EMIFA memory bus, TTC information on serial ports McBSP0 and McBSP1 and transmits the output data through its EMIFB memory bus. The Host Port Interface (HPI) is used to boot the DSP and read histograms.Details about the DSP code are given in the following references :

Input /output management and code structure: see reference [5] Real time operating system : see reference [11] Physics code : see reference [12]

Paragraphs bellow summarizes the DSP communications.

3.2.1 EMIFA The External Memory Interface A (EMIFA) is directly connected to the InFPGA. The EMIFA is a 64 bits wide bus. The EMIFA clock AECLKOUT2 is generated internally and is configured to run at CPU/6 = 100 MHz. This EMIFA is used to read input FEB data in the InFPGA. As a dual port RAM is foreseen in the InFPGA for each FEB, one interrupt and one Chip Enable (CE) are foreseen per FEB.

CE DSP memory address R/W Connected to Purpose ModeCE0 8000 0000 R InFPGA FEB 1 DP-RAM synchronous read interface.

CE1 9000 0000 R InFPGA FEB 2 DP-RAM (staging) synchronous read interface.

CE2 A000 0000 InFPGA Connected but not defined

CE3 B000 0000 InFPGA Connected but not definedTable 3 : EMIFA memory map

3.2.2 EMIFB The External Memory Interface B (EMIFB) is directly connected to the output FIFO. The EMIFB is a 16 bits wide bus. The EMIFB clock BECLKOUT2 is generated internally and is configured to run at CPU/6 = 100 MHz. This EMIF is used to send output events to the FIFO.

CE DSP memory address R/W Connected to Purpose ModeCE0 6000 0000 W Output FIFO Output FIFO write synchronous write interface

CE1 6400 0000 W Output FPGA end of output DMA synchronous write interface

CE2 6800 0000 / Connected but not defined

CE3 6C00 0000 / Connected but not definedTable 4 : EMIFB memory map

3.2.3 Host Port Interface (HPI) The HPI is a parallel port through which the VME (host processor) can directly access the CPU’s memory space. The VME has ease of access because it is the master of the interface. The host and CPU can exchange information via internal memory. For more details about the HPI, have a look on reference [6], chapter 7.On the mezzanine board, the HPI is configured as a 16-bits wide bus connected to the output FPGA. The HPI is mainly used for the DSP boot, histograms reading and debugging purposes.

VMER/W connected to Purpose ModeW output fpga Boot No particular configuration

R Output fpga Histograms, debug variables No particular configurationTable 5 : HPI description.

Note : During DSP reset, the OutFPGA pulls down the HD5 signal to configure the HPI as a 16 bits words interface.

3.2.4 McBSP


The Multi channel Buffered Serial ports are Full duplex communication DSP serial ports, with independent framing and clocking for receive and transmit.The TMS320C6414 has 3 McBSP connected to the output FPGA. McBSP0 and McBSP1 are used for TTC data (DSP receives only), while McBSP2 is bi-directional and used to send commands to the DSP or to read the DSP status.

McBSP R/W Connected to PurposeMcBSP0 R output FPGA BCID + Event ID

McBSP1 R output FPGA Trigger type transmission

McBSP2 R/W outputFPGA DSP Commands writeDSP status read, …

Table 6 : McBSP description

3.2.5 Interrupts and general purposes Pins Table 7 summarizes the DSP General Purposes (GP) configuration pins.

GP function Connected to PurposeGP0 Output GP InFPGA Input FPGA led1 blankingGP1/

CLKOUT4NC

GP2/CLKOUT6

NC

GP3 Output GP InFPGA Input FPGA led1 blankingGP4/

EXT_INT4interrupt InFPGA Interrupt dedicated to FEB1 DMA

GP5/EXT_INT5

interrupt InFPGA Interrupt dedicated to FEB2 DMA

GP6/EXT_INT6

interrupt InFPGA Not defined

GP7/EXT_INT7

interrupt InFPGA Not defined

GP8/CLKS2 NCGP9 Output GP Connector B PU_IRQGP10 Output GP Connector B BUSYGP11 Input GP OutFPGA FIFO almost fullGP12 OutFPGA Not definedGP13 OutFPGA Not definedGP14 OutFPGA Not definedGP15 NC

Table 7 : interrupts and general purposes pins

3.3 The Output FPGA The OutFPGA is an ACEX EP1k30FC256-2 from Altera. This FPGA has 2 main purposes: the TTC and VME interface. It boots from an EPC2 (eeprom) at power up.

3.3.1 The TTC interface The OutFPGA drives the TTC data coming from the motherboard TTC FPGA and going to both DSP through 2 serial ports also called McBSPs. McBSP0 is reserved for the BCID and event ID, whereas the McBSP1 is reserved for the Trigger type.The communication protocol is described in the figure bellow :


TTCx_BCID_Frame

TTCx_TType_Data

TTCx_TType_Frame

BCID 12 bits EVTID 32 bits

TType 8 bits TType 8 bits

40 MHZ Clock

TTCx_BCID_Data MSB

MSB

MSB

MSB

Figure 3 : TTC communication protocol

The protocol for BCID corresponds to a frame having 2 phases of different length one for the BCID and the other for the EVTID each having one element. There must be at least 2 clock cycles between each frame.For the TType there is one frame with only one phase and one element. There must be at least 2 clock cycles between each frame.You can get a detailed description of the Ti6414 McBSP in the manual TMS320C6000 Peripherals reference Guide chapter 12.2 and a detailed description of the TTC FPGA in reference [8].

3.3.2 The VME interface The OutFPGA includes the VME interface of the mezzanine board. It decodes data coming from the motherboard and generates data according to the motherboard protocol. The communication protocol between the mezzanine and the mother board is described in reference [4].Table 8 summarizes all the OutFPGA registers that can be accessed by VME (32 bits wide).

PU_add[4..0] VMEadd R/W Function0 +0 R/W control 1 register1 +4 R Status 1 register2 +8 R/W HPI register (DSP1)3 +C W Broadcast HPI register (both DSP)4 +10 W serial data to McBSP2 (DSP1)5 +14 R Serial data from McBSP2 (DSP1)6 +18 W InFPGA configuration data (8 MSB) both InFPGA7 +1C W InFPGA configuration register (15 LSB) both InFPGA8 +20 R InFPGA1 status register (15 LSB)9 +24 R Test register

16 +40 R/W control 2 register17 +44 R Status 2 register18 +48 R/W HPI register (DSP2)19 +4C W Broadcast HPI register (both DSP)20 +40 W serial data to McBSP2 (DSP2)21 +54 R Serial data from McBSP2 (DSP2)22 +58 W InFPGA configuration data (8 MSB) both InFPGA23 +5C W InFPGA configuration register (15 LSB) both InFPGA24 +60 R InFPGA2 status register (15 LSB)28 +64 R Test register

Table 8 : VME Memory Map

The paragraphs bellow detail the purpose of each register.

3.3.2.1 Control register

The control register is described in table 9:

Bit number R/W Bit wise operator Functionality0 R/W 0000 0001 DSP reset

1 R/W 0000 0002 FIFO reset

2 R/W 0000 0004 Input FPGA reset

3 R/W 0000 0008 HPI reset

4 R/W 0000 0010 HPI burst


5 R/W 0000 0020 DSP launch

6 R/W 0000 0040 /Input fpga nconfig Table 9 : Control Register

3.3.2.2 Status register

The status register is described in table 10:

Bit number R/W Bit wise operator Functionality[7:0] R 0000 00FF Number of events in the output FIFO.

8 R 0000 0100 output FIFO empty flag9 R 0000 0200 output FIFO almost full flag10 R 0000 0400 output FIFO half full flag11 R 0000 0800 output FIFO Almost full flag12 R 0000 1000 output FIFO full flag14 R 0000 4000 Data from McBSP2 available15 R 0000 8000 Serial port buffer overwritten by new data from

McBSP2.

24 R 0100 0000 GP1125 R 0200 0000 GP1226 R 0400 0000 GP1327 R 0800 0000 GP1428 R 1000 0000 HPI INT29 R 2000 0000 HPI Ready30 R 4000 0000 InFPGA nstatus31 R 8000 0000 InFPGA confdone

Table 10 : Status register

Note : the counter of the number of events currently in the output FIFO is increased by the DSP (dedicated Chip Select) and decreased with the output controller fifo_evt_end signal.

3.3.2.3 HPI interface

The OutFPGA includes also the HPI interface, used for the boot of the DSP and for the read out of the histograms. Both DSP can be accessed in broadcast or independently through the specific registers.The way the HPI protocol is implemented in the output FPGA is described in [7].

3.3.2.4 McBSP2 interface

The OutFPGA has the possibility to exchange data with both DSP through the McBSP2 serial port. This serial port can be used to send commands to the DSP, to read the DSP status, ….

3.3.2.5 Input FPGA programming

The OutFPGA allows the programming of the InFPGA from VME. The ability to re-program the InFPGA in situ without use of the byte blaster is important since there can be different versions of the InFPGA configuration code (eg. calibration code, the 32 samples code or the normal 5 samples code). The OutFPGA programs the InFPGA through the dedicated signals provided by Altera for FPGA configuration (data0, dclk, nconfig, …). The configuration is done at 5 MHz. Both InFPGA are configured at the same time.

3.3.2.6 Input FPGA configuration and status register

The OutFPGA has also the possibility to dialog with each InFPGA through a home made serial protocol. This allows the configuration of the InFPGA and the access of the InFPGA status. Table 11 and 12 describe the content of these registers :

15 10 9 8 7 5 4 00 Number of gains 0 Number of samples

Table 11 : InFPGA configuration register

Table 12 : InFPGA status register

3.4 The output FIFO The Output FIFO is an IDT72V253L7-5BC 3.3V high density super synchronous 18-bits bus FIFO. The FIFO is organized in 4 kilo words of 18 bits.


15 8 7 6 5 4 00xBE 0 Number of gains Number of samples

The size of the FIFO is done assuming the following philosophy : We expect, in most of cases, that an entire event can be sent by the DSP. It allows the DSP to launch only one DMA and so not loose time. In seldom cases, when the event is big (raw data, ..), we accept loosing time and then slicing up the output event. Assuming 5 samples per event (most of cases), the output event size is about half of the input ie about 400*16 bits words per FEB. To store 2 events in the FIFO in staging mode, we need at least 1600 words. Due to the very small price difference between 2k and 4k depth FIFO and that they are pin compatible, the 4k FIFO is chosen for the prototype.

The FIFO has empty, full and programmable almost empty and almost full flags. These flags can be spied by VME through the status register . The offset value of the almost flag has been programmed to 1024 words, so that when this flag is not active, the DSP knows that there is enough place to write another event. On the final prototype, the use of the FIFO flags will allow to optimize the FIFO size for the production.The DSP can write the output events at full speed (100 MHz).

4 Power supply and JTAG

4.1 Power-supply The mezzanine board is supplied with an 3.3V unique voltage coming from the mother board and made from the VME 48V through a DC-DC regulator. The estimated power consumption is about 2.5A for the whole mezzanine. This estimation is based on previous studies performed with the TMS320C6414 evaluation board (5A measured for 4 evaluation PU based on a single TMS320C6414 running at 600MHz).The following voltages are derived from this 3.3V supply :

- the 2.5 V for the input FPGA core with the regulator TPS76825Q from Texas Instrument.- the 1.8 V for the output FPGA core with the regulator TPS76818Q from Texas Instrument. - the 1.4 V for the DSP core with an adjustable regulator, the TPS54610 from Texas Instrument. - The 3.3V for the DSP input/output, which must be set up after the DSP core voltage and with

specific setup requirements.

4.2 JTAG chain The JTAG chain includes in this order : DSP1, DSP2, InFPGA1, InFPGA2, EPC2, OutFPGA, FIFO1, FIFO2.The JTAG chain has 3 purposes on the board :

1. Boundary scan analyses: to verify interconnections (stuck at, short and open circuits) and identify defaults. Boundary scan is the main test foreseen to validate the electrical functionality of the mezzanine and more generally the ROD module. More details about these tools and the ROD test bench can be found in reference [9]

1. .2. Altera components programming : FPGAs and EPC2 configuration.3. DSP emulation for debug purposes. For this, the chain can be shorten and only includes both DSP

(the JTAG port of the DSP does not work properly if non-C64x devices are in the scan chain)

The JTAG chain can be controlled either from the mother board or from the mezzanine. The JTAG connector on the mezzanine board is a 2*7 plug connector compatible with the emulator pad. This connector is foreseen on the board because it contains some pins specific for the DSP emulation that are not on the mother board interface. As it is for debug purposes, this connector should not be populated on the production version.

5 MISC

5.1 Board Technical Considerations The mezzanine is a 120*85*1.4 mm board. It is made of 10 layers, 6 signal layers and 4 power planes. The signal layers present almost the same impedance (around 50 ohm for a 0.120 mm wide net) to preserve signal integrity. The whole board is routed with through hole vias :

- 0.5 mm diameter and 0.25 drill size under the DSP (0.8 mm BGA).- 0.6 mm diameter and 0.3 drill size elsewhere.

Annexe 2 shows the electrical schemes, the placement description and the routing of each layer.


5.2 Estimated cost Table 13 gives the foreseen cost for the prototype board so for small quantities and today cost. It does not include manufacturer equipment ie about 800 € for the printed circuit and 1200 € for the assembler (to be paid once only).

Description Manufacturer Part number Quant/ board

Unit cost (€)

Total cost

Printed circuit board production Techci 1 250 250PCB assembly Ardelec 1 150 150

Total without components and without manufacturer equipment

400

Input FPGA Altera EP20k160eqc208-1 2 180 360Output FPGA Altera EP1k30FC256-2 1 35 35DSP Texas Instrument TMS320C6414GLZ532 2 200 400

Output FIFO IDT IDT72V253BC100 2 25 50EEPROM Altera EPC2TC32 1 29 29oscillator 50 MHz Mextal SWO3 1 10 10Zero delay buffer Cypress CY2305SC-1 2 2,5 564 pins connector Tyco Electronics AMP120525-1 2 3,5 784 pins connector Tyco Electronics AMP120525-2 1 3,5 3,5DSP voltage regulator Texas instrument TPS54610PWP 1 10 10InFPGA voltage regulator Texas instrument TPS76825QPWP 1 1 1OutFPGA voltage regulator Texas instrument TPS76818QPWP 1 1 1DSP PLL filter ACF321825 2 0,3 0,6drivers Texas instrument SN74LVTH125DGV 3 0,5 1,5passive components (resistors, capa, inductance, leds, small connectors)

230 0,1 23

Mosfet canal P 1,8V Vishay SI4465DY 1 0,8 0,8Bipolair transistor NPN channel Fairschild MMBT3904 1 0,5 0,5

Total for components 937,9

Table 13 : prototype Mezzanine estimated cost

The estimated cost for the prototype mezzanine is about 1400 € (1000 € for components and 400 € for PCB and cabling) plus the cost of the manufacturer equipment (1200 €) divided by the number of mezzanine produced.

5.3 Availability of components and tools The components foreseen for the ROD mezzanine are recent and commercial chips. The FPGA (Altera products) should be maintained 5 years and the TMS320C6414 products, including tools, are guaranteed by Texas Instrument to be maintained and available during at least 5 years.

5.4 Coming milestones September 16-17 th : Preliminary reviewEnd of October : Prototype production launch.End of December : Prototype ready to be tested.Beginning of 2003: Prototype tests.March 2003 : Mother board tested with 4 PU.

6 REFERENCES [1] LAPP ROD web page :

http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod/index.html

[2] Daniel La Marra « Mezzanine board connectors.pdf » http://dpnc.unige.ch/LArgROD/Mezzanine Board Connectors.pdf

[3] Julie PRAST : « Input FPGA in ROD PU. » July 2002.http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod/Document/finalS2P.pdf

[4] Annie Leger “VME protocol”http://dpnc.unige.ch/LArgROD/VMEBusyFPGA.pdf


[5] Nicolas Chevillot « ATLAS ROD TMS320C6414 DSP based processing Unit. TestDemo1.2. DSP Hardware and code structure. »August 2002

[6] Texas Instrument “TMS320C6000 Peripherals Reference Guide” 2001

[7] Nicolas Chevillot “TMS320C6414 HPI interface” December 2001http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod/Document/HPI.pdf

[8] Guy Perrot “TTC FPGA” July 2002http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod_ttc_fpga/TTC_FPGA.pdf

[9] Guy Perrot “ROD Test Bench and integration tests” March 2002http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Testbench/ROD_Testbench.pdf

[10] Gelu Ionescu “Busy generation, event verification, event synchronization ” September 2002http://wwwlapp.in2p3.fr/informatique/Atlas_online/Documents/Dsp/ATL-ROD-RTX/AOS_ATL-

SYNC-ANA.pdf

[11] Gelu Ionescu “RTX ” September 2002http://wwwlapp.in2p3.fr/informatique/Atlas_online/Documents/Dsp/ATL-ROD-RTX/AOS_RTX-TI-

SRS1.pdf

[12] Remi Lafaye “The physics ROD 64x PU algorithm ” September 2002http://wwwlapp.in2p3.fr/informatique/Atlas_online/Documents/Dsp/ATL-ROD-RTX/AOS_ATL-DSP-

PHYS.pdf

7 ABBREVIATION BCID Bunch Crossing IdentifierDMA Direct memory accessDSP Digital Signal ProcessorEMIF External Memory InterFace of the DSP.FEB Front End BoardFIFO First In First OutHFEB Half FEBHPI Host port Interface of the DSPInFPGA Input FPGAMcBSP Multi channels Buffered Serial Port of the DSPOutFPGA Output FPGARADD Read address in the SCA (Switch Capacitors Table)SEU Single Event Upset


http://wwwlapp.in2p3.fr/informatique/Atlas_online/Documents/Dsp/ATL-ROD-RTX/AOS_ATL-SYNC-ANA.pdf

http://wwwlapp.in2p3.fr/informatique/Atlas_online/Documents/Dsp/ATL-ROD-RTX/AOS_ATL-SYNC-ANA.pdf

http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Testbench/ROD_Testbench.pdf

http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod_ttc_fpga/TTC_FPGA.pdf

http://wwwlapp.in2p3.fr/Electronique/Experiences/ATLAS-ELEC/Rod/Document/HPI.pdf

8 ANNEXES

8.1 Annexe 1 : ADC Read out input event format

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0W1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1W2 0 P 0 0 ADCID PHASE EVENTNW3 0 P 0 0 BCIDW4 0 P 0 0 F L B A CELLNW5 0 P Gain ADC channel 1 sample 1W6 0 P Gain ADC channel 2 sample 1W7 0 P Gain ADC channel 3 sample 1W8 0 P Gain ADC channel 4 sample 1W9 0 P Gain ADC channel 5 sample 1W10 0 P Gain ADC channel 6 sample 1W11 0 P Gain ADC channel 7 sample 1W12 0 P Gain ADC channel 8 sample 1

... ...

... ...WEVT-10 0 P 0 0 F L B A CELLNWEVT-9 0 P Gain ADC channel 1 last sample

... ...WEVT-2 0 P Gain ADC channel 8 last sampleWEVT-1 0 P 0 0 1 S E SCAC status 1WEVT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

W1 : frame start tag

W2 & W3 : event headerADCID : The ADC IDentifier.PHASE : Bits encoding the phase of the 5MHz rclk at the time of the trigger.EVENTN : Event number.BCID : Bunch Counter IDentifier.

W4 WEVT-2 : Sample data W4 : first sample header also called RADD

F : First sample of event, send event header, and perform gain selection algorithm (if in auto gain mode).

L : Last sample of an event, send event status, and delay further samples to make room for the event header of next event.

B : Backporch bit. Do not raise the gain for any channel in auto-gain mode. A : Test mode bit.CELLN : The SCA cell (capacitor) number.

From W5 to W12 : first sample dataGain : - 00 test data.

- 01 low gain.- 10 medium gain.- 11 high gain.

ADC : ADC data WEVT-10 : last sample header

From WEVT-9 to WEVT-2 : last sample data


WEVT-1 : event trailerB11 & B0 : forced high.S : Single bit errors in EDC (Error Detection & Correction) unit.E : Double bit errors in EDC unit.SCA Controller status :

B8 : SEU in the latency’s redundant MSB’s.B7 : done_fifo overflow.B6 : free_fifo Underrun The SCA run out of free cells. Invalid cell numbers were inserted into

the sequence.

B5 : Sequence error : The free_fifo emitted the same cell number twice in a row.B4 : Single bit error : a cell address was found with a single bit error. This error was corrected.B3 : Double bit error. A cell address was found with two bits in error. This bit will reoccur

repeatedly, since the error will not be corrected.B2 : BCID reset. The BCID counter was reset.B1 : Init. Bit set in the first event after initialisation.

WEVT : frame end tag

For all words except the frame start/end tagB14 : odd parity on bit 0-13, 15.Note : the parity bit is set to 0 or 1 in order to always have an odd number of ones in the 16 bits word ;

that way it is impossible to have a “frame end tag” in an event.

8.2 Annexe 2 : Schematics, routing and placement
