dsp processors
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DSP Processors. Digital Signal Processors. Group #13. Outlines. DSP processors Architecture Data handling Program flow Programming Applications. Outlines. DSP processors Architecture Data handling Program flow Programming Applications. DSP processors. - PowerPoint PPT PresentationTRANSCRIPT
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DSP ProcessorsDigital Signal Processors
4\3\2012
Group#13
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
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A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing. ◦ DSP is the application of mathematical operations to digitally represent
signals.
The source of these signals can be
◦ Audio
◦ Image
DSP processors
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Digital signal processing enjoys several advantages over analog signal processing:
◦ DSP systems are able to accomplish tasks inexpensively that would be difficult or even impossible using analog electronics. (Examples of such applications include speech synthesis and speech recognition).
◦ Insensitivity to environment.◦ Insensitivity to component tolerances. ◦ Repeatable behavior.◦ Re-programmability.◦ Size.
DSP processors
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◦ Arithmetic and Multiplication (add, subtract, increment, decrement, negate, round,
absolute value) and multiplication. With the exception of the Texas Instruments TMS320Clx
processor provide multiply-accumulate instructions as well.
◦ Logic Operations and, or, exclusive-or, and not.
◦ Shifting Arithmetic (left and right). Logical (left and right).
Instruction types
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◦ Rotation Left. Right.
◦ Comparison Most processors provide a set of status bits (ex: zero-Bit,
minus Bit and overflow Bit) that provide information about the results of arithmetic operations.
used in conditional branches or conditional execution instructions.
◦ Looping
◦ Subroutine Calls may be called jump-to-subroutine instructions.
Instruction types(Cont.)
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◦ Branching jump or got o instructions on some processors.
Instruction types(Cont.)
ConditionalUn-
conditional
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◦ Branching (cont.)
Instruction types(Cont.)
DelayedMulticycle
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
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Instruction sets
◦ A basic DSP processor supports RISC (Reduce Instruction Set Computers) and CISC (Complex Instruction Set Computers) instructions.
◦ Single instruction, multiple data (SIMD) ◦ Instruction-level parallelism (ILP)
Architecture
Single instruction, multiple data (SIMD) Single instruction, multiple data describes
computers with multiple processing elements that perform the same operation on multiple data simultaneously.
Architecture (cont.)
Instruction-level parallelism (ILP)◦ Instruction-level parallelism (ILP) is a measure of how
many of the operations in a computer program can be performed simultaneously.
◦ Ex: 1. e = a + b 2. f = c + d independent 3. g = e * f
◦ ILP allows the compiler and the processor to overlap the execution of multiple instructions or even to change the order in instructions
Architecture (cont.)
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◦ Transferring information to and from memory includes data, such as samples from the input signal and the filter coefficients, as well as program instructions, the binary codes that go into the program sequencer.
◦ Ex.
Architecture of the Digital Signal Processor
a b×a
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There are mainly three types of architectures employed for the processors:
1. Von Neumann architecture2. Harvard architecture3. Super Harvard Architecture
Architecture of the DSP(cont.)
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contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU).
For example,
1-Von Neumann architecture
Memory (instruction and
data)CPU
add. bus
data bus
a b×a
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• Advantages:• This type of architecture is cheap, and • Simple to use because the programmer can place
instructions or data anywhere throughout the available memory.
• Disadvantages:• Von Neumann computers spend a lot of time moving
data to and from the memory, and his slows the computer.
1-Von Neumann architecture(cont.)
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Separate memories for data and program instructions, with separate buses for each.
• For example,
2- Harvard architecture
Program Memory
(instruction only)
CPUData
Memory (data only)
PM add. bus
PM data bus
DM add. bus
DM data bus
a b×a
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• Advantages:• Since the buses operate independently, program
instructions and data can be fetched at the same time, improving the speed over the single bus design.
• Disadvantages:• data memory bus is busier than the program memory
bus.
2- Harvard architecture(cont.)
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Improves upon the Harvard design by adding an instruction cache and dedicated I/O controller.
• For example,
3- Super Harvard Architecture
a b×a
Program Memory (instruction and secondary data)
CPU Data Memory
(data only)
I/O Controller
Instruction Cache
PM add. bus
PM data bus
DM add. bus
DM data bus
Data
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• Advantages:• the instruction cache improves the performance of the
Harvard architecture.• I/O controller connected to data memory this dedicated
hardware allows the data streams to be transferred directly into memory without having to pass through the CPU's registers.
• Disadvantages:• If we were executing random instructions, this situation
would be no better at all.
3- Super Harvard Architecture (cont.)
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Now let's look inside the CPU
Architecture of the DSP(Cont.)
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At the top of the diagram are two blocks labeled Data Address Generator (DAG), one for each of the two memories.
◦ These control the addresses sent to the program and data memories, specifying where the information is to be read from or written to.
Architecture of the DSP(Cont.)
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The data register section : contains16 general purpose registers of 40 bits each. ◦ These can hold intermediate calculations, ◦ prepare data for the math processor, ◦ serve as a buffer for data transfer, ◦ hold flags for program control.
Architecture of the DSP(Cont.)
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The math processing is broken into three sections,◦ a multiplier (MAC), ◦ an arithmetic logic unit (ALU), and ◦ a shifter.
Architecture of the DSP(Cont.)
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
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DSP processors fall into two major categories based on the way they represent numerical values and implement numerical operations internally.
Data handling
Fixed PointFloating Point
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Floating point◦ Floating point processors primarily represent numbers in
floating point format.
◦ Advantages: Easier to develop code.. The large dynamic range available means that dynamic range
limitations can be practically ignored in a design.
◦ Disadvantages: More expensive because they implement more functionality
(complexity )in silicon and have wider buses (32 bit).
Data handling (Cont.)
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Fixed point◦ Fixed point processors represent and manipulate numbers
as integers.
◦ Advantages: lower cost and higher speed
◦ Disadvantages: Added design effort for algorithm implementation analysis, and
data and Coefficient scaling to avoid accumulator overflow (16-20-24 bit).
Data handling (Cont.)
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Let’s take an example:
FIR filters (Finite Impulse Response)
y[n]=b0 x[n] + b1 x[n-1] + b2 x[n-2] + ……. + bN x[n-N]
Structurally, FIR filters consist of just two things: ◦ a sample delay line and ◦ a set of coefficients.
Data handling (Cont.)
RoundOr
Truncate(at fixed point)
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
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Pipelined
Hardware-controlled looping
Program flow
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Pipelined
Hardware-controlled looping
Program flow
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A pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one.
Instruction pipelines, used in processors to allow overlapping execution of multiple instructions.
Pipelined
Fetch
Decode
Execute
Fetch ‘A’
• 2nd CLK Cycle
Fetch ‘B’
Decode ‘A’
• 3rd CLK Cycle
Fetch ‘C’
Execute‘A’
Decode ‘B’
• 1st CLK Cycle
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1st Approach◦ Each clock cycle = 20ns◦ One instruction = 80 ns◦ each stage of instruction execution is idle 75 % of the
time.
Pipelined (cont.)
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2nd Approach◦ One instruction is now completed every clock cycle
(every 20 ns)
Pipelined (cont.)
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Pipelined
Hardware-controlled looping
Program flow
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DSP algorithms frequently involve the repetitive execution of a small number of instructions (ex: FIR and IIR filters, FFTs and matrix multiplication)
DSP processors have evolved to include features to efficiently handle this sort of repeated execution.
Hardware-controlled looping
MOV #16,B LOOP : MAC (R0)+,(R4+),A DEC B JNE LOOP
RPT #16 MAC (R0)+,(R4+),A
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
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Most DSPs are programmed in special versions of C.
DSP vendors will almost always provide support for C++ programming, but it is not very popular in the DSP software industry.
Some DSP software programmers will resort to assembly programming for DSPs.
Programming
DSP processors ◦ Architecture◦ Data handling◦ Program flow ◦ Programming ◦ Applications
Outlines
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Digital cameras.
Digital radios.
High-resolution printers.
Satellites.
Applications
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