1 1 The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

ESA DSP DAY

ESA/ESTEC Noordwijk, August 28th 2012

DSPACE Project Introduction

and Core Architecture

Walter Errico

SITAEL S.p.A.

Phone: +39 050 9912116

E-mail: walter.errico@sitael.com

URL - http://www.sitael.com

2 2

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Outline

Project Overview

Design Approach

Core Architecture

Conclusion

3 3

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

EU FP7 Research Project

o 2 years duration: July 2011 – July 2013

o Total budget: 1.6 M€

DSPACE Consortium:

o SITAEL (project coordinator)

o RWTH Aachen University

o Consorzio Pisa Ricerche

o INTECS

o Space Applications Services

DSPACE Project

4 4

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Higher DSP performance required for feasibility of new space missions:

o Earth Observation missions (e.g. processing of IR sounder and SAR instruments data)

o Science and Robotic Exploration missions (e.g. optical navigation for descent and landing; camera image compression)

o Telecom applications

European strategic non-dependence for critical technologies

Key requirements for next generation space DSP:

o Processing power ≥ 1 GFLOPS

o Radiation hardness (TID > 100 Krad) and protected memories (EDAC)

o Space standard I/O interfaces

o High quality SW Development

Requirements

5 5

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

DSP synthetisable VHDL core for space applications

o TMR

o EDAC

o Synchronous/Asynchronous reset

o Optional low power support with clock gating

Software Development Environment including:

o Optimized ‘C’ compiler chain

o Instruction Level Simulator

o SW debugger

Benchmark Core validation

Objectives

6 6

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Outline

Project Overview

Design Approach

Core Architecture

Conclusion

7 7

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

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The most demanding task of a new (Digital Signal) Processor development is the design and the debugging, of its compilation chain.

Such effort was not compatible with the DSPACE project budged.

Design approach

Two expedients to manage the SW impact:

1. The exploitation of LISA methodology to automatically generate part of the SDK (assembly, linker, instruction Level Simulator ..).

2. The reuse of existing compilation chain tools combining them with a low level glue SW layer and code optimizer.

SoftWare

Development

Environment

HardWare

device

8 8

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

HW design

o Architecture definition

o VHDL Core finalization

o Demo Board

SW Design

o Glue Layer

o Code Optimizer

o Benchmarks

Reuse

o LISA VHDL, ILS, Assembler

o Open-Source DSP optimized ‘C’ compiler

DSPACE activities

SoftWare

Development

Environment

Space DSPCore

Code Optimizer

Benchmarks

Ground

DSP

Glue Layer &

9 9

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Adoption of ESA DSP SW benchmarks specification

“Next Generation Space Digital Signal Processor Software Benchmark,

TEC-EDP/2008.18/RT, December 2008”

Application-oriented benchmarks

Main kernel algorithms:

o FIR filters, FFTs

o Standard CCSDS Lossless Data Compression, Image Data Compression

Benchmark code development in C and Assembly (for filters and FFTs)

Execution for performance measurement on:

o Cycle Accurate Simulator

o FPGA demonstrator board

Benchmarks

10 10

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Outline

Project Overview

Design Approach

Core Architecture

Conclusion

11 11

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

DSPACE Architecture

Data Processing Unit

Program Flow ControllerFetch

Decode & DispatchControl & Status

Registers

Instruction Cache

FPALU

FPALU

FPMUL

AGUFP

ALUFP

ALUFP

MULAGU

Data Cache

Register File

AP

B M

stMem

ory

Co

ntr

olle

r

Co

ntr

ol

Logi

c

DM

AA

PB

Slv

APB Slv

AMB Mst

SpWR_1

APB Slv

AMB Mst

SpWR_2

APB Slv

APB Slv

Cnt Bus

Instr Bus

Data Bus

AHB Bus

APB Bus

DSPACE SoC

DMA bus

DDR2 Memory

12 12

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Building Blocks

VLIW 8 slot data processing unit

Instruction Cache, 32 Kbyte + EDAC

Data Cache , 64 Kbyte + EDAC

DMA

Memory controller for 72 bit ECC DDR2

SpW-RMAP Communication modules

AHB/APB bus

13 13

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Data Processing Unit

8 slot VLIW with predicated execution

parallel functional units:

o 4 FP ALUs

o 2 FP MUL units

o 2 AGUs

64 x 32-bit Register File

Data formats:

o 32-bit fixed-point

o 32-bit (IEEE 754 single precision) floating-point

Data Processing Unit

Program Flow ControllerFetch

Decode & DispatchControl & Status

Registers

Instruction Cache

FPALU

FPALU

FPMUL

AGUFP

ALUFP

ALUFP

MULAGU

Data Cache

Register File

14 14

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Three Different Functional Units

Functional Unit Instruction Functionality

FPMUL: Integer and single precision FP Multiplier unit

• 32x32-bit multiply • Single-precision floating point multiplication • 16 x 16bit multiply

FPALU: Integer and single precision FP Arithmetic Logic Unit

• 32-bit logical operations • 32-bit arithmetic operations • 32-bit compare operations • 32-bit bit-field operations • 32-bit shift • Min/Max operations • Bit reversal • Trailing bit count • Single-precision floating point compare • Single-precision floating point arithmetic operations • Min/Max floating point operations • Integer / floating point conversion • Branch • Interrupt Handling • Control register transfers to/from register file • Input / Output transfer to/from external peripherals (I/O Space)

AGU: Integer Address Generation Unit

• Load and store bytes, half-words, words and double-words • 32-bit add and sub in linear or circular address calculation • Load and store with 5-bit and 15-bit constant offset using 18 different addressing option

(base + register with address post/pre modify)

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ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

DPU Pipeline sr

cA

srcB

dst

Register File

(R0-R31)

op

A

op

B

res

FPALU1

op

A

op

B

res

FPALU2

op

A

op

B

res

FPMUL

op

A

op

B

res

AGUo

pA

op

B

res

FPALU1

op

A

op

B

res

FPALU2

op

A

op

B

res

FPMUL

op

A

op

B

res

AGU

Decode Barrier

Exec Barrier

LP1

_op

A

LP1

_op

B

LP2

_op

A

LP2

_op

B

MP

_op

A

MP

_op

B

AP

_op

A

AP

_op

B

LP1

_op

A

LP1

_op

B

LP2

_op

A

LP2

_op

B

MP

_op

A

MP

_op

B

AP

_op

A

AP

_op

B

Write Back Barrier

LP1_res LP2_res MP_res AP_res LP1_res LP2_res MP_res AP_res

srcA

srcB

dst

srcA

srcB

dst

srcA

srcB

dst

srcA

srcB

dst

srcA

srcB

dst

srcA

srcB

dst

srcA

srcB

dst

LD

ST

LD

ST

5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4

64

32

64

32

32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

32 32 32 32 32323232

DispatchBarrier

Co

de

256

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Dispatch Network

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

Inst

r

32

16 16

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

DPU Pipeline

Simple and scholastic HW architecture

o Strictly pipelined VLIW structure

o No dynamic instruction schedule, no stall management

o Delayed branch

o The same latency for all instructions except than LOAD/STORE/JMP

HW specification early frozen to allow the full SW/HW integration

HW optimization/enhancements are postponed:

o Data forwarding (Register File by-pass)

o Instruction Multi-latency

o Complex operands support

o …

17 17

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Target Technologies and Performances

• DSPACE design will incorporate radiation-hardening-by-design techniques (EDAC protection of on-chip and off-chip memories, TMR on registers)

• Atmel ATC18RHA

– currently available, space-qualified 180 nm ASIC technology

expected DSP performance: 750 MFLOPS (peak) @ 125 MHz

• ST Microelectronics DSM65

– new space-qualified 65 nm ASIC technology (NDA signed)

expected DSP performance ≥ 1 GFLOPS

• Xilinx Virtex5-QV XQR5VFX130 FPGA

– It is the only space-qualified FPGA compatible with DSPACE features

– A Larger Kintex7 XC7K160T/XC7K325T device has been selected for the demonstrator board

18 18

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

DSPACE Demonstrator Board

• Compact PCI 3U + mezzanine communication board

• Xilinx Kintex7 FPGA

• In C-PCI crates or as a standalone desktop board (with case and power adapter)

• Will be used in test and validation activities

SRAM

SRAM

SRAM

SRAM

DDRAM

DDRAM

DDRAM

DDRAMXilinxFPGA

Power Supply

FLASH

SRAM

MIL1553

SpW

USB/ETH to Serial

Co

mp

act-

PC

I

CAN Bus

Preliminary board layout

19 19

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Outline

Project Overview

Design Approach

Core Architecture

Conclusion

20 20

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

DSPACE project aims to realize the core for a Space 1 GFLOPs DSP component providing it with a complete and reliable SDE.

The VHDL core is complete and under test.

Simple ‘C’ programs and Assembly test are running on the Instruction Level Simulator.

Schedule

o Demo board for FPGA emulation is planned in Q4 2012

o Complete C compiler chain: Q1 2013

o HW/SW test and benchmarking Q2 2013

o Evaluation Kit based on ILS can be released to Beta-Tester in Q1 2013

Conclusions

21 21

ESA DSP DAY, DSPACE Project Introduction

The research leading to these results has received funding from the European Community's Seventh Framework Programme ([FP7/2007-2013]) under Grant Agreement n°262798

This document is the property of SITAEL S.p.A. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

.

Thank you for your attention!

Walter Errico Design Responsible

phone: +39 050 9912116

e-mail: walter.errico@sitael.com

SITAEL S.p.A. Via Livornese 1019

56122 Pisa - San Piero a Grado (PI) ITALY

www.sitael.com