dspic33fj32mc302

2009 Microchip Technology Inc. Preliminary DS70291C

dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, and

dsPIC33FJ128MCX02/X04Data Sheet

High-Performance,16-bit Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breacher ou of in

rned

r cane.

mitteay b

workInformation contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,

knowledge, require using the Microchip products in a mannSheets. Most likely, the person doing so is engaged in theft

Microchip is willing to work with the customer who is conce

Neither Microchip nor any other semiconductor manufacturemean that we are guaranteeing the product as unbreakabl

Code protection is constantly evolving. We at Microchip are comproducts. Attempts to break Microchips code protection feature mallow unauthorized access to your software or other copyrightedDS70291C-page ii Prelimin

suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial

the code protection feature. All of these methods, to our tside the operating specifications contained in Microchips Data tellectual property.

about the integrity of their code.

guarantee the security of their code. Code protection does not

d to continuously improving the code protection features of oure a violation of the Digital Millennium Copyright Act. If such acts, you may have a right to sue for relief under that Act.ary 2009 Microchip Technology Inc.

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, AND

dsPIC33FJ128MCX02/X04

Operating Range: Up to 40 MIPS operation (at 3.0V -3.6V):

- Industrial temperature range (-40C to +85C)

- Extended temperature range (-40C to +125C)

High-Performance DSC CPU: Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M

instruction words Linear data memory addressing up to 64 Kbytes 83 base instructions: mostly 1 word/1 cycle Two 40-bit accumulators with rounding and

saturation options Flexible and powerful addressing modes:

- Indirect- Modulo- Bit-Reversed

Software stack 16 x 16 fractional/integer multiply operations 32/16 and 16/16 divide operations Single-cycle multiply and accumulate:

- Accumulator write back for DSP operations- Dual data fetch

Up to 16-bit shifts for up to 40-bit data

Direct Memory Access (DMA): 8-channel hardware DMA Up to 2 Kbytes dual ported DMA buffer area (DMA

RAM) to store data transferred via DMA:- Allows data transfer between RAM and a

peripheral while CPU is executing code (no

Timers/Capture/Compare/PWM: Timer/Counters, up to five 16-bit timers:

- Can pair up to make two 32-bit timers- One timer runs as a Real-Time Clock with an

external 32.768 kHz oscillator- Programmable prescaler

Input Capture (up to four channels):- Capture on up, down or both edges- 16-bit capture input functions- 4-deep FIFO on each capture

Output Compare (up to four channels):- Single or Dual 16-bit Compare mode- 16-bit Glitchless PWM mode

Hardware Real-Time Clock/Calendar (RTCC):- Provides clock, calendar, and alarm functions

Interrupt Controller: 5-cycle latency Up to 53 available interrupt sources Up to three external interrupts Seven programmable priority levels Five processor exceptions

Digital I/O: Peripheral pin Select functionality Up to 35 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 31 pins Output pins can drive from 3.0V to 3.6V Up to 5V output with open drain configuration All digital input pins are 5V tolerant 4 mA sink on all I/O pins

On-Chip Flash and SRAM: Flash program memory (up to 128 Kbytes) Data SRAM (up to 16 Kbytes)

High-Performance, 16-bit Digital Signal Controllers 2009 Microchip Technology Inc. Preliminary DS70291C-page 1

cycle stealing) Most peripherals support DMA

Boot, Secure, and General Security for program Flash

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04System Management: Flexible clock options:

- External, crystal, resonator, internal RC- Fully integrated Phase-Locked Loop (PLL)- Extremely low jitter PLL

Power-up Timer Oscillator Start-up Timer/Stabilizer Watchdog Timer with its own RC oscillator Fail-Safe Clock Monitor Reset by multiple sources

Power Management: On-chip 2.5V voltage regulator Switch between clock sources in real time Idle, Sleep, and Doze modes with fast wake-up

Analog-to-Digital Converters (ADCs): 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:

- Two and four simultaneous samples (10-bit ADC)- Up to nine input channels with auto-scanning- Conversion start can be manual or

synchronized with one of four trigger sources- Conversion possible in Sleep mode- 2 LSb max integral nonlinearity- 1 LSb max differential nonlinearity

Audio Digital-to-Analog Converter (DAC):- 16-bit Dual Channel DAC module- 100 Ksps maximum sampling rate- Second-Order Digital Delta-Sigma Modulator

Comparator Module: Two analog comparators with programmable

input/output configuration

CMOS Flash Technology: Low-power, high-speed Flash technology Fully static design 3.3V (10%) operating voltage Industrial and Extended temperature Low power consumption

Motor Control Peripherals: 6-channel 16-bit Motor Control PWM:

- Three duty cycle generators- Independent or Complementary mode- Programmable dead-time and output polarity- Edge-aligned or center-aligned- Manual output override control- One Fault input- Trigger for ADC conversions- PWM frequency for 16-bit resolution

(@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode

- PWM frequency for 11-bit resolution(@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode

2-channel 16-bit Motor Control PWM:- One duty cycle generator- Independent or Complementary mode- Programmable dead time and output polarity- Edge-aligned or center-aligned- Manual output override control- One Fault input- Trigger for ADC conversions- PWM frequency for 16-bit resolution

(@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode

- PWM frequency for 11-bit resolution(@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode

2-Quadrature Encoder Interface module:- Phase A, Phase B, and index pulse input- 16-bit up/down position counter- Count direction status- Position Measurement (x2 and x4) mode- Programmable digital noise filters on inputs- Alternate 16-bit Timer/Counter mode- Interrupt on position counter rollover/underflowDS70291C-page 2 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04Communication Modules: 4-wire SPI (up to two modules):

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data- Supports all serial clock formats and

sampling modes I2C:

- Full Multi-Master Slave mode support- 7-bit and 10-bit addressing- Bus collision detection and arbitration- Integrated signal conditioning- Slave address masking

UART (up to two modules):- Interrupt on address bit detect- Interrupt on UART error- Wake-up on Start bit from Sleep mode- 4-character TX and RX FIFO buffers- LIN bus support- IrDA encoding and decoding in hardware- High-Speed Baud mode- Hardware Flow Control with CTS and RTS

Enhanced CAN (ECAN module) 2.0B active:- Up to eight transmit and up to 32 receive buffers- 16 receive filters and three masks- Loopback, Listen Only and Listen All- Messages modes for diagnostics and bus

monitoring- Wake-up on CAN message- Automatic processing of Remote

Transmission Requests- FIFO mode using DMA- DeviceNet addressing support

Parallel Master Slave Port (PMP/EPSP):- Supports 8-bit or 16-bit data- Supports 16 address lines

Programmable Cyclic Redundancy Check (CRC):- Programmable bit length for the CRC

generator polynomial (up to 16-bit length)- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data

input

Packaging: 28-pin SDIP/SOIC/QFN-S 44-pin TQFP/QFN

Note: See the device variant table for exactperipheral features per device. 2009 Microchip Technology Inc. Preliminary DS70291C-page 3

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04 PRODUCT FAMILIESThe device names, pin counts, memory sizes, andperipheral availability of each device are listed below.The following pages show their pinout diagrams.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Controller Families

Device

Pins

Prog

ram

Fla

sh M

emor

y (K

byte

)

RA

M (K

byte

)(1)

Remappable Peripheral

RTC

C

I2C

C

RC

Gen

erat

or

10-b

it/12

-bit

AD

C(C

hann

els)

6-pi

n 16

-bit

DA

C

Ana

log

Com

para

tor

(2 C

hann

els/

Volta

ge R

egul

ator

)

I/O P

ins

Pack

ages

Rem

appa

ble

Pins

16-b

it Ti

mer

(2)

Inpu

t Cap

ture

Out

put C

ompa

reSt

anda

rd P

WM

Mot

or C

ontr

ol P

WM

(Cha

nnel

s)(3

)

Qua

drat

ure

Enco

der

Inte

rfac

e

UA

RT

SPI

ECA

N

Exte

rnal

Inte

rrup

ts(4

)

8-b

it Pa

ralle

l Mas

ter

Port

(Add

ress

Lin

es)

dsPIC33FJ128MC804 44 128 16 26 5 4 4 6, 2 2 2 2 1 3 1 1 1 9 1 1/1 11 35 QFNTQFP

dsPIC33FJ128MC802 28 128 16 16 5 4 4 6, 2 2 2 2 1 3 1 1 1 6 0 1/0 2 21 SDIPSOIC

QFN-S



QFN-S



QFN-S



QFN-S



QFN-SNote 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32MC302/304, which include 1 Kbyte of DMA RAM.

2: Only four out of five timers are remappable. 3: Only PWM fault pins are remappable.4: Only two out of three interrupts are remappable.DS70291C-page 4 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04Pin Diagrams

dsPIC33FJ32M

C302

1

2

345

678

91011121314

28

27

262524

232221

201918171615

28-Pin SDIP, SOICAVDDAVSS

PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6

VSSVCAP/VDDCORE

INT0/RP7(1)/CN23/PMD5/RB7

TDO/PWM2L1/SDA1/RP9(1)/CN21/PMD3/RB9TCK/PWM2H1/SCL1/RP8(1)/CN22/PMD4/RB8

PWM1L1/RP15(1)/CN11/PMCS1/RB15PWM1H1/RTCC/RP14(1)/CN12/PMWR/RB14PWM1L2/RP13(1)/CN13/PMRD/RB13PWM1H2/RP12(1)/CN14/PMD0/RB12

PGED2/TDI/PWM1H3/RP10(1)/CN16/PMD2/RB10PGEC2/TMS/PWM1L3/RP11(1)/CN15/PMD1/RB11

MCLR

VSS

VDD

AN0/VREF+/CN2/RA0AN1/VREF-/CN3/RA1

PGED1/AN2/C2IN-/RP0(1)/CN4/RB0

SOSCO/T1CK/CN0/PMA1/RA4SOSCI/RP4(1)/CN1/PMBE/RB4OSC2/CLKO/CN29/PMA0/RA3

OSC1/CLKI/CN30/RA2

AN5/C1IN+/RP3(1)/CN7/RB3AN4/C1IN-/RP2(1)/CN6/RB2

PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1

PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5

dsPIC33FJ64M

C202

dsPIC33FJ64M

C802

dsPIC33FJ128M

C202

dsPIC33FJ128M

C802

28-Pin QFN-S(2)

dsPIC33FJ128MC202

23

6

1

18192021

22

1571617

232425262 728

54

MC

LR

VSS

VD

DA

N0/

VRE

F+/C

N2/

RA

0A

N1/

VRE

F-/C

N3/

RA

1

AVD

D

AVS

S

PGED1/AN2/C2IN-/RP0(1)/CN4/RB0

PG

EC

3//A

SC

L1/R

P6(

1)/C

N24

/PM

D6/

RB6

SOS

CO

/T1C

K/C

N0/

PM

A1/

RA4

SO

SCI/R

P4(

1)/C

N1/

PM

BE/

RB4

VSSOSC2/CLKO/CN29/PMA0/RA3

OSC1/CLKI/CN30/RA2VCAP/VDDCORE

INT0

/RP

7(1)

/CN

23/P

MD

5/R

B7

TDO/PWM2L1/SDA1/RP9(1)/CN21/PMD3/RB9

TCK

/PW

M2H

1/S

CL1

/RP

8(1)

/CN

22/P

MD

4/R

B8

AN5/C1IN+/RP3(1)/CN7/RB3AN4/C1IN-/RP2(1)/CN6/RB2

PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1

PW

M1L

1/R

P15

(1) /C

N11

/PM

CS

1/R

B15

PW

M1H

1/R

TCC

/RP

14(1

) /CN

12/P

MW

R/R

B14

PWM1L2/RP13(1)/CN13/PMRD/RB13PWM1H2/RP12(1)/CN14/PMD0/RB12

PGED2/TDI/PWM1H3/RP10(1)/CN16/PMD2/RB10PGEC2/TMS/PWM1L3/RP11(1)/CN15/PMD1/RB11

PG

ED3/

ASD

A1/

RP

5(1)

/CN

27/P

MD

7/R

B5

dsPIC33FJ64MC202dsPIC33FJ64MC802

dsPIC33FJ128MC802

dsPIC33FJ32MC302

14131 21 11098

Note 1: The RPx pins can be used by any remappable peripheral. See the table dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,and dsPIC33FJ128MCX02/X04 Controller Families in this section for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

= Pins are up to 5V tolerant

= Pins are up to 5V tolerant 2009 Microchip Technology Inc. Preliminary DS70291C-page 5

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04Pin Diagrams (Continued)

44-Pin QFN(2)

dsPIC33FJ64MC80444434241403938373635

12131415161718192021

33029282726252423

45

7891011

1232

31

6

22

33 34PG

EC

1/A

N3/

C2I

N+/

RP1

(1) /C

N5/

RB1

PGE

D1/

AN

2/C

2IN

-/RP0

(1) /C

N4/

RB0

AN1/

VRE

F-/C

N3/

RA

1AN

0/VR

EF+

/CN

2/R

A0

MC

LR

TMS

/PM

A10/

RA

10

AVD

DAV

SS

PWM

1L1/

DA

C1L

N/R

P15

(1) /C

N11

/PM

CS1

/RB1

5PW

M1H

1/D

AC1L

P/R

TCC

/RP1

4(1)

/CN

12/P

MW

R/R

B14

TCK

/PM

A7/R

A7S

CL1

/RP

8(1)

/CN

22/P

MD

4/R

B8

INT0

/RP

7(1)

/CN

23/P

MD

5/R

B7

PG

EC3/

ASC

L1/R

P6(

1)/C

N24

/PM

D6/

RB

6P

GED

3/AS

DA

1/R

P5(

1)/C

N27

/PM

D7/

RB

5V

DD

TDI/P

MA

9/R

A9

SO

SCO

/T1C

K/C

N0/

RA

4

VS

SR

P21

(1) /C

N26

/PM

A3/

RC

5R

P20

(1) /C

N25

/PM

A4/

RC

4R

P19

(1) /C

N28

/PM

BE/R

C3

PWM1H2/DAC1RP/RP12(1)/CN14/PMD0/RB12PGEC2/PWM1L3/RP11(1)/CN15/PMD1/RB11PGED2/PWM1H3/RP10(1)/CN16/PMD2/RB10VCAP/VDDCOREVSSRP25(1)/CN19/PMA6/RC9RP24(1)/CN20/PMA5/RC8PWM2L1/RP23(1)/CN17/PMA0/RC7PWM2H1/RP22(1)/CN18/PMA1/RC6SDA1/RP9(1)/CN21/PMD3/RB9

PWM1L2/DAC1RN/RP13(1)/CN13/PMRD/RB13AN4/C1IN-/RP2(1)/CN6/RB2AN5/C1IN+/RP3(1)/CN7/RB3

AN6/DAC1RM/RP16(1)/CN8/RC0AN7/DAC1LM/RP17(1)/CN9/RC1

AN8/CVREF/RP18(1)/PMA2/CN10/RC2

SOSCI/RP4(1)/CN1/RB4

VDDVSS

OSC1/CLKI/CN30/RA2OSC2/CLKO/CN29/RA3

TDO/PMA8/RA8

dsPIC33FJ128MC804



= Pins are up to 5V tolerant DS70291C-page 6 Preliminary 2009 Microchip Technology Inc.


44-Pin QFN(2)

dsPIC33FJ64MC204

44434241403938373635

12131415161718192021

33029282726252423

45

78910

11

1232

31

6

22

33 34P

GEC

1/A

N3/

C2I

N+/

RP

1(1)

/CN

5/R

B1

PG

ED1/

AN

2/C

2IN

-/RP

0(1)

/CN

4/R

B0

AN

1/VR

EF-

/CN

3/R

A1A

N0/

VRE

F+/C

N2/

RA0

MC

LR

TMS

/PM

A10

/RA

10

AVD

DAV

SS

PW

M1L

1/R

P15(

1)/C

N11

/PM

CS

1/R

B15

PW

M1H

1/R

TCC

/RP1

4(1)

/CN

12/P

MW

R/R

B14

TCK/

PMA

7/R

A7

SC

L1/R

P8(1

) /CN

22/P

MD

4/R

B8

INT0

/RP

7(1)

/CN

23/P

MD

5/R

B7

PG

EC

3/A

SC

L1/R

P6(1

) /CN

24/P

MD

6/R

B6

PG

ED

3/A

SD

A1/R

P5(1

) /CN

27/P

MD

7/R

B5

VDD

TDI/P

MA

9/R

A9

SOS

CO

/T1C

K/C

N0/

RA

4

VS

SR

P21

(1) /C

N26

/PM

A3/

RC

5R

P20

(1) /C

N25

/PM

A4/

RC

4R

P19

(1) /C

N28

/PM

BE/

RC

3PWM1H2/RP12(1)/CN14/PMD0/RB12PGEC2/PWM1L3/RP11(1)/CN15/PMD1/RB11PGED2/PWM1H3/RP10(1)/CN16/PMD2/RB10VCAP/VDDCOREVSSRP25(1)/CN19/PMA6/RC9RP24(1)/CN20/PMA5/RC8PWM2L1/RP23(1)/CN17/PMA0/RC7PWM2H1/RP2(1)2/CN18/PMA1/RC6SDA1/RP9(1)/CN21/PMD3/RB9

PWM1L2/RP13(1)/CN13/PMRD/RB13AN4/C1IN-/RP2(1)/CN6/RB2AN5/C1IN+/RP3(1)/CN7/RB3

AN6/RP16(1)/CN8/RC0AN7/RP17(1)/CN9/RC1



VDDVSS


TDO/PMA8/RA8

dsPIC33FJ32MC304

dsPIC33FJ128MC204





44-Pin TQFP

1011

23456

1

1819202122 12131415

38

87

4443424140391617

2930313233

232425262728

3634 35

9

37

SCL1

/RP

8(1)

/CN

22/P

MD

4/R

B8

INT0

/RP

7(1)

/CN

23/P

MD

5/R

B7

PG

EC3/

ASC

L1/R

P6(

1)/C

N24

/PM

D6/

RB6

PG

ED3/

ASD

A1/

RP

5(1)

/CN

27/P

MD

7/R

B5V

DD

TDI/P

MA

9/R

A9

SO

SC

O/T

1CK/

CN

0/R

A4

VSS

RP2

1(1)

/CN

26/P

MA3

/RC

5R

P20(

1)/C

N25

/PM

A4/R

C4

RP1

9(1)

/CN

28/P

MB

E/R

C3

PG

EC

1/A

N3/

C2I

N+/

RP

1(1)

/CN

5/R

B1

PG

ED

1/A

N2/

C2I

N-/R

P0(1

) /CN

4/R

B0A

N1/

VRE

F-/C

N3/

RA

1A

N0/

VRE

F+/C

N2/

RA

0M

CLR

TMS

/PM

A10

/RA1

0

AVD

DAV

SS

PW

M1L

1/D

AC

1LN

/RP

15(1

) /CN

11/P

MC

S1/

RB1

5 P

WM

1H1/

DA

C1L

P/R

TCC

/RP1

4(1)

/CN

12/P

MW

R/R

B14

PWM1H2/DAC1RP/RP12(1)/CN14/PMD0/RB12PGEC2/PWM1L3/RP11(1)/CN15/PMD1/RB11PGED2/EMCD2/PWM1H3/RP10(1)/CN16/PMD2/RB10VCAP/VDDCOREVSSRP25(1)/CN19/PMA6/RC9RP24(1)/CN20/PMA5/RC8PWM2L1/RP23(1)/CN17/PMA0/RC7PWM2H1/RP22(1)/CN18/PMA1/RC6SDA1/RP9(1)/CN21/PMD3/RB9

AN4/C1IN-/RP2(1)/CN6/RB2AN5/C1IN+/RP3(1)/CN7/RB3

AN6/DAC1RM/RP16(1)/CN8/RC0AN7/DAC1LM/RP17(1)/CN9/RC1



VDDVSS


TDO/PMA8/RA8

PWM1L2/DAC1RN/RP13(1)/CN13/PMRD/RB13

TCK

/PM

A7/

RA

7dsPIC33FJ64MC804dsPIC33FJ128MC804

Note 1: The RPx pins can be used by any remappable peripheral. See the table dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Controller Families in this section for the list of availableperipherals.

= Pins are up to 5V tolerant DS70291C-page 8 Preliminary 2009 Microchip Technology Inc.


44-Pin TQFP

1011

23456

1

1819202122 12131415

3887

4443424140391617

2930313233

232425262728

3634 35

937

SCL1

/RP

8(1)

/CN

22/P

MD

4/R

B8

INT0

/RP

7(1)

/CN

23/P

MD

5/R

B7

PG

EC3/

ASC

L1/R

P6(

1)/C

N24

/PM

D6/

RB

6P

GED

3/AS

DA

1/R

P5(

1)/C

N27

/PM

D7/

RB

5V

DD

TDI/P

MA

9/R

A9

SO

SCO

/T1C

K/C

N0/

RA

4

VSS

RP2

1(1)

/CN

26/P

MA3

/RC

5R

P20(

1)/C

N25

/PM

A4/R

C4

RP1

9(1)

/CN

28/P

MB

E/R

C3

PG

EC

1/A

N3/

C2I

N+/

RP

1(1)

/CN

5/R

B1

PG

ED

1/A

N2/

C2I

N-/R

P0(1

) /CN

4/R

B0A

N1/

VRE

F-/C

N3/

RA

1A

N0/

VRE

F+/C

N2/

RA

0M

CLR

TMS

/PM

A10

/RA1

0

AVD

DAV

SS

PW

M1L

1/R

P15

(1) /C

N11

/PM

CS

1/R

B15

PW

M1H

1/R

TCC

/RP

14(1

) /CN

12/P

MW

R/R

B14

PWM1H2/RP12(1)/CN14/PMD0/RB12PGEC2/PWM1L3/RP11(1)/CN15/PMD1/RB11PGED2/EMCD2/PWM1H3/RP10(1)/CN16/PMD2/RB10VCAP/VDDCOREVSSRP25(1)/CN19/PMA6/RC9RP24(1)/CN20/PMA5/RC8PWM2L1/RP23(1)/CN17/PMA0/RC7PWM2H1/RP22(1)/CN18/PMA1/RC6SDA1/RP9(1)/CN21/PMD3/RB9

AN4/C1IN-/RP2(1)/CN6/RB2AN5/C1IN+/RP3(1)/CN7/RB3

AN6/RP16(1)/CN8/RC0AN7/RP17(1)/CN9/RC1

AN8/CVREF/RP18/PMA2/CN10/RC2


VDDVSS


TDO/PMA8/RA8

PWM1L2/RP13(1)/CN13/PMRD/RB13

TCK

/PM

A7/

RA

7

dsPIC33FJ32MC304dsPIC33FJ64MC204dsPIC33FJ128MC204

Note 1: The RPx pins can be used by any remappable peripheral. See the table dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Controller Families in this section for the list of availableperipherals.


dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04Table of ContentsdsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Product Families............................................ 41.0 Device Overview ........................................................................................................................................................................ 132.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 193.0 CPU............................................................................................................................................................................................ 234.0 Memory Organization ................................................................................................................................................................. 355.0 Flash Program Memory.............................................................................................................................................................. 716.0 Resets ....................................................................................................................................................................................... 777.0 Interrupt Controller ..................................................................................................................................................................... 858.0 Direct Memory Access (DMA) .................................................................................................................................................. 1279.0 Oscillator Configuration ............................................................................................................................................................ 13910.0 Power-Saving Features............................................................................................................................................................ 15111.0 I/O Ports ................................................................................................................................................................................... 15712.0 Timer1 ...................................................................................................................................................................................... 18913.0 Timer2/3 And TImer4/5 feature ............................................................................................................................................... 19114.0 Input Capture............................................................................................................................................................................ 19715.0 Output Compare....................................................................................................................................................................... 19916.0 Motor Control PWM Module ..................................................................................................................................................... 20317.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 21718.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 22119.0 Inter-Integrated Circuit (I2C) ................................................................................................................................................. 22720.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 23521.0 Enhanced CAN (ECAN) Module........................................................................................................................................... 24122.0 10-bit/12-bit Analog-to-Digital Converter (ADC1) ..................................................................................................................... 26723.0 Audio Digital-to-Analog Converter (DAC)................................................................................................................................. 28124.0 Comparator Module.................................................................................................................................................................. 28725.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 29326.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 30327.0 Parallel Master Port (PMP)....................................................................................................................................................... 30728.0 Special Features ...................................................................................................................................................................... 31529.0 Instruction Set Summary .......................................................................................................................................................... 32530.0 Development Support............................................................................................................................................................... 33331.0 Electrical Characteristics .......................................................................................................................................................... 33732.0 Packaging Information.............................................................................................................................................................. 383Appendix A: Revision History............................................................................................................................................................. 393Index ................................................................................................................................................................................................. 399The Microchip Web Site ..................................................................................................................................................................... 405Customer Change Notification Service .............................................................................................................................................. 405Customer Support .............................................................................................................................................................................. 405Reader Response .............................................................................................................................................................................. 406Product Identification System............................................................................................................................................................. 407DS70291C-page 10 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our website at www.microchip.com to receive the most current information on all of our products. 2009 Microchip Technology Inc. Preliminary DS70291C-page 11

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04NOTES:DS70291C-page 12 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X041.0 DEVICE OVERVIEW This document contains device specific information forthe dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Digital SignalController (DSC) Devices. The dsPIC33F devicescontain extensive Digital Signal Processor (DSP)functionality with a high performance 16-bitmicrocontroller (MCU) architecture.

Figure 1-1 shows a general block diagram of thecore and peripheral modules in thedsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,and dsPIC33FJ128MCX02/X04 families of devices.Table 1-1 lists the functions of the various pinsshown in the pinout diagrams.

Note: This data sheet summarizes the featuresof dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 families ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the related section of thedsPIC33F Family Reference Manual,which is available from the Microchipwebsite (www.microchip.com) 2009 Microchip Technology Inc. Preliminary DS70291C-page 13

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04FIGURE 1-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04 BLOCK DIAGRAM

16

OSC1/CLKIOSC2/CLKO

VDD, VSS

TimingGeneration

MCLR

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

Brown-outReset

Precision

ReferenceBand Gap

FRC/LPRCOscillators

RegulatorVoltage

VCAP/VDDCORE

IC1, 2, 7, 8 I2C1

PORTA

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features pres-ent on each device.

InstructionDecode and

Control

PCH PCL

16

Program Counter

16-bit ALU

23

23

24

23

Instruction Reg

PCU

16 x 16W Register Array

ROM Latch

16

EA MUX

16

16

8

InterruptController

PSV and TableData AccessControl Block

StackControl Logic

LoopControlLogic

Data Latch

AddressLatch

Address Latch

Program Memory

Data Latch

L

itera

l Dat

a 16 16

16

16

Data Latch

AddressLatch

16

X RAM Y RAM

16

Y Data Bus

X Data Bus

DSP Engine

Divide Support

16

Control Signals to Various Blocks

ADC1Timers

PORTB

Address Generator Units

1-5

CNx

UART1, 2 OC/PWM1-4

QEI1, 2

PWM

2 Ch

PWM6 Ch

RemappablePins

DMARAM

DMAController

PORTC

SPI1, 2

ECAN1

DAC1

Comparator2 Ch.

RTCC

PMP/EPSPDS70291C-page 14 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name PinTypeBufferType PPS Description

AN0-AN8 I Analog No Analog input channels. CLKI

CLKO

I

O

ST/CMOS

No

No

External clock source input. Always associated with OSC1 pin function.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

OSC1

OSC2

I

I/O

ST/CMOS

No

No

Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

SOSCISOSCO

IO

ST/CMOS

NoNo

32.768 kHz low-power oscillator crystal input; CMOS otherwise.32.768 kHz low-power oscillator crystal output.

CN0-CN30 I ST No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.

IC1-IC2IC7-IC8

II

STST

YesYes

Capture inputs 1/2. Capture inputs 7/8.

OCFAOC1-OC4

IO

ST

YesYes

Compare Fault A input (for Compare Channels 1, 2, 3 and 4).Compare outputs 1 through 4.

INT0INT1INT2

III

STSTST

NoYesYes

External interrupt 0.External interrupt 1.External interrupt 2.

RA0-RA4RA7-RA10

I/OI/O

STST

NoNo

PORTA is a bidirectional I/O port.PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.RC0-RC9 I/O ST No PORTC is a bidirectional I/O port.T1CKT2CKT3CKT4CKT5CK

IIIII

STSTSTSTST

NoYesYesYesYes

Timer1 external clock input.Timer2 external clock input.Timer3 external clock input.Timer4 external clock input.Timer5 external clock input.

U1CTSU1RTSU1RXU1TX

IOIO

STST

YesYesYesYes

UART1 clear to send.UART1 ready to send.UART1 receive.UART1 transmit.

U2CTSU2RTSU2RXU2TX

IOIO

STST

YesYesYesYes

UART2 clear to send.UART2 ready to send.UART2 receive.UART2 transmit.

SCK1SDI1SDO1SS1

I/OIOI/O

STSTST

YesYesYesYes

Synchronous serial clock input/output for SPI1.SPI1 data in.SPI1 data out.SPI1 slave synchronization or frame pulse I/O.

SCK2SDI2SDO2SS2

I/OIOI/O

STSTST

YesYesYesYes

Synchronous serial clock input/output for SPI2.SPI2 data in.SPI2 data out.SPI2 slave synchronization or frame pulse I/O.

SCL1SDA1ASCL1ASDA1

I/OI/OI/OI/O

STSTSTST

NoNoNoNo

Synchronous serial clock input/output for I2C1.Synchronous serial data input/output for I2C1.Alternate synchronous serial clock input/output for I2C1.Alternate synchronous serial data input/output for I2C1.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer 2009 Microchip Technology Inc. Preliminary DS70291C-page 15

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04TMSTCKTDITDO

IIIO

STSTST

NoNoNoNo

JTAG Test mode select pin.JTAG test clock input pin.JTAG test data input pin.JTAG test data output pin.

INDX1QEA1

QEB1

UPDN1

II

I

O

STST

ST

CMOS

YesYes

Yes

Yes

Quadrature Encoder Index1 Pulse input.Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer External Clock/Gate input in Timer mode.Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer External Clock/Gate input in Timer mode.Position Up/Down Counter Direction State.

INDX2QEA2

QEB2

UPDN2

II

I

O

STST

ST

CMOS

YesYes

Yes

Yes

Quadrature Encoder Index2 Pulse input.Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer External Clock/Gate input in Timer mode.Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer External Clock/Gate input in Timer mode.Position Up/Down Counter Direction State.

C1RX C1TX

IO

ST

YesYes

ECAN1 bus receive pin.ECAN1 bus transmit pin.

RTCC O No Real-Time Clock Alarm Output.CVREF O ANA No Comparator Voltage Reference Output.C1IN- C1IN+ C1OUT

IIO

ANAANA

NoNoYes

Comparator 1 Negative Input.Comparator 1 Positive Input.Comparator 1 Output.

C2IN- C2IN+ C2OUT

IIO

ANAANA

NoNoYes

Comparator 2 Negative Input.Comparator 2 Positive Input.Comparator 2 Output.

PMA0

PMA1

PMA2 -PMPA10PMBE PMCS1PMD0-PMPD7

PMRDPMWR

I/O

I/O

OOOI/O

OO

TTL/ST

TTL/ST

TTL/ST

No

No

NoNoNoNo

NoNo

Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes).Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes).Parallel Master Port Address (Demultiplexed Master Modes).Parallel Master Port Byte Enable Strobe.Parallel Master Port Chip Select 1 Strobe.Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes).Parallel Master Port Read Strobe.Parallel Master Port Write Strobe.

DAC1RN DAC1RP DAC1RM

OOO

NoNoNo

DAC1 Negative Output.DAC1 Positive Output.DAC1 Output indicating middle point value (typically 1.65V).

DAC2RN DAC2RP DAC2RM

OOO

NoNoNo

DAC2 Negative Output.DAC2 Positive Output.DAC2 Output indicating middle point value (typically 1.65V).

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)


Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input bufferDS70291C-page 16 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04FLTA1PWM1L1PWM1H1PWM1L2PWM1H2PWM1L3PWM1H3FLTA2PWM2L1PWM2H1

IOOOOOOIOO

STST

YesNoNoNoNoNoNoYesNoNo

PWM1 Fault A input.PWM1 Low output 1PWM1 High output 1PWM1 Low output 2PWM1 High output 2PWM1 Low output 3PWM1 High output 3PWM2 Fault A input.PWM2 Low output 1PWM2 High output 1

PGED1PGEC1PGED2PGEC2PGED3PGEC3

I/OI

I/OI

I/OI

STSTSTSTSTST

NoNoNoNoNoNo

Data I/O pin for programming/debugging communication channel 1.Clock input pin for programming/debugging communication channel 1.Data I/O pin for programming/debugging communication channel 2.Clock input pin for programming/debugging communication channel 2.Data I/O pin for programming/debugging communication channel 3.Clock input pin for programming/debugging communication channel 3.

MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.

AVDD P P No Positive supply for analog modules. This pin must be connected at all times.

AVSS P P No Ground reference for analog modules.VDD P No Positive supply for peripheral logic and I/O pins.VCAP/VDDCORE P No CPU logic filter capacitor connection.VSS P No Ground reference for logic and I/O pins.VREF+ I Analog No Analog voltage reference (high) input.VREF- I Analog No Analog voltage reference (low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)


Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer 2009 Microchip Technology Inc. Preliminary DS70291C-page 17

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04NOTES:DS70291C-page 18 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X042.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

2.1 Basic Connection RequirementsGetting started with the dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 family of 16-bit DigitalSignal Controllers (DSC) requires attention to aminimal set of device pin connections beforeproceeding with development. The following is a list ofpin names, which must always be connected:

All VDD and VSS pins (see Section 2.2 Decoupling Capacitors)

All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 Decoupling Capacitors)

VCAP/VDDCORE (see Section 2.3 Capacitor on Internal Voltage Regulator (Vcap/Vddcore))

MCLR pin (see Section 2.4 Master Clear (MCLR) Pin)

PGECx/PGEDx pins used for In-Circuit Serial Programming (ICSP) and debugging purposes (see Section 2.5 ICSP Pins)

OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 External Oscillator Pins)

Additionally, the following pins may be required:

VREF+/VREF- pins used when external voltage reference for ADC module is implemented

2.2 Decoupling CapacitorsThe use of decoupling capacitors on every pair ofpower supply pins, such as VDD, VSS, AVDD, andAVSS is required.

Consider the following criteria when using decouplingcapacitors:

Value and type of capacitor: Recommendation of 0.1 F (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used.

Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F.

Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

Note: This data sheet summarizes the featuresof the dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the dsPIC33F FamilyReference Manual, which is available fromthe Microchip website(www.microchip.com).

Note: The AVDD and AVSS pins must beconnected independent of the ADCvoltage reference source. 2009 Microchip Technology Inc. Preliminary DS70291C-page 19

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION

2.2.1 TANK CAPACITORSOn boards with power traces running longer than sixinches in length, it is suggested to use a tank capacitorfor integrated circuits including DSCs to supply a localpower source. The value of the tank capacitor shouldbe determined based on the trace resistance that con-nects the power supply source to the device, and themaximum current drawn by the device in the applica-tion. In other words, select the tank capacitor so that itmeets the acceptable voltage sag at the device. Typicalvalues range from 4.7 F to 47 F.

2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)

A low-ESR (< 5 Ohms) capacitor is required on theVCAP/VDDCORE pin, which is used to stabilize thevoltage regulator output voltage. The VCAP/VDDCOREpin must not be connected to VDD, and must have acapacitor between 4.7 F and 10 F, 16V connected toground. The type can be ceramic or tantalum. Refer toSection 31.0 Electrical Characteristics foradditional information.

The placement of this capacitor should be close to theVCAP/VDDCORE. It is recommended that the tracelength not exceed one-quarter inch (6 mm). Refer toSection 28.2 On-Chip Voltage Regulator fordetails.

2.4 Master Clear (MCLR) PinThe MCLR pin provides for two specific devicefunctions:

Device Reset Device programming and debugging.

During device programming and debugging, theresistance and capacitance that can be added to thepin must be considered. Device programmers anddebuggers drive the MCLR pin. Consequently,specific voltage levels (VIH and VIL) and fast signaltransitions must not be adversely affected. Therefore,specific values of R and C will need to be adjustedbased on the application and PCB requirements.

For example, as shown in Figure 2-2, it isrecommended that the capacitor C, be isolated fromthe MCLR pin during programming and debuggingoperations.

Place the components shown in Figure 2-2 withinone-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

dsPIC33FV

DD

VS

S

VDD

VSS

VSS

VDD

AVD

D

AVS

S

VD

D

VS

S

0.1 FCeramic

0.1 FCeramic

0.1 FCeramic

0.1 FCeramic

C

R

VDD

MCLR

0.1 FCeramic

VC

AP/V

DD

CO

RE

10

R1

Note 1: R 10 k is recommended. A suggestedstarting value is 10 k. Ensure that theMCLR pin VIH and VIL specifications are met.

2: R1 470 will limit any current flowing intoMCLR from the external capacitor C, in theevent of MCLR pin breakdown, due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS). Ensure that the MCLR pinVIH and VIL specifications are met.

C

R1R

VDD

MCLR

dsPIC33FJPDS70291C-page 20 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X042.5 ICSP PinsThe PGECx and PGEDx pins are used for In-CircuitSerial Programming (ICSP) and debugging pur-poses. It is recommended to keep the trace lengthbetween the ICSP connector and the ICSP pins on thedevice as short as possible. If the ICSP connector isexpected to experience an ESD event, a series resistoris recommended, with the value in the range of a fewtens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes, and capacitors on thePGECx and PGEDx pins are not recommended as theywill interfere with the programmer/debugger communi-cations to the device. If such discrete components arean application requirement, they should be removedfrom the circuit during programming and debugging.Alternatively, refer to the AC/DC characteristics andtiming requirements information in the respectivedevice Flash programming specification for informationon capacitive loading limits and pin input voltage high(VIH) and input low (VIL) requirements.

Ensure that the Communication Channel Select (i.e.,PGECx/PGEDx pins) programmed into the devicematches the physical connections for the ICSP toMPLAB ICD 2, MPLAB ICD 3, or MPLAB REALICE.

For more information on ICD 2, ICD 3, and REAL ICEconnection requirements, refer to the followingdocuments that are available on the Microchip website.

MPLAB ICD 2 In-Circuit Debugger User's Guide DS51331

Using MPLAB ICD 2 (poster) DS51265 MPLAB ICD 2 Design Advisory DS51566 Using MPLAB ICD 3 (poster) DS51765 MPLAB ICD 3 Design Advisory DS51764 MPLAB REAL ICE In-Circuit Debugger

User's Guide DS51616 Using MPLAB REAL ICE (poster) DS51749

2.6 External Oscillator PinsMany DSCs have options for at least two oscillators: ahigh-frequency primary oscillator and a low-frequencysecondary oscillator (refer to Section 9.0 OscillatorConfiguration for details). The oscillator circuit should be placed on the sameside of the board as the device. Also, place theoscillator circuit close to the respective oscillator pins,not exceeding one-half inch (12 mm) distancebetween them. The load capacitors should be placednext to the oscillator itself, on the same side of theboard. Use a grounded copper pour around theoscillator circuit to isolate them from surroundingcircuits. The grounded copper pour should be routeddirectly to the MCU ground. Do not run any signaltraces or power traces inside the ground pour. Also, ifusing a two-sided board, avoid any traces on theother side of the board where the crystal is placed. Asuggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT

13Main Oscillator

Guard Ring

Guard Trace

SecondaryOscillator

14

15

16

17

18

19

20 2009 Microchip Technology Inc. Preliminary DS70291C-page 21

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X042.7 Oscillator Value Conditions on Device Start-up

If the PLL of the target device is enabled andconfigured for the device start-up oscillator, themaximum oscillator source frequency must be limitedto 4 MHz < FIN < 8 MHz to comply with device PLLstart-up conditions. This means that if the externaloscillator frequency is outside this range, theapplication must start-up in the FRC mode first. Thedefault PLL settings after a POR with an oscillatorfrequency outside this range will violate the deviceoperating speed.

Once the device powers up, the application firmwarecan initialize the PLL SFRs, CLKDIV, and PLLDBF to asuitable value, and then perform a clock switch to theOscillator + PLL clock source. Note that clock switchingmust be enabled in the device Configuration word.

2.8 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, ICD 3, or REAL ICE is selected as adebugger, it automatically initializes all of the A/D inputpins (ANx) as digital pins, by setting all bits in theAD1PCFGL register.

The bits in this register that correspond to the A/D pinsthat are initialized by MPLAB ICD 2, ICD 3, or REALICE, must not be cleared by the user applicationfirmware; otherwise, communication errors will resultbetween the debugger and the device.

If your application needs to use certain A/D pins asanalog input pins during the debug session, the userapplication must clear the corresponding bits in theAD1PCFGL register during initialization of the ADCmodule.

When MPLAB ICD 2, ICD 3, or REAL ICE is used as aprogrammer, the user application firmware mustcorrectly configure the AD1PCFGL register. Automaticinitialization of this register is only done duringdebugger operation. Failure to correctly configure theregister(s) will result in all A/D pins being recognized asanalog input pins, resulting in the port value being readas a logic '0', which may affect user applicationfunctionality.

2.9 Unused I/OsUnused I/O pins should be configured as outputs anddriven to a logic-low state.

Alternatively, connect a 1k to 10k resistor to VSS onunused pins and drive the output to logic low.DS70291C-page 22 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X043.0 CPU

3.1 OverviewThe dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 CPU module has a 16-bit(data) modified Harvard architecture with an enhancedinstruction set, including significant support for DSP.The CPU has a 24-bit instruction word with a variablelength opcode field. The Program Counter (PC) is23 bits wide and addresses up to 4M x 24 bits of userprogram memory space. The actual amount of programmemory implemented varies by device. A single-cycleinstruction prefetch mechanism is used to help main-tain throughput and provides predictable execution. Allinstructions execute in a single cycle, with the excep-tion of instructions that change the program flow, thedouble-word move (MOV.D) instruction and the tableinstructions. Overhead-free program loop constructsare supported using the DO and REPEAT instructions,both of which are interruptible at any time.

The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 devices have sixteen, 16-bitworking registers in the programmers model. Each ofthe working registers can serve as a data, address oraddress offset register. The 16th working register(W15) operates as a software Stack Pointer (SP) forinterrupts and calls.

There are two classes of instruction in thedsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,and dsPIC33FJ128MCX02/X04 devices: MCU andDSP. These two instruction classes are seamlesslyintegrated into a single CPU. The instruction setincludes many addressing modes and is designed foroptimum C compiler efficiency. For most instructions,the dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 is capable of executing adata (or program data) memory read, a workingregister (data) read, a data memory write and aprogram (instruction) memory read per instructioncycle. As a result, three parameter instructions can besupported, allowing A + B = C operations to beexecuted in a single cycle.

A block diagram of the CPU is shown in Figure 3-1, andthe programmers model for thedsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,and dsPIC33FJ128MCX02/X04 is shown in Figure 3-2.

3.2 Data Addressing OverviewThe data space can be addressed as 32K words or64 Kbytes and is split into two blocks, referred to as Xand Y data memory. Each memory block has its ownindependent Address Generation Unit (AGU). TheMCU class of instructions operates solely through theX memory AGU, which accesses the entire memorymap as one linear data space. Certain DSP instructionsoperate through the X and Y AGUs to support dualoperand reads, which splits the data address spaceinto two parts. The X and Y data space boundary isdevice-specific.

Overhead-free circular buffers (Modulo Addressingmode) are supported in both X and Y address spaces.The Modulo Addressing removes the softwareboundary checking overhead for DSP algorithms.Furthermore, the X AGU circular addressing can beused with any of the MCU class of instructions. The XAGU also supports Bit-Reversed Addressing to greatlysimplify input or output data reordering for radix-2 FFTalgorithms.

The upper 32 Kbytes of the data space memory mapcan optionally be mapped into program space at any16K program word boundary defined by the 8-bitProgram Space Visibility Page (PSVPAG) register. Theprogram-to-data-space mapping feature lets anyinstruction access program space as if it were dataspace.

3.3 DSP Engine OverviewThe DSP engine features a high-speed 17-bit by 17-bitmultiplier, a 40-bit ALU, two 40-bit saturatingaccumulators and a 40-bit bidirectional barrel shifter.The barrel shifter is capable of shifting a 40-bit value upto 16 bits right or left, in a single cycle. The DSPinstructions operate seamlessly with all otherinstructions and have been designed for optimalreal-time performance. The MAC instruction and otherassociated instructions can concurrently fetch two dataoperands from memory while multiplying two Wregisters and accumulating and optionally saturatingthe result in the same cycle. This instructionfunctionality requires that the RAM data space be splitfor these instructions and linear for all others. Dataspace partitioning is achieved in a transparent andflexible manner through dedicating certain workingregisters to each address space.

Note: This data sheet summarizes the featuresof dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 families of devices.It is not intended to be a comprehensivereference source. To complement theinformation in this data sheet, refer to thedsPIC33F Family Reference Manual,Section 2. CPU (DS70204), which isavailable from the Microchip website(www.microchip.com). 2009 Microchip Technology Inc. Preliminary DS70291C-page 23

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X043.4 Special MCU FeaturesThe dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 features a 17-bit by 17-bitsingle-cycle multiplier that is shared by both the MCUALU and DSP engine. The multiplier can performsigned, unsigned and mixed-sign multiplication. Usinga 17-bit by 17-bit multiplier for 16-bit by 16-bitmultiplication not only allows you to perform mixed-signmultiplication, it also achieves accurate results forspecial operations, such as (-1.0) x (-1.0).

The dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 supports 16/16 and 32/16divide operations, both fractional and integer. All divideinstructions are iterative operations. They must beexecuted within a REPEAT loop, resulting in a totalexecution time of 19 instruction cycles. The divideoperation can be interrupted during any of those19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bitleft or right shift in a single cycle. The barrel shifter canbe used by both MCU and DSP instructions.DS70291C-page 24 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04FIGURE 3-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04 CPU CORE BLOCK DIAGRAM

InstructionDecode &

Control

PCH PCLProgram Counter

16-bit ALU

24

23

Instruction Reg

PCU

16 x 16W Register Array

ROM Latch

EA MUX

InterruptController

StackControlLogic

LoopControlLogic

Data Latch

AddressLatch

Control Signalsto Various Blocks

L

itera

l Dat

a

16 16

16

To Peripheral Modules

Data Latch

AddressLatch

16

X RAM Y RAM

Address Generator Units

16

Y Data Bus

X Data Bus

DMA

Controller

DMA

RAM

DSP Engine

Divide Support

16

16

23

23

168

PSV & TableData AccessControl Block

16

16

16

16

Program Memory

Data Latch

Address Latch 2009 Microchip Technology Inc. Preliminary DS70291C-page 25

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04FIGURE 3-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04 PROGRAMMERS MODEL

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP OperandRegisters

W1

W2

W3

W4

W5

W6W7

W8

W9

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP AddressRegisters

AD39 AD0AD31

DSPAccumulators

ACCAACCB

7 0Program Space Visibility Page Address

Z

0

OA OB SA SB

RCOUNT15 0

REPEAT Loop Counter

DCOUNT15 0

DO Loop Counter

DOSTART 22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End AddressDOEND 22

CDS70291C-page 26 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X043.5 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0OA OB SA(1) SB(1) OAB SAB DA DC

bit 15 bit 8

R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL(2) RA N OV Z C

bit 7 bit 0

Legend:C = Clear only bit R = Readable bit U = Unimplemented bit, read as 0S = Set only bit W = Writable bit -n = Value at POR1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit1 = Accumulator A overflowed0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit1 = Accumulator B overflowed0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation Sticky Status bit(1)

1 = Accumulator A is saturated or has been saturated at some time0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation Sticky Status bit(1)

1 = Accumulator B is saturated or has been saturated at some time0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit1 = Accumulators A or B have overflowed0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator (Sticky) Status bit(4)

1 = Accumulators A or B are saturated or have been saturated at some time in the past0 = Neither Accumulator A or B are saturated

bit 9 DA: DO Loop Active bit1 = DO loop in progress0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry/Borrow bit1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

Note 1: This bit can be read or cleared (not set).2: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled whenIPL = 1.

3: The IPL Status bits are read only when NSTDIS = 1 (INTCON1).4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. 2009 Microchip Technology Inc. Preliminary DS70291C-page 27

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04

bit 7-5 IPL: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bitThis bit is used for signed arithmetic (twos complement). It indicates an overflow of a magnitude thatcauses the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation)0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit1 = An operation that affects the Z bit has set it at some time in the past0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)

Note 1: This bit can be read or cleared (not set).2: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled whenIPL = 1.

3: The IPL Status bits are read only when NSTDIS = 1 (INTCON1).4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.DS70291C-page 28 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04REGISTER 3-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 US EDT(1) DL

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF

bit 7 bit 0

Legend: C = Clear only bitR = Readable bit W = Writable bit -n = Value at POR 1 = Bit is set0 = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as 0

bit 15-13 Unimplemented: Read as 0bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit(1)1 = Terminate executing DO loop at end of current loop iteration0 = No effect

bit 10-8 DL: DO Loop Nesting Level Status bits111 = 7 DO loops active001 = 1 DO loop active000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit1 = Accumulator A saturation enabled0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit1 = Accumulator B saturation enabled0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit1 = Data space write saturation enabled0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit1 = 9.31 saturation (super saturation)0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data space

Note 1: This bit is always read as 0.2: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. 2009 Microchip Technology Inc. Preliminary DS70291C-page 29

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04bit 1 RND: Rounding Mode Select bit1 = Biased (conventional) rounding enabled0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit1 = Integer mode enabled for DSP multiply ops0 = Fractional mode enabled for DSP multiply ops

REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)

Note 1: This bit is always read as 0.2: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.DS70291C-page 30 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X043.6 Arithmetic Logic Unit (ALU)The dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 ALU is 16 bits wide and iscapable of addition, subtraction, bit shifts and logicoperations. Unless otherwise mentioned, arithmeticoperations are twos complement in nature. Dependingon the operation, the ALU can affect the values of theCarry (C), Zero (Z), Negative (N), Overflow (OV) andDigit Carry (DC) Status bits in the SR register. The Cand DC Status bits operate as Borrow and Digit Borrowbits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,depending on the mode of the instruction that is used.Data for the ALU operation can come from the Wregister array or data memory, depending on theaddressing mode of the instruction. Likewise, outputdata from the ALU can be written to the W register arrayor a data memory location.

Refer to the dsPIC30F/33F Programmers ReferenceManual (DS70157) for information on the SR bitsaffected by each instruction.

The dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 CPU incorporateshardware support for both multiplication and division.This includes a dedicated hardware multiplier andsupport hardware for 16-bit-divisor division.

3.6.1 MULTIPLIERUsing the high-speed 17-bit x 17-bit multiplier of theDSP engine, the ALU supports unsigned, signed ormixed-sign operation in several MCU multiplicationmodes:

16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned

3.6.2 DIVIDERThe divide block supports 32-bit/16-bit and 16-bit/16-bitsigned and unsigned integer divide operations with thefollowing data sizes:

1. 32-bit signed/16-bit signed divide2. 32-bit unsigned/16-bit unsigned divide3. 16-bit signed/16-bit signed divide4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0and the remainder in W1. 16-bit signed and unsignedDIV instructions can specify any W register for boththe 16-bit divisor (Wn) and any W register (aligned)pair (W(m + 1):Wm) for the 32-bit dividend. The dividealgorithm takes one cycle per bit of divisor, so both32-bit/16-bit and 16-bit/16-bit instructions take thesame number of cycles to execute.

3.7 DSP EngineThe DSP engine consists of a high-speed 17-bit x17-bit multiplier, a barrel shifter and a 40-bitadder/subtracter (with two target accumulators, roundand saturation logic).

The dsPIC33FJ32MC302/304,dsPIC33FJ64MCX02/X04, anddsPIC33FJ128MCX02/X04 is a single-cycle instructionflow architecture; therefore, concurrent operation of theDSP engine with MCU instruction flow is not possible.However, some MCU ALU and DSP engine resourcescan be used concurrently by the same instruction(e.g., ED, EDAC).

The DSP engine can also perform inherentaccumulator-to-accumulator operations that require noadditional data. These instructions are ADD, SUB andNEG.The DSP engine has options selected through bits inthe CPU Core Control register (CORCON), as listedbelow:

Fractional or integer DSP multiply (IF) Signed or unsigned DSP multiply (US) Conventional or convergent rounding (RND) Automatic saturation on/off for ACCA (SATA) Automatic saturation on/off for ACCB (SATB) Automatic saturation on/off for writes to data

memory (SATDW) Accumulator Saturation mode selection

(ACCSAT)

A block diagram of the DSP engine is shown inFigure 3-3. 2009 Microchip Technology Inc. Preliminary DS70291C-page 31

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04TABLE 3-1: DSP INSTRUCTIONS SUMMARY

FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM

Instruction Algebraic Operation ACC Write BackCLR A = 0 YesED A = (x y)2 NoEDAC A = A + (x y)2 NoMAC A = A + (x y) YesMAC A = A + x2 NoMOVSAC No change in A YesMPY A = x y NoMPY A = x 2 NoMPY.N A = x y NoMSC A = A x y Yes

Zero Backfill

Sign-Extend

BarrelShifter

40-bit Accumulator A40-bit Accumulator B Round

Logic

X D

ata

Bus

To/From W Array

Adder

Saturate

Negate

32

3233

16

16 16

16

40 40

4040

Saturate

Y D

ata

Bus

40

Carry/Borrow Out

Carry/Borrow In

16

40

Multiplier/Scaler17-bitDS70291C-page 32 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X043.7.1 MULTIPLIERThe 17-bit x 17-bit multiplier is capable of signed orunsigned operation and can multiplex its output using ascaler to support either 1.31 fractional (Q31) or 32-bitinteger results. Unsigned operands are zero-extendedinto the 17th bit of the multiplier input value. Signedoperands are sign-extended into the 17th bit of themultiplier input value. The output of the 17-bit x 17-bitmultiplier/scaler is a 33-bit value that is sign-extendedto 40 bits. Integer data is inherently represented as asigned twos complement value, where the MostSignificant bit (MSb) is defined as a sign bit. The rangeof an N-bit twos complement integer is -2N-1 to 2N-1 1.

For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0.

For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractionalmultiplication, the data is represented as a twoscomplement fraction, where the MSb is defined as asign bit and the radix point is implied to lie just after thesign bit (QX format). The range of an N-bit twoscomplement fraction with this implied radix point is -1.0to (1 21-N). For a 16-bit fraction, the Q15 data rangeis -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0and has a precision of 3.01518x10-5. In Fractionalmode, the 16 x 16 multiply operation generates a 1.31product that has a precision of 4.65661 x 10-10.

The same multiplier is used to support the MCUmultiply instructions, which include integer 16-bitsigned, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte orword-sized operands. Byte operands direct a 16-bitresult, and word operands direct a 32-bit result to thespecified registers in the W array.

3.7.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40-bitadder/subtracter with automatic sign extension logic. Itcan select one of two accumulators (A or B) as itspre-accumulation source and post-accumulationdestination. For the ADD and LAC instructions, the datato be accumulated or loaded can be optionally scaledusing the barrel shifter prior to accumulation.

3.7.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optionalzero input into one side, and either true or complementdata into the other input.

In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented).

In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented.

The adder/subtracter generates Overflow Status bits,SA/SB and OA/OB, which are latched and reflected inthe STATUS register:

Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed.

Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block thatcontrols accumulator data saturation, if selected. Ituses the result of the adder, the Overflow Status bitsdescribed previously and the SAT(CORCON) and ACCSAT (CORCON) modecontrol bits to determine when and to what value tosaturate.

Six STATUS register bits support saturation andoverflow:

OA: ACCA overflowed into guard bits OB: ACCB overflowed into guard bits SA: ACCA saturated (bit 31 overflow and

saturation)orACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

SB: ACCB saturated (bit 31 overflow and saturation)orACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

OAB: Logical OR of OA and OB SAB: Logical OR of SA and SB

The OA and OB bits are modified each time datapasses through the adder/subtracter. When set, theyindicate that the most recent operation has overflowedinto the accumulator guard bits (bits 32 through 39).The OA and OB bits can also optionally generate anarithmetic warning trap when set and thecorresponding Overflow Trap Flag Enable bits (OVATE,OVBTE) in the INTCON1 register are set (refer toSection 7.0 Interrupt Controller). This allows theuser application to take immediate action, for example,to correct system gain.

The SA and SB bits are modified each time datapasses through the adder/subtracter, but can only becleared by the user application. When set, they indicatethat the accumulator has overflowed its maximumrange (bit 31 for 32-bit saturation or bit 39 for 40-bit sat-uration) and is saturated (if saturation is enabled).When saturation is not enabled, SA and SB default tobit 39 overflow and thus indicate that a catastrophicoverflow has occurred. If the COVTE bit in theINTCON1 register is set, the SA and SB bits generatean arithmetic warning trap when saturation is disabled. 2009 Microchip Technology Inc. Preliminary DS70291C-page 33

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04The Overflow and Saturation Status bits canoptionally be viewed in the STATUS Register (SR) asthe logical OR of OA and OB (in bit OAB) and thelogical OR of SA and SB (in bit SAB). Programmerscan check one bit in the STATUS register todetermine if either accumulator has overflowed, orone bit to determine if either accumulator hassaturated. This is useful for complex numberarithmetic, which typically uses both accumulators.

The device supports three Saturation and Overflowmodes:

Bit 39 Overflow and Saturation:When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as super saturation and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations).

Bit 31 Overflow and Saturation:When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set.

Bit 39 Catastrophic Overflow:The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

3.7.3 ACCUMULATOR WRITE BACKThe MAC class of instructions (with the exception ofMPY, MPY.N, ED and EDAC) can optionally write arounded version of the high word (bits 31 through 16)of the accumulator that is not targeted by the instructioninto data space memory. The write is performed acrossthe X bus into combined X and Y address space. Thefollowing addressing modes are supported:

W13, Register Direct:The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

[W13] + = 2, Register Indirect with Post-Increment:The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

3.7.3.1 Round LogicThe round logic is a combinational block that performsa conventional (biased) or convergent (unbiased)round function during an accumulator write (store). TheRound mode is determined by the state of the RND bitin the CORCON register. It generates a 16-bit, 1.15data value that is passed to the data space writesaturation logic. If rounding is not indicated by theinstruction, a truncated 1.15 data value is stored andthe least significant word is simply discarded.

Conventional rounding zero-extends bit 15 of theaccumulator and adds it to the ACCxH word (bits 16through 31 of the accumulator).

If the ACCxL word (bits 0 through 15 of the accu-mulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented.

If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged.

A consequence of this algorithm is that over a succes-sion of random rounding operations, the value tends tobe biased slightly positive.

Convergent (or unbiased) rounding operates in thesame manner as conventional rounding, except whenACCxL equals 0x8000. In this case, the LeastSignificant bit (bit 16 of the accumulator) of ACCxH isexamined:

If it is 1, ACCxH is incremented. If it is 0, ACCxH is not modified.Assuming that bit 16 is effectively random in nature,this scheme removes any rounding bias that mayaccumulate.

The SAC and SAC.R instructions store either atruncated (SAC), or rounded (SAC.R) version of thecontents of the target accumulator to data memory viathe X bus, subject to data saturation (seeSection 3.7.3.2 Data Space Write Saturation). Forthe MAC class of instructions, the accumulatorwrite-back operation functions in the same manner,addressing combined MCU (X and Y) data spacethough the X bus. For this class of instructions, the datais always subject to rounding.DS70291C-page 34 Preliminary 2009 Microchip Technology Inc.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X043.7.3.2 Data Space Write SaturationIn addition to adder/subtracter saturation, wri

dspic33fj32mc302

Documents

microchip logo

microchip products

microchip devices

trademarksthe microchip

theft microchip

andhold harmless microchip

unbreakablcode protection

keeloq logo