Microelectronics Reliability 53 (2013) 1036–1042

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Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Dynamic voltage and frequency scaling algorithm for fault-tolerantreal-time systems

Sandra Djosic ⇑, Milun JevticFaculty of Electronic Engineering, University of Nis, Aleksandra Medvedeva 14, 18000 Nis, Serbia

a r t i c l e i n f o a b s t r a c t

Article history:Received 25 October 2012Received in revised form 26 March 2013Accepted 26 March 2013Available online 16 April 2013

0026-2714/$ - see front matter � 2013 Elsevier Ltd. Ahttp://dx.doi.org/10.1016/j.microrel.2013.03.012

⇑ Corresponding author. Tel.: +381 18 529 601; faxE-mail address: sandra.djosic@elfak.ni.ac.rs (S. Djo

Many modern real-time systems (RTSs) are required to provide both fault tolerance and energy-efficiencyin addition to their main objective to compute and deliver correct results within a specified period oftime. Dynamic voltage and frequency scaling (DVFS) technique is known as one of the most effectivelow-energy technique for RTSs. However, most existing DVFS techniques only focus on minimizingenergy consumption without taking the fault-tolerant capability of RTS into account. To solve this prob-lem, in this paper we developed a new heuristic-based fault-tolerant dynamic voltage and frequency scal-ing (FT-DVFS) algorithm. The goal of the proposed algorithm is to find frequencies at which each taskshould be executed such that the energy consumed by the set of task is minimized. Beside energy min-imization FT-DVFS algorithm has to meet all real-time requirements of individual tasks and to keep thesystem’s ability to tolerate transient faults via task re-execution. The simulation results show that theproposed approach could save a significant amount of energy while preserving the required level of sys-tem’s fault-tolerance capability when compared with the solutions obtained without energy-minimization.

� 2013 Elsevier Ltd. All rights reserved.

1. Introduction

A system is said to be real-time if the total correctness of anoperation depends not only upon its logical correctness, but alsoupon the time in which it is performed. Many RTSs are requiredto have continuous reliability so they are usually realized withthe ability of tolerating some faults. Fault-tolerant real-time sys-tems (FT RTSs) have to ensure that faults in the system do not leadto a failure. Nowadays, transient faults represent one of the mostsignificant issues in the design of FT RTSs [1]. These faults appearonly once and then disappear so we cannot trace them later on.Transient faults occur when an event (e.g., cosmic particle strikes,power supply noise, device coupling) causes the deposit or removalof enough charge to invert the state of a transistor. The invertedvalue may propagate to cause an error in program execution [2].CMOS downscaling trends, manifested in the use of smallertransistor feature sizes and lower supply voltages, make digitalcircuits more and more vulnerable to transient errors with eachnew technology generation [3].

Fault-tolerance schemes generally rely on some form of redun-dancy [4]. We are particularly interested in the time redundancytechniques, since they are cost-effective as well as more suitableto applications where there are severe constraints on space and

ll rights reserved.

: +381 18 588 399.sic).

weight. This technique is specially used for overcoming the tran-sient faults [5,6]. Since, among all types of faults the transientfaults are much more common [7] we found the problem of theirovercoming in RTSs using time redundancy important. In the con-text of RTSs the most common approach of time redundancy is there-execution of a faulty task (i.e., running the task affected by afault again) [8–10]. This is relatively inexpensive method of provid-ing fault tolerance since no extra hardware is required.

Response Time Analysis (RTA) [11] is an important techniquefor analyzing timing constraints of RTSs. In its various forms it al-lows an exact calculation of the worst-case response time of tasksin single and multiprocessor RTSs scheduled under fixed priorities.Originally, RTA has been used for analyzing RTSs with the assump-tion that there is no error during system execution. This fault-freeassumption is, in fact, not realistic. Quoting Laprie: ‘‘Non-faultysystems hardly exist, there are only systems which may have notyet failed’’. Burns et al. extended classical RTA to cope with the pos-sibility of errors in the RTSs [12]. Their RTA method assumes theuse of static free slack-time in the system schedule for performingre-execution of the faulty task in order to obtain reliable RTS. In[13] we used RTA for analyzing timing constraints of one faulttolerant hard real-time system with time redundancy. Modifiedversion RTA, with the aim of getting more reliable RTS, waspresented on our paper [14]. RTA was focus of some recent re-searches [15–17]. Altmeyer et al. integrates pre-emption costsinto RTA for fixed priority pre-emptive scheduling [15]. Theyshowed that this combined approach offers a significant improve-

S. Djosic, M. Jevtic / Microelectronics Reliability 53 (2013) 1036–1042 1037

ment in performance for a wide range of different task and cacheconfigurations. In [16] Mubeen et al. implemented and integratedmodified real-time analysis technique with an existing industrialtool suite for the development of distributed real-time embeddedsystems. Yun et al. used RTA in multiprocessor RTSs [17]. They ex-tended basic RTA by taking into account the task stalling caused bycontention from interfering cores in multiprocessor systems.

In addition to high reliability, demand for low power consump-tion has risen sharply, particularly in RTSs where energy is limited(e.g., battery-powered systems). Decreasing the energy consump-tion not only extends the battery life, but also reduces the packag-ing and cooling costs of the systems. Since energy consumption ofthe CPU often dominates to the energy consumption of the entireRTS our attention is focused on the energy efficiency of the proces-sor. Dynamic voltage and frequency scaling (DVFS) technique hasproven to be a highly effective method of achieving CPU’s lowpower consumption while meeting the performance requirements[18–20]. A number of modern microprocessors such as AMD’s Mo-bile Athlon [21], Intel’s XScale [22] and Transmeta’s Crusoe [23] areequipped with the DVFS functionality. The key idea behind DVFStechnique is to exploit the quadratic relationship between CPU en-ergy consumption and supply voltage. By lowering the supply volt-age and correspondingly the clock frequency simultaneously, theenergy consumption of processors can be reduced quadratically[24]. However, the energy saving achieved by DVFS comes at thecost of extended execution time of real-time tasks, which maycompromise the timing correctness of RTS. For example in [19]execution time of a real-time task scales linearly with the process-ing speed i.e., if the operating frequency is scaled the by a factor a,then execution time must be scaled by factor 1/a. Several DVFStechniques have been proposed to minimize the total energy inthe RTS [18,25–28]. These techniques differ in many aspects, suchas the scheduling algorithms being on-line or off-line, handlinghard or soft deadline requirements, and assuming fixed or dynamicpriority assignment. In [18] Kim et al. compare several key DVFSalgorithms proposed for hard real-time periodic task sets, analyzetheir energy efficiency, and discuss the performance differencesquantitatively. Pillai and Shin in [29] proposed the ccRM algorithm,which first computes off-line the maximum speed necessary tomeet all task deadlines. On-line, the processor speed is scaleddown when task complete early. In [28] Gruian presents a methodof off-line task stretching coupled with on-line slack distribution.In addition, the paper presents a voltage scheduling method thatcomputes the optimal speed for each execution cycle of the activetask. Chen et al. control CPU utilization in distributed RTSs usingDVFS technique [30]. Their method is based on adjusting the exe-cution time of the tasks by scaling the processor frequency. In [31]He and Mueller presents energy efficient scheduling in componentoriented hard real-time system using DVFS techniques. Kumari andKumar propose a real-time scheduling algorithm with variabletask’s speed assignment scheme aims to reduce the energy con-sumption of the task set [32]. They use DVFS to control operatingspeed.

While time redundancy techniques use free slack time to im-prove reliability, DVFS exploits slack time to decrease energy con-sumption. Because the free slack time is a limited resource, it isobvious that more slack time used for DVFS leaves less time slackfor fault tolerance, and vice versa. Therefore, there is a tradeoff be-tween low energy consumption and high fault tolerance. In thecontext of real-time systems this tradeoff is analyzed in several pa-pers [33–35]. Qadi and Goddard [33] present a DVFS algorithmsupporting the canonical sporadic real-time task model. The meth-od, however, is designed only for the EDF (earliest deadline first)priority discipline and it is not applicable to RM (rate monotonic)[36]. Melham et al. proposed techniques to exploit free slacks intask schedules to reduce energy consumption while tolerating

faults based on DVFS [35]. They make several simplifying assump-tions such as a task is susceptible to at most one fault occurrenceand the processor can scale its frequency in continuous range. Nev-ertheless, practical commercial processors only support severaldiscrete levels of supply voltages and frequencies [21–23].

In this paper, we propose a heuristic-based FT-DVFS (fault-tol-erant – DVFS) algorithm for RTSs that attempts to minimize the en-ergy consumed by a real-time task sets under fault toleranceconstraints while guaranteeing that each task can complete suc-cessfully before its deadline. Our proposed FT-DVFS algorithm isapplicable to an important class of RTS modeled as a set of fixed-priority preemptive periodic tasks, with different periods. Severaldiscrete supply voltages and operating frequency levels are takeninto consideration. Compensating for the negative effect on reli-ability, we adopt the faulty task re-execution fault-tolerant tech-nique. The main novelty of our approach is the use of RTA tocheck the schedulability of fault-tolerant real-time task sets whilevarying voltage/frequency levels during DVFS power-optimization.To the best of our knowledge, this is the first time that RTA is inte-grated into a DVFS technique.

Theremainderofthepaperproceedsasfollows.Section2introducethe system model and problem statement. The proposed FT-DVFSalgorithm is presented in Section 3. Section 4 presents simulation re-sults to validate our work. Conclusions are included in Section 5.

2. Modeling and problem statement

For the FT-DVFS problem, we are given n real time tasks. Eachtask has a given period, worst case execution time, deadline andpriority. Also, a RTS can switch the frequency of its processor bydynamically adapting its voltage level. Hence, we have a set of ac-tive operating levels with frequencies and corresponding powers.Furthermore, it is expected that the RTS attains a given level offault-tolerant capability, which is expressed via a fault-tolerantconstraint (will be defined later in this section). The goal of ourFT-DVFS algorithm is to assign each task an operating frequencyso that the total power consumption is minimized while keepingthe real-time task set schedulable under fault-tolerant constraint.

In this section, we first describe models that cover three differentaspects of the FT-DVFS problem: real-time, power consumption andfault-tolerance. Then, we formally specify the FT-DVFS problem.

2.1. Task model

We modeled RTS as a set of n periodic real-time tasks, C = {s1, -. . . ,sn} where each task si is associated with period Ti, worst caseexecution time (WCET) Ci and deadline Di. We also assumed thatall tasks start at the time 0 and have deadline Di equal to periodTi. Each task is assigned a unique fixed priority pi. Algorithm forscheduling real-time tasks could be any priority assignment algo-rithm [36]. We adopted a fully preemptive and independent taskexecution model. We assume a scenario where a single CPU exe-cutes a set of real-time tasks. The voltage and consequently theoperating frequency of the CPU can be switched among m discretevalues. We denoted voltage levels with Uj (j = 1, . . . ,m), where Uj < -Uj+1 and Um is the maximum voltage and frequency levels with fj

(j = 1, . . . ,m), where fj < fj+1 and fm is the maximum frequency.Given a set C of n tasks and a set of m frequencies, there are mn

different mappings of the set of frequencies onto the set of tasks.Each mapping can be represented by the so called frequency assign-ment vector F = (x1,x2, . . . ,xn), where xi e {1, . . . ,m} is the index of thefrequency assigned to task si.

We adopt assumption that the WCET of a task scales linearlywith the processing speed [19]. Therefore, if we scale the operatingfrequency by a factor a, then WCET is scaled by factor 1/a.

1038 S. Djosic, M. Jevtic / Microelectronics Reliability 53 (2013) 1036–1042

2.2. Power model

In this work, we adopt a simple power model proposed in [37],where the power consumption P of a system is given by:

P ¼ Ps þ hðPind þ PdÞ ¼ Ps þ hðPind þ V2ðf ÞCef f Þ ð1Þ

Despite its simplicity, this power model captures the essentialpower consumption components [38]. In Eq. (1), Ps is the staticpower, which can be removed only by powering off the whole sys-tem. Pind is the frequency-independent active power, which is con-stant and corresponds to the power that is independent of CPUprocessing speed. It can be efficiently removed by putting systemsinto sleep state. Pd is the frequency-dependent active power, whichincludes processor’s dynamic power and any power that dependson CPU speed. When there is computation in progress, the systemis active and h = 1. Otherwise, when the system is turned off or inpower-saving sleep modes, h = 0. Cef is the effective switchingcapacitance, f is the operating frequency and V is supply voltageand it is a function of operating frequency.

For simplicity, we ignore the static power Ps (i.e., Ps = 0).Whereas the DVFS techniques enable energy management varyingthe supply voltage and correspondingly the operating frequency,frequency-independent active power Pind also does not affect thepower reduction of the system. Consequently, in our analysis, wetake into account the frequency-dependent active power Pd, only.

2.3. Fault and recovery model

In this paper we focus on transient faults. We suppose thatfaults can occur during execution of any task. Our proposedscheme uses re-execution recovery for fault-tolerance. We supposethat affected task executing again at its original priority level andat its original operating frequency. The re-execution of the cor-rupted task must not violate timing constraints of any task in C.For checking the schedulability of fault-tolerant real-time taskset we use the response time analysis. In the RTA, the fault-toler-ance capability of a RTS is represented by a single parameter, TF,which corresponds to minimum time interval between two con-secutive faults that the RTS can tolerate. According to RTA the re-sponse time of task si is calculated as [12]:

Rnþ1i ¼ Ci þ

Xj2hpðiÞ

Rni

Tj

� �Cj þ

Rni

TF

� �max

j2hpðiÞ[iðCjÞ ð2Þ

The response time Ri of the task si is defined as the time span be-tween the activation time of that task and its completion time.According to Eq. (2) Ri is represented as the sum of:– WCET Ci for a task si,– interference due to preemption by higher priority tasks sj from

the set hp(i) = {sj e C|pj > pi},– tolerance due to possible fault in the system (the third addend).

There can be at most Rni

TF

l mfaults during the response time Rn

i oftask si. Since these faults could occur during the execution oftask si or any higher priority task which has preempted si, eachfault may add maxj2hpðiÞ[iðCjÞ to the response time of task si.

Hence, the third addend in Eq. (2) presents an extra timeneeded for task recovery due to faults.

Eq. (2) presents recurrence relation since Ri appears on bothsides of the equation. The calculation starts with R0

i ¼ Ci and thesolution is found when Rnþ1

i ¼ Rni . If during the iteration process

we get that Rnþ1i > Di then task si is considered infeasible and the

iteration process is terminated. The task sets is feasible if each taskfinishes before its deadline, i.e. Ri 6 Di, i = 1, . . . ,n.

2.4. Problem statement

Given a fully-specified task set (each task is defined by Ti, Ci, Di

and pi), plus m voltage levels with the associated clock frequenciesand power, as well as the fault-tolerant constrain, the FT-DVFSproblem is to find the frequency assignment vector to minimizethe power consumption for the entire task-set under the followingconstraints: the task set is schedulable according to RTA schedula-bility test.

To write FT-DVFS problem in formulas, let {C1, . . . ,Cn},{T1, . . . ,Tn}, {D1, . . . ,Dn}, and {p1, . . . ,pn} be the WCET, period, dead-line and priority of each task in real-time task-set C = {s1, . . . ,sn},respectively. Let {f1, . . . , fm} and F = (x1,x2, . . . ,xn) be the set of avail-able frequency levels, and the frequency assignment vector,respectively. Finally, let TF be the minimum time interval betweentwo consecutive faults that the RTS can tolerate. Then, the FT-DVFSproblem is:

min PCðFÞ ¼Xn

i¼1

Pd;xi� Ci;xi

=Ti ð3Þ

subject to:

RiðFÞ � Di; i ¼ 1; . . . ;n ð4Þ

Eq. (3) describes the total power consumption of the task-set Cwhen assigned with the frequency vector F. In this equation Pd;xi

and Ci;xiare the power consumption of the CPU when operating at

frequency fi and WCET of task si when executed with the frequencyindex xi, respectively. We define Ci;xi

as:

Ci;xi¼ fm=fi � Ci;m

Eq. (4) describes schedulability condition for each task in C. In thisequation, Ri(F) is the response time of task si calculated according to(1) by using WCET of tasks at their assigned frequencies, instead ofCi:

Rnþ1i ¼ Ci;xi

þX

j2hpðiÞ

Rni

Tj

� �Cj;xjþ Rn

i

TF

� �max

j2hpðiÞ[iðCj;xjÞ

3. Proposed FT-DVFS algorithm

The straightforward solution for FT-DVFS problem is to explic-itly generate all nm frequency assignment vectors, reject unsched-ulable ones, and choose the frequency assignment vector for whichthe power consumption of the task sets is minimal. Given the min-imum time interval between two consecutive faults that RTSshould tolerate (input parameter TF), and frequency assignmentvector, the schedulability of task-set is checked by using RTA, whilethe power consumption is calculated according to Eq. (3). We callthis approach the method of exhaustion. The main difficulty of thisapproach is that it is too computationally intensive to be used forlarge task sets. This is because of exponential number of frequencyassignment vectors for which the schedulabiity of the task set needto checked. Nevertheless, for small set of real-time tasks the meth-od of exhausting is a useful and optimal solution.

In this section, we present our proposed heuristic-based FT-DVFS algorithm which can find near-optimal solution within anacceptable computational time even for large real-time task set in-stances. The FT-DVFS algorithm starts with assigning the maxi-mum frequency to each task and then iteratively improves thefrequency assignment, in terms of total power consumption, bygradually decreasing the frequencies of selected tasks until no fur-ther improvement can be achieved.

Fig. 1 gives the proposed FT-DVFS algorithm in pseudo codeform. The FT-DVFS algorithm starts from the frequency assignment

S. Djosic, M. Jevtic / Microelectronics Reliability 53 (2013) 1036–1042 1039

vector F = (m, m, . . . , m), which assigns the maximum executionfrequency, fm, to each real-time task (step 1). Also, at the beginning,all tasks are allowed to change their frequencies – we say that alltasks are unlocked (step 2). The main loop of the algorithm startswith (step 3) and executes until there are unlocked task (steps4–17). An each iteration of the algorithm, the frequency of one taskis decreased for one frequency level. To this end, the algorithmexplicitly checks each currently unlocked task, si (step 5). First,the frequency index of si is temporarily decreased for one fre-quency level, i.e. from xi to xi � 1 and then the schedulability testis performed using RTA for assumed value of parameter TF (steps6 and 7). This schedulability test has to ensure that fault-tolerantconstraint represented through parameter TF is met. If the new taskset C does not pass the RTA schedulability test (step 8), task si islocked (step 9). Otherwise, if the task sets remain schedulable,the difference between power consumption of task si at lowerðfxi�1Þ and higher ðfxi

Þ frequency is calculated (step 11), as

DPiðsiÞ ¼ PCðsi; xiÞ � PCðsi; xi � 1Þ

where

PCðsi; xiÞ ¼ Pd;xi� ðCi;xi

Þ=Ti

and

PCðsi; xi � 1Þ ¼ Pd;xi�1 � ðCi;xi�1Þ=Ti

are power consumption of task of si at higher ðfxiÞ and lower ðfxi�1Þ

frequency, respectively. Finally, si’s frequency index is changed backto xi (step 13). After checking all tasks, the one that remainsunlocked and provides the maximal power reduction is selected,and its frequency index is permanently decremented (step 16).Additionally, the selected task is locked if its new frequency indexequals 1, i.e. corresponds to the lowest execution frequency, f1. Afterthat, the algorithm enters the next iteration. The algorithm finisheswhen there are no more unlocked tasks. The frequency assignmentvector containing frequencies of locked tasks is the FT-DVFSalgorithm’s output.

Fig. 1. Proposed FT-D

We will explain our proposed FT-DVFS algorithm on a simpleexample. Suppose that we have set of 4 fully-specified task set,C = {s1, s2, s3, s4} that should be executed on a single CPU. Theoperating frequency of the CPU can be switched among three dis-crete values fj (j = 1, 2, 3), where f1 < f2 < f3 and f3 is the maximalfrequency. Given a set of four tasks and a set of three frequencies,there are 81 different mappings of the set of frequencies onto theset of tasks and accordingly the same number of different fre-quency assignment vector F. Instead of generating all different fre-quency assignment vectors, the proposed FT-DVFS algorithm leadsto a solution after only 10 iterations, Fig. 2.

The proposed FT-DVFS algorithm starts from the frequencyassignment vector F0 = (3, 3, 3, 3) which means that maximal fre-quency is assigned to each task. Initially, all tasks are unlocked.The first iteration of the algorithm temporary decreases the fre-quency of only one task for just one frequency level. Now we havefour candidates F1,1 = (2, 3, 3, 3), F1,2 = (3, 2, 3, 3), F1,3 = (3, 3, 2, 3)and F1,4 = (3, 3, 3, 2), among which one should be selected as thenew frequency assignment. First, the algorithm eliminates thosefrequency assignment vectors for which the task set does not passthe schedulability test. Suppose that task set does not pass theschedulability test when assigned with F1,2 and F1,3. Thereforethe algorithm locks the tasks s2 and s3. It means that frequenciesof tasks s2 and s3 are returned to f3 and could not be changedany more. Then, the algorithm calculates the gain in power con-sumption obtained when the task set is assigned with remainingfrequency assignment vector. Suppose that the reduction in powerconsumption is larger when the frequency of task s1 is changedfrom f3 to f2, then when the same frequency decrement is appliedto s4. Consequently, the algorithm eliminates F1,2, and enters thesecond iteration with F1,1 = (2, 3, 3, 3). The second iteration of thealgorithm starts by decreasing the frequency of the remaining un-locked tasks for one frequency level. This leads to two candidatesfrequency assignment vectors F2,1 = (1, 3, 3, 3) and F2,4 = (2, 3, 3,2). Suppose now that the task set is schedulable when assignedwith any of two candidate frequency assignment vectors, but the

VFS algorithm.

Fig. 2. The search paths for the frequency assignment vector come from four real-time tasks and three frequency levels.

Table 2Tasks set from Generic Avionics Platform.

Task si pi Ti = Di (ms) Ci (ms)

Nav_Status 1 1000 1BET_E_Status_Update 2 1000 1Display_Stat_Update 3 200 3Display_Keyset 4 200 1Display_Stores_Update 5 200 1Nav_Steering_Cmds 6 200 3Tracking_Target_Upd 7 100 5Display_Hook_Update 8 80 2Display_Graphic 9 80 9Nav_Update 10 59 8

1040 S. Djosic, M. Jevtic / Microelectronics Reliability 53 (2013) 1036–1042

power consumption is smaller with F2,4. Therefore, the algorithmeliminates F2,1, and keeps F2,4, in which both tasks, s1 and s4, areunlocked. After that, the algorithm starts with the third iterationand the frequency assignment vector F2,4 = (2, 3, 3, 2). Now candi-dates frequency assignment vectors are F3,1 = (1, 3, 3, 2) andF3,4 = (2, 3, 3, 1). Assume that the schedulability test is passed withboth frequency assignment vectors, and F3,4 is eliminated due tolarger power consumption than F3,1. Before entering the next iter-ation, the algorithm locks task s1 in F3,1, since this task has reachedthe minimum execution frequency f1. Because s4 is the onlyremaining unlocked task, there is a single candidate frequencyassignment vector F4,4 = (1, 3, 3, 1). Assume that the task set as-signed with F4,4 does not pass the schedulability test. Hence, thealgorithm locks the task s4 and returns its frequency to f2. Now,all tasks are lock and the algorithm finishes with the frequencyassignment vector F = (1, 3, 3, 2) as its final results. It means thattasks s1, s2, s3 and s4 should execute on CPU’s frequencies f1, f3,f3 and f2 respectively to satisfy: real-time timing requirements,fault-tolerant constraints and power reduction demands.

4. Simulation results

In this section, we analyze the performance of our proposed FT-DVFS algorithm by simulation in a custom simulator build in C++.The processor model we used in our simulations is based on theTransmeta Crusoe processor with DVFS capability [39]. The CPUfrequency, voltage and power levels are depicted in Table 1. Theoperating CPU frequency is in the range from 300 MHz to667 MHz. Decreasing the clock frequency of the processor allowsthe corresponding reduction of the supply voltage from 1.6 V formaximum down to 1.2 V for minimum operating frequency. Notethat the reduction of operation frequency from 667 MHz to300 MHz, i.e. for 2.23 times, leads to reduction of power consump-tion for 4.07 times.

We performed simulations with a number of synthesized real-time task sets and few real-world applications. Our evaluations,presented here, are based on the simulations of a task set takenfrom the Generic Avionics Platform (GAP) previously used in[40]. The task set consists of ten real-time tasks listed in Table 2.

Table 1Frequency, voltage and power levels for Transmeta Crusoe processor.

Frequency (MHz) Voltage (V) Power (W)

300 1.200 1.3400 1.225 1.9533 1.350 3.0600 1.500 4.2667 1.600 5.3

Each task is characterized with the following parameters: priority(pi), period (Ti) and execution time (Ci). The priorities of the tasksare assigned according to the earliest deadline first algorithm. Also,deadline of each tasks equals task’s period, i.e. Ti = Di. The parame-ter Ci refers to execution time on maximum processor operatingfrequency. Also, fault-tolerant constraint, which is representedthrough parameter TF, is the input data for our simulator.

Since the main purpose of the proposed FT-DVFS algorithm is toreduce energy consumption of fault-tolerant real-time systems,the simulation results are analyzed from the energy consumptionpoint of view. Performance is evaluated in terms of normalizedpower reduction, which is defined as ratio of power consumptionwhen tasks are executed at maximum frequency (with no DVFS)and power consumption when tasks are executed on frequenciesdetermined by the proposed FT-DVFS algorithm, in percentage.

First, we assumed that there are no faults in the system. Withthis assumption, we apply our proposed FT-DVFS algorithm to findthe execution frequency for each real-time task that lead to themaximum energy savings. The effectiveness of our proposed FT-DVFS algorithm when applied on RTS with no faults is presentedin Fig. 3. We used GAP task set (Table 2) and different number ofCPU frequency levels (Table 1). A bar in Fig. 3, labeled with i,i = 2, . . . ,5 represents the normalized power reduction as achievedby using a subset of i frequency levels chosen from the set of allow-able frequencies (Table 1).

According to results presented in Fig. 3, we can conclude thatthe proposed FT-DVFS algorithm achieves a significant energyreduction even with a small number of available frequency levels.As can be seen, only two frequency levels are sufficient to save31.5% of energy. The power reduction increases with the increaseof the number of frequency levels and reaches 42.8% when allavailable frequencies are utilized. With larger number of frequencylevels there are more possible task-frequency mapping, so thechance of finding solutions with lower energy becomes higher.

Next, we present the result concerning the performance of ourproposed FT-DVFS algorithm in the presence of faults. Let TFmax

be the minimum time interval between two consecutive faults thatthe task set can tolerate assuming that all tasks execute at maxi-mum frequency. As we mentioned before, in the RTA the fault-tol-erance capability of a RTS is represented by a single inputparameter, TF, which corresponds to minimum time interval be-tween two consecutive faults that the RTS has to tolerate. Thus,the desired level of fault-tolerant capability of a RTS is specifiedthrough TF. We defined the normalized fault tolerance capability(NFTC) as the ratio between the maximum and desired fault toler-ance capability, i.e. TFmax/TF.

TFmax is precalculated value and it corresponds to the minimumtime interval between two consecutive faults that the RTS can tol-erate assuming that all tasks execute at maximum frequency. TF isas input variable and it corresponds to the minimum time intervalbetween two consecutive faults that the RTS should tolerate. Itranges from infinity down to TFmax.

Fig. 3. Normalized power consumption versus number of frequency levels in theabsence of faults. Notice: bar #2 (667 MHz, 300 MHz), bar #3 (667 MHz, 600 MHz,300 MHz), bar #4 (667 MHz, 600 MHz, 533 MHz, 300 MHz), bar #5 (667 MHz,600 MHz, 533 MHz, 400 MHz, 300 MHz).

Fig. 5. Normalized power consumption for five frequency levels (667 MHz,600 MHz, 533 MHz, 400 MHz, 300 MHz) in the presence of faults obtained by theFT-DVFS algorithm and the method of exhaustion.

S. Djosic, M. Jevtic / Microelectronics Reliability 53 (2013) 1036–1042 1041

Thus, limit values for NFTC are 0 and 1. With NFTC = 0 (i.e. whenTF is set to infinity) RTS is not expected to tolerate any fault. In thatcase we are only concerned with the minimization of energy con-sumption saving and completely reject the fault tolerant aspect. Bysetting NFTS = 1 (i.e., TF = TFmax), we expect that RTS achieves themaximum possible level of fault tolerance, without regard to en-ergy consumption. If TF > TFmax then time redundancy can be usedfor both the energy management and the fault tolerance.

The time redundancy is a limited resource, so it is obvious thatif more time redundancy is used for energy management, thenthere is a less time available for fault tolerance, and vice versa.The tradeoff between low energy consumption and high fault tol-erance is solved by our proposed FT-DVFS algorithm.

Fig. 4 depicts the normalized power reduction versus NFTC fordifferent number of available frequency levels. We used a subsetof i, i = 2, . . . ,5 frequency levels chosen from the set of allowablefrequencies given in Table 1 (see caption of Fig. 4). As expected,the higher the NFTC, the lower power savings and vice versa. Also,these results show that the power reduction increases with thenumber of frequency levels. For example, if NFTC is equal to 0.5then power reduction reaches 35% when all available frequenciesare utilized. If only two frequency levels are utilized then powerreduction is about 15%.

The simulation analysis also showed that our proposed FT-DVFSalgorithm achieves near-optimal solutions in acceptable computa-tion time. Fig. 5 depicts the normalized power reduction versus

Fig. 4. Normalized power consumption versus number of frequency levels in thepresence of faults. Notice: 2 levels (667 MHz, 300 MHz), 3 levels (667 MHz,600 MHz, 300 MHz), 4 levels (667 MHz, 600 MHz, 533 MHz, 300 MHz), 5 levels(667 MHz, 600 MHz, 533 MHz, 400 MHz, 300 MHz).

NFTC for Generic Avionics Platform task set (Table 2) and all fivefrequency levels (Table 1) as achieved with the heuristic FT-DVFSalgorithm and an optimal algorithm based on the method ofexhaustion. As can be seen, the heuristic FT-DVFS algorithm attainsthe optimal results when it is primarily focused on either reducingpower consumption (TFmax/TF < 0.3) or maximizing fault-tolerancecapability (TFmax/TF > 0.8). The problem of finding the optimum fre-quency assignment is much harder to solve when the pre-specifiedTF gives more freedom in selecting tasks’ frequencies (0.3 < TFmax/TF < 0.8). Although, the heuristic FT-DVFS algorithm cannot achievethe optimal solutions under such fault-tolerance constraints, theperformance drop in term of power reduction does not exceed5%. On the other hand, the computation time taken by the heuristicFT-DVFS algorithm is less than a second, even when it is applied onlarge task sets (more than 30 tasks), in contrast to the optimal algo-rithm which takes several hours to generate the solution even forrelatively small task sets.

5. Conclusions

In this paper we have considered the trade-off problem be-tween energy-efficiency and fault tolerance for the real-time sys-tems. The trade-off arises from the fact that techniques, powerreduction and fault tolerance exploit slack time to decrease energyconsumption and to improve reliability, respectively. In accor-dance with this problem we realized a heuristic-based algorithm,named FT-DVFS. This algorithm combines dynamic voltage and fre-quency scaling technique, for optimizing energy consumption, andresponse time analysis for schedulability and fault tolerance. TheFT-DVFS algorithm assigns each real-time task an operating fre-quency so that the total power consumption is minimized whilekeeping the real-time task set schedulable under fault-tolerantconstraint. The simulation results have shown that the proposedalgorithm saves a considerable amount of energy compared tothe solution without considering energy. Another advantage ofthe proposed approach is that it achieved near-optimal solutionsin acceptable computation time. We compared the proposed FT-DVFS algorithm with an optimal algorithm based on the methodof exhaustion and showed that the performance drop in term ofpower reduction does not exceed 5%. For the future work, we planto extend the proposed algorithm to multiprocessors real-timesystems.

Acknowledgment

This paper was supported by Project Grant III44004 financed byMinistry of Education and Science, Republic of Serbia.

1042 S. Djosic, M. Jevtic / Microelectronics Reliability 53 (2013) 1036–1042

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