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Dynamic Voltage/Frequency Scaling Dynamic Voltage/Frequency Scaling in Loop Accelerators using BLADESin Loop Accelerators using BLADES

Ganesh Dasika1, Shidhartha Das2, Kevin Fan1,Scott Mahlke1, David Bull2

1

1University of MichiganAdvanced Computer

Architecture LaboratoyAnn Arbor, MI

2ARM Ltd.Cambridge

United Kingdom

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IntroductionIntroduction

2

[Austin, IEEE Computer March 04]

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RazorRazor

• Allows for voltage/frequency scaling beyond first-failure point• Exploits difference between design-time conditions (“slow”) and

actual conditions (“typical”)

3

[Das, JSSC 2006]

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Razor in General Purpose ProcessorsRazor in General Purpose Processors

• Requires detailed analysis of microarchitectural impact– Analyze what state should be stored– Lengthening pipeline for stabilization increases

complexity of forwarding logic• Unpredictable control and data flow• Difficult to determine worst-case vectors

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BLADESBLADES

• Better-than-worst-case Loop Accelerator Design• Incorporate DVFS into ASICs using Razor

– Shave off some of the high NRE using HLS– Develop generic methodology for any application– Razor solution for a templated architecture

• Create ASIC design flow that is aware of Razor-ization costs

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Loop Accelerator TemplateLoop Accelerator Template

• Hardware realization of modulo-scheduled loop• Parameterized execution resources, storage, connectivity• Control is statically determined, simple and not timing-critical• Opportunity to make application-specific optimizations

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Razorized Loop AcceleratorRazorized Loop Accelerator

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Razor++ **++ **

Extended register queues

Addedinterconnect

“Roll-back” muxes

} R

R is the number of extra entries required

Function of max pipeline depth and error-detection delay

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Error “Life-Cycle”Error “Life-Cycle”

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Razor++ **++ **

Error Reset

Error

…

Error OR-tree Error stabilization

Roll-backpipelining

…

++Error

processing

Control

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Issues with RazorIssues with Razor

• Area, added hold-fixing

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tspec

D

CLK

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Or1Or1Or0Or0FU 1

Add1Add1Add0Add0FU 0

Time 5Time 4Time 3Time 2Time 1Time 0

Or1FU 3

Or0FU 2

Add1FU 1

Add0FU 0

Time 2Time 1Time 0

Add-Or1Add-Or0FU 0

Time 3Time 2Time 1Time 0

Or1Or0FU 1

Add1Add0FU 0

Time 2Time 1Time 0

50% FU utilization removes hold-fixing need, but requires halving performance or doubling area

Use hybrid scheme to execute >2 ops per FU

++

II

Opcode-chainingOpcode-chaining

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Identifying Opcode ChainsIdentifying Opcode Chains• Compiler identifies

subgraphs of 3-4 input, 1 output instructions– All arith. ops supported

• Greedy selection algorithm

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<<<< <<<<

++++

>>>>

+

>>>>

++++

++

++

&&

STST

&&

STST

>>>>

++

<<<< ++

<<<<

LDLD

>>>>

LDLD

1 2

3

4 5

6

7

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Custom FUsCustom FUs

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<<<< <<<<

++++

>>>>

+

>>>>

++++

++

++

&&

STST

&&

STST

>>>>

++

<<<< ++

<<<<

LDLD

>>>>

LDLD

1 2

3

4 5

6

7

<<<< <<<<

++++

>>>>

+

>>>>

++++

++

++

&&

STST

&&

STST

>>>>

++

<<<< ++

<<<<

LDLD

>>>>

LDLD

1 2

3

4 5

6

7

>>

+

+

<<

+

Enabled every2 cycles

Razor DFF

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ResultsResults

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idct, sharp, systolic_dct had multiple CFUs, and overall lower # of FUsViterbi, dequant had signficant control-flow that restricted opportunities for creating custom ops

22% reduction in hold-fixing overhead in sobel

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ConclusionConclusion

• Application-specific optimizations definitely help to mitigate Razor costs– 24% reduction in overhead– 33% energy savings overall

• Can optimize Razor-ization with further input from the compiler– Critical-instruction analysis– Error impact analysis

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Thank you!Thank you!

15

http://cccp.eecs.umich.edu

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Future WorkFuture Work

• Errors in different FUs affect the system differently– Error “impact-analysis”– Data computation not necessarily error-sensitive– Address, branch target/direction critical to functionality

• Razor-ization of arbitrary Verilog

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MotivationMotivation

• Using Razor has significant design overhead– Error-recovery system– Added “backup” state– Additional hold-time fixing

• Modifications for different u-archs are different• Information about work-load cannot be used since

design must preserve generality

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++ **