dynamically reconfigurable architecture for third generation mobil systems ahmad alsolaim ohio...

Dynamically Dynamically Reconfigurable Reconfigurable

Architecture for Third Architecture for Third Generation Mobil SystemsGeneration Mobil Systems

Ahmad AlsolaimAhmad Alsolaim

Ohio UniversityOhio University

School of of Electrical School of of Electrical Engineering and Computer Engineering and Computer

ScienceScience

School of Electrical Engineering and Computer Science

Tuesday, April 18, 2023 2

OutlineOutline

IntroductionIntroduction Third and Future Generations Mobile SystemsThird and Future Generations Mobile Systems WCDMA Baseband Signal ProcessingWCDMA Baseband Signal Processing Computing Architecture ModelsComputing Architecture Models Dynamically Reconfigurable Architecture Dynamically Reconfigurable Architecture

DRAW !DRAW ! Dynamically Reconfigurable Architecture Dynamically Reconfigurable Architecture

DesignDesign Mapping Examples Mapping Examples Conclusion and RecommendationsConclusion and Recommendations



Introduction Introduction

Wireless broadband access Wireless broadband access techniques challenges: techniques challenges: Access mechanisms, Access mechanisms, Energy conservation, Energy conservation, Low error rate, Low error rate, Transmission speed characteristics, Transmission speed characteristics, Small size, Light weight, Long battery Small size, Light weight, Long battery

life, and Low cost.life, and Low cost.



Introduction Introduction

AdaptabilityAdaptability Many standards: Many standards:

WCDMA, IS-95, cdma2000, ...etcWCDMA, IS-95, cdma2000, ...etc

FlexibilityFlexibility Many services within one standard:Many services within one standard:

voice, audio/video, data, GPS, …etc.voice, audio/video, data, GPS, …etc.



Introduction (Cont’d)Introduction (Cont’d) Future generations mobile terminals will be Future generations mobile terminals will be

implemented with a System-on-a-Chip (SoC)implemented with a System-on-a-Chip (SoC)

Storage Unit

General Purpose Micro-Processor

ReconfigurableModule

SpecialProcessing

Unit

I /O Module

Digital SignalProcessor

Peripherals

Configurable System-on-a-Chip (CSoC)



Introduction (Cont’d)Introduction (Cont’d)

Reconfigurable Architectures:Reconfigurable Architectures: Fine-grain reconfigurable architectures Fine-grain reconfigurable architectures

Commercial FPGAs like Xilinx 4000 FPGA family, Commercial FPGAs like Xilinx 4000 FPGA family, and Altera Flex 8000 FPGA familyand Altera Flex 8000 FPGA family

Coarse-grained architecturesCoarse-grained architectures:: PADDI-2, PipeRench, Morphosys, Grap, PADDI-2, PipeRench, Morphosys, Grap,

KressArray, and Colt.KressArray, and Colt.

Special commercial RA for Special commercial RA for communication applications:communication applications: QuickSilver , and Chameleon CS2000QuickSilver , and Chameleon CS2000



Third and Future Third and Future Generations Mobile Generations Mobile

SystemsSystemsProposal Description Source DECT Digital Enhanced Cordless

Telecommunications ETSI Project DECT

UWC-136 Universal Wireless Communications USA TIA TR45.3 WIMS W-CDMA

Wireless Multimedia and Messaging Services Wideband CDMA

USA TIA TR46.1

TD-SCDMA Time-division synchronous CDMA China CATT W-CDMA Wideband CDMA Japan ARIB CDMA II Asynchronous DS-CDMA S. Korea TTA UTRA UMTS Terrestrial Radio Access ETSI SMG2 NA: W-CDMA North American: Wideband CDMA USA T1P1-ATIS cdma2000 Wideband CDMA (IS-95) USA TIA TR45.5 CDMA I Multi band synchronous DS-CDMA S. Korea TTA



Characteristics of Characteristics of WCDMAWCDMA

WCDMA standard has two modes for the WCDMA standard has two modes for the duplex method. A Frequency Division duplex method. A Frequency Division Duplex (FDD) and Time Division Duplex Duplex (FDD) and Time Division Duplex (TDD).(TDD).

W-C

DM

A U

plin

k(F

DD

)

1920

W-C

DM

A (T

DD

)19

00

MS

1980

W-C

DM

A (T

DD

)20

10

2025

W-C

DM

AD

ownlink (F

DD

)

2110

MS

2170

2200

Uplink DownlinkGuard



Characteristics of WCDMA Characteristics of WCDMA (Cont’d)(Cont’d)

Channel bandwidth

5 MHz

Duplex mode FDD and TDD

Chip rate 3.84 Mcps

Frame length 10 ms

Spreading modulation

Balanced QPSK (downlink) Dual-channel QPSK (uplink)

Data modulation QPSK (downlink) BPSK (uplink)

Channel coding Convolutional and turbo codes

Coherent detection

User time multiplexed pilot (downlink and uplink), common pilot in the downlink

Spreading factors

4–256 (uplink), 4–512 (downlink)

Spreading (downlink)

OVSF sequences for channel separation Gold sequences 218-1 for cell and user separation (truncated cycle 10 ms)

Spreading (uplink)

OVSF sequences, Gold sequence 241 for user separation (different time shifts in I and Q channel, truncated cycle 10 ms)



Characteristics of WCDMA Characteristics of WCDMA (Cont’d)(Cont’d)

Data 1 TPC TFCI Data 2 Pilot

284 8 8 1000 16

Number ofbits

Tslot = 2560 Chips, 10*2K bits (K = 0 to 7). Shown is the maximum numberof data bits.

Transmission Power ControlTransmitted Format Control

Indicator

Slot #1 Slot #2 Slot #3 ... Slot #15

Frame #1 Frame #2 Frame #3 ... Frame#72

1 Radio Frame, 10 ms, 38400 chips (3.84 Mcps)

Time

Time

72 Radio Frame, Super Frame



Future Generations Future Generations wireless Systemswireless Systems

Future Generation Mobile SystemsFuture Generation Mobile Systems

2nd

GenerationsGSM

CDMA

IMT-20

00

3rd

Genera

tion

Bro

adba

ndW

irel

ess

Loc

al L

oop

4th

Gen

erat

ion

Transmission rate Mbps0.01 0.10 1.00 10.0 100

Mob

ilit

y

2G 3G 4G



WCDMA Baseband Signal WCDMA Baseband Signal ProcessingProcessing

RFUnit

IF Unit BPF 90o fc

A/D

A/D

BasebandUnit

I

Q

I

Q

To Upperlayers

Digital Baseband




A/D

A/D

DigitalBaseband

Channelization

Digital LPF(RRC)

RAKE

Searcher




RAKE

Searcher

MaximalRatio

Combining

ChannelEstimation

... TurboDecoder

ConvolutionDecoder

Un-encodedChannels

Channel Decoding

Other Functions: Power control, Finger allocation,Tracking, Rate matching, ..etc

To upperlayers




Baseband Signal Processing Baseband Signal Processing RequirementsRequirementsFunctionFunction Number of Million Number of Million

Instructions per Second Instructions per Second (MIPS) @ 384 Kbps(MIPS) @ 384 Kbps

Digital Filters (RRC, Digital Filters (RRC, Channelization)Channelization)

~3600 MIPS~3600 MIPS

Searcher (Frame, slot, delay path, Searcher (Frame, slot, delay path, etc.)etc.)

~1500~1500

RAKE ReceiverRAKE Receiver ~650~650

Turbo codingTurbo coding ~52~52

Maximal Ratio Combiner (MRC)Maximal Ratio Combiner (MRC) ~24~24

Channel estimationChannel estimation ~12~12

AGC, AFCAGC, AFC ~10~10

De-interleaving, rate matchingDe-interleaving, rate matching ~14~14

TOTAL ~5860




Digital FiltersDigital Filters

Z-1 Z-1Z-1Z-1Z-1

C0 C1 C2 C3 C4

Y output

X inputTappedDelay Line

CoefficientConstantMultipliers

AdderTree




SearcherSearcher

Code Group # 1

Code Group # 2

Code Group # 3

Code Group # 32

...Group of 16

scrambling codes

HAWQXCDOWTMKRSWV

16 letter word which is apointer to a code group

One slot= 0.666ms

PrimarySCH

SecondarySCH

Same code (256 chips) repeated in every slot and arethe code is the same for every cell in the system

Toffset

...

...

Distinctive code (256 chips) in each slot, the code determines the slotnumber in the frame. In addition the code is modulated by 16 bit

word which points to the group of the cell scrambling code.

One frame 10 ms




MATLAB Simulation of PSCH searcher MATLAB Simulation of PSCH searcher

360 370 380 390 400 410 420 430 440 450 460

0

50

100

150

200

250Peak at chip number 413

PSCH




RAKE Receiver and Maximal Ratio RAKE Receiver and Maximal Ratio CombiningCombining

Align

ing

Correlation arm 1

Delay1/Rc

ChipMatched

Filter

Synchronizationand control

PN Generator

+

Correlation arm 2

Correlation arm 3

...aL

a3

a2

a1

...

Delay1/Rc

Delay1/Rc

I and Q PathsData Out

Decision

Correlation arm L




RAKE finger correlation armRAKE finger correlation arm

Output ofcorrelator arm

C2[n]_

I branch

Q branch

C1[n]

C1[n]




Turbo encodingTurbo encodingD D D

Turbo CodeInternal

Interleaver

D D D

S

P1

P2

Xk’

Input

1st constituent encoder

2nd constituent encoder

S




Turbo decoderTurbo decoder

SISODecoder 1

Interleaver

Interleaver

SISODecoder 2

De-Interleaver

P1i

‘

P2i

‘

Si

‘

uK




MATLAB turbo simulationMATLAB turbo simulation

0 10 20 30 40 50-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 50 100 150-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 10 20 30 40 50-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

Turboencoder Channel

Turbodecoder

InputOutput



Computing Architecture Computing Architecture ModelsModels

Current computer Current computer architecturesarchitectures

ASIC ASIC implementationimplementation

DSP DSP ImplementationImplementation

FPGA FPGA ImplementationImplementation

FPGASynthesis

ASICSynthesis

Compiler

DSPImplement(Place and

Route)

Fabricate

VLSI Layout

FPGA

ASIC

Natural description of the algorithm

HDL languageC Language or

assemply




Why Dynamically Reconfigurable Why Dynamically Reconfigurable Computing?Computing?

ProcessorPerformance

(log scale)

1G

2G

3GAlgorithmic Complexity

Shannon’s Law

ProcessorComplexityMoore’s Law

Time (years)




Why Dynamically Reconfigurable Why Dynamically Reconfigurable ComputingComputing

ReconfigurableComputing

ASIC DSP

Flexibility

Performance




Why Why Dynamically Dynamically ReconfigurablReconfigurable Computinge Computing

IP-based IP-based MappingMapping

FlexibilityFlexibility

Area, Power, Area, Power, and Costand Cost

IP Mapping

...

IP1 IP2 IP3 IPn

DynamicallyReconfigurableArchitecture

RunningIPProcessing

element

Pre-compiled IPs



Dynamically Reconfigurable Dynamically Reconfigurable ArchitectureArchitecture

The Dynamically The Dynamically Reconfigurable Reconfigurable Architecture Architecture (DRAW) Model(DRAW) Model

CommunicationPlane

I/O Plane

u1

x2

x1

* / *

33 MHz

100101001100101001001010010110010010010011

000100101001100101001001010010110010010010011

000

100101001100101001001010010110010010010011

000

ControlPlane

ProcessingPlane

ConfigurationPlane



Introducing Introducing DRAWDRAW

DRAW consists of:DRAW consists of: Coarse-grained Dynamically Coarse-grained Dynamically

Reconfigurable Processing Units (DRPUs)Reconfigurable Processing Units (DRPUs)

Communication NetworkCommunication Network

Dedicated I/ODedicated I/O

Fast Dynamic ReconfigurationFast Dynamic Reconfiguration




Control lines

16-bit Global data linesConfiguration lines

16-bit Local data lines

DIO

Global routing linesLocal routing lines

CSU

Global Control UnitGCU

CMUDRPU SWBSWB




DRAW consists of an array of parallel operating DRAW consists of an array of parallel operating coarse-grained Dynamically Reconfigurable coarse-grained Dynamically Reconfigurable Processing Units Processing Units (DRPUs)(DRPUs)

Regular and Simple Array StructureRegular and Simple Array Structure

Special Processing UnitsSpecial Processing Units

Configurable Linear Feedback Shift Register Configurable Linear Feedback Shift Register (CLFSR)(CLFSR)

Configurable Spreading Data Path (CSDP)Configurable Spreading Data Path (CSDP)

RAM and FIFO StorageRAM and FIFO Storage

Scale and DelayScale and Delay



Designing Designing DRAWDRAW

MATLABsimulation of thereceiver functions

Matlab code

Desin of the DynamicallyReconfigurable Architecture

DRAW

VHDL funtional and timingsimulation

Final VHDL description ofDRAW

VHDL code

SynthesisLeonardoSpec

(Fujtisu CS71 0.25 Micron )

Mapping application ontoDRAW



Designing Designing DRAWDRAW Operation ProfileOperation Profile

Text2Bin.m

DataGeneration

Wlsh_gen.m

Any_bits.m

dl_sc_code.m

concatenation.m

CHKwcdmaCRC.m

wcdmaCRC.m

GOLD_SEQ.m

m_r_comp.m

dat_gen_img.m

Coars_CH_EST.mch_estm.m

de_itrlvg.m

demodulator.m

ssc_group_frame.m

sRAKE.m finger.m

sercher.m

ser2parl.m

segmentation.m

wcdma_turbo_ntrlvr.m

sec_sync_code.m

wcdma_turbo_coder.m

PSCH.m

SSCH.m

pri_sync_code.m

Mgen.m

mod1bit.m

modulatora

rrcf.m

Scrambling

wcdma_turbo_de_coder.m

rrcf.m

De-Scrambling

Channel.m

Bin2Text.m

Wlsh_gen.m

Data Recovery

Input

Output

Data 1 TPC TFCI Data 2 Pilot

284 8 8 1000 16

Number ofbits

Total bits = 1,280Spreading factor = 4

Total number of chips = 1,280 x 4 = 5,120 chips/slotChannel rate is 1,280 x 15 slots = 1,920 Kbps

TransmissionPower Control

Transmitted FormatControl Indicator




Operation ProfileOperation ProfileNumber of Ops vs. Ops type per one RF slot

1

10

100

1000

10000

100000

AD

D/S

UB

MU

L

ME

M

SH

FT

LG

CL

MA

X/M

IN

Ops type

Nu

mber

of O

ps

MRC RAKE FIR TURBO SEARCH




Operation ProfileOperation ProfilePercentage Number of Ops vs. Op Type

01020304050607080

AD

D/S

UB

MU

L

ME

M

SH

FT

LG

CL

MA

X/M

IN

Operation Type

Perc

en

tage o

f to

tal ops.




Operation ProfileOperation Profile

Number of interconnections vs. interconnection type

0

20

40

60

80

100

120

1 to 1 1 to 2 1 to 3 1 to 4 1 to 5

Interconnection type

Num

ber

of

inte

rcon

nec

tion

s

MRC RAKE FIR TURBO SEARCH




Review of 3GPP WCDMAReview of 3GPP WCDMA A transmitter block diagramA transmitter block diagram

Modulation

RRCFilter

RRCFilter

NCOBasebandTransmitter

FilterDAC

CRC

FEC Encoder

ConvolutionalEncoder

Turbo Encoder

BlockInterleaver

Cahnnalizationcode (OVSF)

ScramblingCode

IncomingData bits

RF Unit




Review of 3GPP WCDMAReview of 3GPP WCDMA A receiver baseband block diagramA receiver baseband block diagram

DAC Demodulator

MultipathEstimation

De-spreadMultipathCombining

De-interleaving

FEC Decoder

ConvolutionalDecoder(Viterbi)

Turbo Decoder

CRC

RF Unit

ReceivedData bits

Errorindecation



Designing Designing DRAWDRAW Review of 3GPP WCDMAReview of 3GPP WCDMA

3GPP downlink scrambling code generator3GPP downlink scrambling code generator

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I

Q




Review of 3GPP Review of 3GPP WCDMAWCDMA De-spreading De-spreading

circuit for QPSKcircuit for QPSKIntegrator

+

Integrator

+

Integrator

Integrator

I

Q

Data I

Data Q

I codeQcode

Dump

Integrator

+

Integrator

+

Integrator

Integrator

I

Q

Data I

Data Q

I code Qcode

Dump

-

(b)



DRAWDRAW

Dynamically Reconfigurable Dynamically Reconfigurable Processing Unit (DRPU)Processing Unit (DRPU)

One 16-bit Dynamically Reconfigurable One 16-bit Dynamically Reconfigurable Arithmetic Processing unit (DRAP), Arithmetic Processing unit (DRAP),

One Configurable Spreading Data Path (CSDP),One Configurable Spreading Data Path (CSDP), One Configurable linear Feedback Shift One Configurable linear Feedback Shift

Register (CLFSR),Register (CLFSR), One DRPU controller, One DRPU controller, One dual port RAM/FIFO, andOne dual port RAM/FIFO, and Two I/O interfaces. Two I/O interfaces.



DRAWDRAW

DRPUDRPU

DRAP

Output Interface

Input Interface

Shift, Rotate, andMux Unit (SRMU)

RAM/FIFO

RAM/FIFOInterface

CLFRCSDP

DRAP Interface

CLFSR connectionsto other DRPUs CLFSR connections

to other DRPUs

Six input data lines, 16 bit each Two from the global lines and four from local

DRPU neighbors. Four Start_Hold control signals from neighboring

DRPUs Four CARY signals from neighboring DRPUs

Control Unit

Six data lines, 16 bit each. Two to the global lines and four to the neighboring DRPUs

Four Start_Hold control signals to neighboring DRPUs. 1 biteach.

One CARY signals to neighboring DRPUs. 1 bit.

16-bit data line

1 bit control line

1 bit serial data tothe neighboringDRPU for theCLFSR unit.



DRAWDRAW Dynamically Reconfigurable Dynamically Reconfigurable

Arithmetic Processing unit (DRAP)Arithmetic Processing unit (DRAP)

DRAP

Output Interface

Input Interface

Shift, Rotate, andMux Unit (SRMU)

RAM/FIFO

RAM/FIFOInterface

CLFRCSDP

DRAP Interface

Control Unit

CLFSR_OUT_1_LFTCLFSR_OUT_1_RGT

DRPU_DONEIN_E_RPU(DATA_PATH_WIDTH-1:0)IN_N_RPU(DATA_PATH_WIDTH-1:0)IN_S_RPU(DATA_PATH_WIDTH-1:0)

IN_W_RPU(DATA_PATH_WIDTH-1:0)RPU_OUT_1_GBUS(DATA_PATH_WIDTH-1:0)RPU_OUT_2_GBUS(DATA_PATH_WIDTH-1:0)

RPU_START_HOLD_ERPU_START_HOLD_NRPU_START_HOLD_S

RPU_START_HOLD_W

CARRY_IN_FROM_E

CARRY_IN_FROM_N

CARRY_IN_FROM_S

CARRY_IN_FROM_W

CLFSR_IN_1_LFT

CLFSR_IN_1_RHT

CLK

CONFIGURATION_BITS(DRPU_CONFIG_BITS_WIDTH-1:0)

GO_CONFIG

GO_HOLD

GO_RUN

GO_SLEEP

IN_FROM_E_RPU(DATA_PATH_WIDTH-1:0)

IN_FROM_N_RPU(DATA_PATH_WIDTH-1:0)

IN_FROM_S_RPU(DATA_PATH_WIDTH-1:0)

IN_FROM_W_RPU(DATA_PATH_WIDTH-1:0)

IN_G_1_BUS(DATA_PATH_WIDTH-1:0)

IN_G_2_BUS(DATA_PATH_WIDTH-1:0)

SRART_HOLD_FROM_E

SRART_HOLD_FROM_N

SRART_HOLD_FROM_S

SRART_HOLD_FROM_W

T_ENABLE

T_RESET

DRPU top level

ALU

1

2

9

10

11

MAX/MIN12

13

3

4

5

67

8

DRAP_X_IDRAP_Y_I

DRAP_OUT

0 1 22 1 0

0 1 2

BoothDecoder

14 to 22

2 3 41

1 Shift direction of the right barrel-shifter

2 Number of shifts of the right barrel-shifter

3 Shift direction of the left barrel-shifter

4 Number of shifts of the left barrel-shifter



DRAWDRAW DRAP DRAP

operationsoperations# Operation Description

1 MUL 2’s complement multiplication

2 ADD 2’s complement addition

3 SUB 2’s complement subtraction

4 SHIFT Logic & arithmetic shift

5 AND Bit-wise AND

6 NAND Bit-wise NAND

7 OR Bit-wise OR

8 NOR Bit-wise NOR

9 XOR Bit-wise XOR

10 XNOR Bit-wise XNOR

11 NOT Bit-wise NOT

12 MAX Maximum

13 MIN Minimum



DRAWDRAW

The DRPU controllerThe DRPU controllerCRNT_STATE

RESET

HOLD

CONFIG

SLEEP

GO_CONFIG = '1'

RESET_CTROL = '1'

DRPU_FULL_CONFIG_BITS< =( others = >' 0' ) ;

ENABLE_DRPU< ='0';

DISABLE_CLK< = '0'; -- Clock is ENABLED

CONFIGURED< = '0';

DRPU_FULL_CONFIG_BITS< =( others = >' 0' ) ;

ENABLE_DRPU< ='0';


CONFIGURED< = '0';

-- Add here any signal you want to keep it

-- active as long you are in this stste

RESET_DRPU< = '1';

DRPU_DONE< = '0';

RAM_RD< = '0';

RAM_WR< ='0';

DRPU_START_HOLD< = '0';

DRPU_DONE< = '0';

-- Add here any signal you want to keep it

-- active as long you are in this stste

RESET_DRPU< = '1';

DRPU_DONE< = '0';

RAM_RD< = '0';

RAM_WR< ='0';

DRPU_START_HOLD< = '0';

DRPU_DONE< = '0';

GO_SLEEP = '1'

GO_HOLD = '1' GO_HOLD ='1'

GO_HOLD ='0'

GO_SLEEP = '1'

GO_SLEEP = '0

-- Befor exit this state set configured to 1

CONFIGURED< = '1';

ENABLE_DRPU< = '1';

-- Befor exit this state set configured to 1

CONFIGURED< = '1';

ENABLE_DRPU< = '1';

CONFIGURED< = '0';CONFIGURED< = '0';

GO_RUN ='1'

GO_RUN ='0'

DRPU_FULL_CONFIG_BITS< = CONFIGURATION_BITS;DRPU_FULL_CONFIG_BITS< = CONFIGURATION_BITS;

ENABLE_DRPU< = '0';ENABLE_DRPU< = '0';

RESET_DRPU< = '1';RESET_DRPU< = '1';

DISABLE_CLK< = '0';DISABLE_CLK< = '0';

ENABLE_DRPU< = '1';ENABLE_DRPU< = '1';

ENABLE_DRPU < = '0';

DISABLE_CLK< = '1';

ENABLE_DRPU < = '0';

DISABLE_CLK< = '1';

RESET_DRPU< = '0';

DRPU_DONE< = '0';


RESET_DRPU< = '0';

DRPU_DONE< = '0';


RUN



DRAWDRAW

The RAM/FIFO The RAM/FIFO UnitUnit

RAM/FIFO Unit

CLEAR

CLK

ENABLE

Configuration

ADRS A

ADRS B

RW

RD

DATA A

DATA B

OUT A

OUT B

FIFO_FULLFIFO EMPTY

ENABLE

Configure RAM/FIFO to a FIFO

function

NO

NewDATA?

YES

NO

START

Write the data atthe bottom to

Port B

Hold FromReceiving DRPU?

YES

NO

Is FIFOFull?

IS FIFOEmpty

NO

YES

YESAssert

Output Holdsignal to hold

sendingDRPU

De-assert OutputHold signal to hold

sending DRPU

Read new dataword through

port A andstore it at the

top of the FIFO

YES

NO

NewConfiguration?

WRITE Cycle

READ Cycle



DRAWDRAW

The Configurable Spreading Data Path The Configurable Spreading Data Path (CSDP)(CSDP)

1 Bit

16 Bit 16 Bit

One CSDP unit.

Data 2 Output Data

Data 1

1 Bit

16 Bit 16 Bit

Spreading configuration. 1 bit of data is spreadedby 16 chips of PN code, spreading gain in this case

is 16/1

At thetransmitter

Output DataPN

Data



DRAWDRAW

1 Bit

16 Bit 16 Bit

De-spreading configuration. One datasymbol word (16 bit) is de-spreaded by1 chips of PN code. The accumulatorACC accumulates data for one data

period.

ACC Unit withdumping

period of TNOutput Data

PN

Data

At thereceiver

+

+

I

Q

Complex spreading configuration.Utilized in QPSK modulation

Data I

Data I

Data I I

Data I I

PN 2

PN 1

PN 2

PN 1

The Configurable The Configurable Spreading Data Spreading Data Path (CSDP)Path (CSDP)



DRAWDRAW

CommunicatioCommunication Networkn Network

Dynamically Dynamically ReconfigurableReconfigurable

Deterministic/Deterministic/Non Non deterministic deterministic communicatiocommunicationsns

DRPU 1De-spread

DRPU 2Accumulate

DRPU 3De-spread

DRPU 4Accumulate

Commonconnectionline

Connectionpoints

RAKE finger # 1

RAKE finger # 2

one chipdelay

Data in

PN code

PN code

SWB

DRPUDRPU

DRPU DRPU

Switching Box



DRAWDRAW Dedicated I/ODedicated I/O

1 Register/non-register input and output selection

2 Set the DIO as input or output

4 Select wither to connect the DIO to only one I /O line or rotate between the I /Os

3 Select only one of the I /O lines to be connected to the DIO

1

1

2

2

2

2

D

D

Q

D

Clock

Clock

3

DRPU

4

I /O 1I/O 2I/O 3I/O 4

I/OPad



DRAWDRAW

Fast Dynamic Fast Dynamic ReconfiguratioReconfigurationn

CSU

DRPU 1

DRPU 2

DRPU 3

DRPU 4

Config. 1

Config. 2

Config. 3

Config. 4

CMU

Configuration bit stream

Config. Reg

Config. Reg

Config. Reg

Config. Reg

Control signals

Configuration bits

8 bits

64 bits

64 bit configuration word

Config. N64 bit configuration register

Control signalsF

rom

Glo

bal C

ontr

olU

nit

(G

CU

)

Control signals



Mapping ExamplesMapping Examples

3

S=2, D=0

3

Mul

N, W

OUTPUT Code

EXAMPLE: Configuration of a DRPU

The input interface is configured to selectthe 1st Global line, the North DRPU output,and the West DRPU output.

The CLFSR is utilized as 3 stages LFSR.The output of the CLFSR is routed to thenext CLFSR in the right DRPU neighbor.

The DRAP is configured to do aMultiplication operation.

The output Interface is configured to scalethe results by 2 right shifts and no delay.

The other components of the DRPU are notused in this example.




OP

Input Interface

Output Interface

CLFSR

CSDP

RAM/FIFO

Shows thethree inputlines selected.

Shows the lengthof the linearshift register (2or 3)

Shows whetherthe CSDP isused or not.

RAM/FIFOusage

Shows the DRAPoperation type

Shows theoutput interfacescale and delay

value



Mapping Mapping ExamplesExamples Mapping M-sequence

generator

Mapping Gold-Code Mapping Gold-Code generatorgenerator

Mapping an FIR filter




Mapping M-sequence generator

Register #N

XOR gate

OUTPUT

N-stageshift

register

Register #1

CLK

One tap




Mapping M-sequence generator (3-Stage)

NoOP

No OP

No

OP

3NoOP

No OP

OUTPUT Code




Mapping M-sequence generator (5-Stage)

D=0, S=0

32

OUTPUT Code




Mapping Gold-Code generatorMapping Gold-Code generator

S=0, D=0

3

OUTPUT Code

2

S=0, D=0

32

S=0, D=0

XOR

N, W

LFSR1

LFSR2

XOR




Mapping Gold-Code generatorMapping Gold-Code generator





Z-1 Z-1Z-1Z-1Z-1

C0 C1 C2 C3 C4

Y output

X input

TappedDelay Line

CoefficientConstantMultipliers

Adder Tree





OUTPUT

Z-1

+

*

Z-1

+

*

Z-1

+

*

+

*

OTHERS => ‘0’

INPUT8 bits

16 bits

16 bits

C3 C2 C1 C0





One tap

S=0, D=0

MUL

G1

S=0, D=0

ADD

N, W

S=0, D=0

MUL

G1

S=0, D=0

ADD

N, W

0S=0, D=0

MUL

G1

S=0, D=0

ADD

N, W

S=0, D=0

MUL

G1

S=0, D=0

ADD

N, W

output data

Input data



Conclusion and Conclusion and RecommendationsRecommendations

There is a strong need for Dynamic There is a strong need for Dynamic Reconfigurable Architectures (DRA) as a Reconfigurable Architectures (DRA) as a part of SoC for future wireless mobile part of SoC for future wireless mobile devicesdevices

DRA provide:DRA provide: Smaller physical size,Smaller physical size, Longer batteries, Longer batteries, Lower cost, andLower cost, and

FlexibilityFlexibility




The DRA must provide fast The DRA must provide fast configuration/Reconfigurationconfiguration/Reconfiguration DRAW uses a dedicated routing lines for the DRAW uses a dedicated routing lines for the

configuration bits.configuration bits. DRAW uses a hierarchal reconfiguration DRAW uses a hierarchal reconfiguration

structurestructure DRAW uses four shared context of DRAW uses four shared context of

configuration sets.configuration sets.




The DRA must provide efficient processing The DRA must provide efficient processing elementselements DRAW provides a 16-bit based dynamically DRAW provides a 16-bit based dynamically

reconfigurable processing units (DRPUs)reconfigurable processing units (DRPUs) The DRPU provides:The DRPU provides:

Multiplication (2’s Complement) Multiplication (2’s Complement) ALUALU StorageStorage Scale and DelayScale and Delay Spreading/De-spreadingSpreading/De-spreading Linear Feedback Shift RegisterLinear Feedback Shift Register Rotate and shiftRotate and shift




Recommendations for Future WorkRecommendations for Future Work Auto MappingAuto Mapping Interfacing to other components for the Interfacing to other components for the

SoCSoC Improve the design for power savingImprove the design for power saving Auto generation of a DRA design Auto generation of a DRA design

guidelines from a set of functional-guidelines from a set of functional-descriptionsdescriptions. .



Contributions During Contributions During this Ph.D.this Ph.D.

Publications:Publications: Journal Papers:Journal Papers:

1.1. Jürgen Becker, Jürgen Becker, Ahmad AlsolaimAhmad Alsolaim, Janusz Starzyk, and Manfred , Janusz Starzyk, and Manfred Glesner. “A Parallel Dynamically Reconfigurable Architecture Glesner. “A Parallel Dynamically Reconfigurable Architecture Designed for Application-specific Hardware/Software Systems in Designed for Application-specific Hardware/Software Systems in Future Mobile Communication”, In The Journal of Future Mobile Communication”, In The Journal of Supercomputing, Kluwer Academic Publishers, October, 2000Supercomputing, Kluwer Academic Publishers, October, 2000

Conferences Papers:Conferences Papers:1.1. A. AlsolaimA. Alsolaim, J. Becker, M. Glesner, J. Starzyk. “Architecture , J. Becker, M. Glesner, J. Starzyk. “Architecture

and Application of a Dynamically Reconfigurable Hardware Array and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems”, In Proc. of IEEE for Future Mobile Communication Systems”, In Proc. of IEEE Symposium of Field-Programmable Custom Computing Machines Symposium of Field-Programmable Custom Computing Machines (FCCM´00), Napa, USA, April 17-19, 2000, Page(s): 205 -214(FCCM´00), Napa, USA, April 17-19, 2000, Page(s): 205 -214

2.2. J. Becker, M. Glesner, J. Becker, M. Glesner, A. AlsolaimA. Alsolaim, J. Starzyk: “Fast , J. Starzyk: “Fast Communication Mechanisms in Coarse-grained Dynamically Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures” Proceedings of Second Reconfigurable Array Architectures” Proceedings of Second International Workshop on Engineering of Reconfigurable International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE´00, in conjunction with Hardware/Software Objects (ENREGLE´00, in conjunction with PDPTA 2000), Las Vegas, USA, June 26-29, 2000.PDPTA 2000), Las Vegas, USA, June 26-29, 2000.




Conferences Papers:Conferences Papers:3.3. A. AlsolaimA. Alsolaim, J. Becker, M. Glesner, J. Starzyk. “A , J. Becker, M. Glesner, J. Starzyk. “A

Dynamically Reconfigurable System-on-Chip Dynamically Reconfigurable System-on-Chip Architecture for Future Mobile Digital Signal Architecture for Future Mobile Digital Signal Processing”, In Proc. of X European Signal Processing Processing”, In Proc. of X European Signal Processing Conference (EUSIPCO 2000), Tampere, Finland, Conference (EUSIPCO 2000), Tampere, Finland, September 4-8, 2000September 4-8, 2000

4.4. Szabo, A.; Manolescu, Szabo, A.; Manolescu, A. AlsolaimA. Alsolaim, A.; Glesner, M. , A.; Glesner, M. “Performance simulation of a RAKE receiver for direct “Performance simulation of a RAKE receiver for direct sequence spreading spectrum communication sequence spreading spectrum communication systems”, International Semiconductor Conference, systems”, International Semiconductor Conference, 2000. CAS 2000 Proceedings., Page(s): 245 -248 vol.12000. CAS 2000 Proceedings., Page(s): 245 -248 vol.1

5.5. Alsolaim, A.Alsolaim, A. ; Starzyk, J. “Dynamically ; Starzyk, J. “Dynamically Reconfigurable Solution in the Digital Baseband Reconfigurable Solution in the Digital Baseband Processing for Future Mobile Radio Devices”, Processing for Future Mobile Radio Devices”, Proceedings of the 33rd Southeastern Symposium on Proceedings of the 33rd Southeastern Symposium on System Theory, 2001. Page(s): 221 -226System Theory, 2001. Page(s): 221 -226




Conferences Papers:Conferences Papers:

6.6. A.Szabo, A.M. Manolescu, A.Szabo, A.M. Manolescu, A. AlsolaimA. Alsolaim, M.Glesner, , M.Glesner, “Direct Sequence Spread Spectrum Communication “Direct Sequence Spread Spectrum Communication Systems in a Multipath Fading Channel. RAKE Systems in a Multipath Fading Channel. RAKE Receiver Performance Analysis”, Balkan Conference Receiver Performance Analysis”, Balkan Conference on Signal Processing, Communications, Circuits and on Signal Processing, Communications, Circuits and Systems, 2000, IstanbulSystems, 2000, Istanbul

7.7. Mingwei Ding, Mingwei Ding, Ahmad AlsolaimAhmad Alsolaim, and Janusz , and Janusz Starzyk, “Designing and Mapping of a Turbo Decoder Starzyk, “Designing and Mapping of a Turbo Decoder for 3G Mobile Systems Using Dynamically for 3G Mobile Systems Using Dynamically Reconfigurable Architecture”, The 2002 International Reconfigurable Architecture”, The 2002 International Conference on Engineering Of Reconfigurable Conference on Engineering Of Reconfigurable Systems And Algorithms ERSA'02 June 24-27, 2002 Systems And Algorithms ERSA'02 June 24-27, 2002 Monte Carlo Resort, Las Vegas, Nevada, USAMonte Carlo Resort, Las Vegas, Nevada, USA



Contributions During Contributions During this Ph.D.this Ph.D. ProposalsProposals

1.1. ““Dynamically Reconfigurable Architecture for 3G Mobil Dynamically Reconfigurable Architecture for 3G Mobil Communication Systems”, Submitted to NSF, April. 1999.Communication Systems”, Submitted to NSF, April. 1999.

2.2. ““Dynamically Reconfigurable Architecture for Third Dynamically Reconfigurable Architecture for Third Generation Mobil Systems”, Submitted to NSF, May 2001.Generation Mobil Systems”, Submitted to NSF, May 2001.

Joint ResearchJoint Research One academic year at Darmstadt University of One academic year at Darmstadt University of

Technology, Institute of Microelectronic Systems.Technology, Institute of Microelectronic Systems. One Master of science thesis “ Design and Simulation of One Master of science thesis “ Design and Simulation of

a Dynamically Reconfigurable Hardware Architecture a Dynamically Reconfigurable Hardware Architecture for Future Mobile Communication System” By: Thilo for Future Mobile Communication System” By: Thilo Pionteck.Pionteck.

Arrangement for a lecture by Dr. Mohammed Arrangement for a lecture by Dr. Mohammed Al-Ogeeli titled “A Simple Alternative For Al-Ogeeli titled “A Simple Alternative For Storage Allocation in High-Level Synthesis” at Storage Allocation in High-Level Synthesis” at the Institute of Microelectronic Systems, the Institute of Microelectronic Systems, Darmstadt, Nov. 1999. Darmstadt, Nov. 1999.




Co-chaired with Dr. Mohammed Al-Ogeeli the Co-chaired with Dr. Mohammed Al-Ogeeli the first Reconfigurable System-on-a-Chip (RSoC) first Reconfigurable System-on-a-Chip (RSoC) workshop at King Saud University, Riyadh, workshop at King Saud University, Riyadh, Saudi Arabia. Saudi Arabia. Keynote Speakers:Keynote Speakers:

Prof. Janusz StarzykProf. Janusz Starzyk Prof. Manfred GlsnerProf. Manfred Glsner Dr. Jurgen BeckerDr. Jurgen Becker

Tough a senior level VHDL Class. EECS 414 Tough a senior level VHDL Class. EECS 414 VHDL Design at the School of EECS, Ohio VHDL Design at the School of EECS, Ohio University. University.

Was the recipient of Stocker Scholarship for Was the recipient of Stocker Scholarship for the academic year 2001-2002.the academic year 2001-2002.



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