early power estimator for intel® arria® 10 fpgas user guide · 2020-03-31 · 1 overview of the...

PowerPlay Early Power Estimator for Arria 10 User Guide

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Contents

Overview of the PowerPlay Early Power Estimator for Arria 10....................... 1-1Power Model Status..................................................................................................................................... 1-1

Setting Up the PowerPlay Early Power Estimator for Arria 10......................... 2-1System Requirements.................................................................................................................................. 2-1Download and Install the PowerPlay Early Power Estimator............................................................... 2-1

Changing the Macro Security Level in Microsoft Excel 2003....................................................2-1Changing the Macro Security Level in Microsoft Excel 2007....................................................2-2Changing the Macro Security Level in Microsoft Excel 2010....................................................2-2

Estimating Power Consumption................................................................................................................2-2Estimating Power Consumption Before Starting the FPGA Design........................................ 2-3Estimating Power Consumption While Creating the FPGA Design........................................2-3Estimating Power Consumption After Completing the FPGA Design....................................2-5

PowerPlay Early Power Estimator for Arria 10 Graphical User Interface........ 3-1PowerPlay EPE Input Fields.......................................................................................................................3-1PowerPlay EPE Output Fields....................................................................................................................3-2PowerPlay EPE Input/Output Fields.........................................................................................................3-3PowerPlay EPE Field Shading.................................................................................................................... 3-3PowerPlay EPE Input Field Dependencies...............................................................................................3-3PowerPlay EPE Buttons.............................................................................................................................. 3-4

PowerPlay Early Power Estimator Worksheets for Arria 10............................. 4-1Arria 10 EPE - Common Worksheet Elements....................................................................................... 4-2Arria 10 EPE - Main Worksheet................................................................................................................ 4-3Arria 10 EPE - Logic Worksheet..............................................................................................................4-12Arria 10 EPE - RAM Worksheet..............................................................................................................4-16Arria 10 EPE - DSP Worksheet................................................................................................................4-20Arria 10 EPE - Clock Worksheet............................................................................................................. 4-23Arria 10 EPE - PLL Worksheet................................................................................................................ 4-25Arria 10 EPE - I/O Worksheet................................................................................................................. 4-26Arria 10 EPE - I/O-IP Worksheet............................................................................................................4-31Arria 10 EPE - XCVR Worksheet............................................................................................................4-32Arria 10 EPE - HPS Worksheet............................................................................................................... 4-37Arria 10 EPE - Report Worksheet........................................................................................................... 4-38Arria 10 EPE - Enpirion Worksheet........................................................................................................4-42

Factors Affecting the Accuracy of the PowerPlay Early Power Estimator forArria 10............................................................................................................ 5-1

TOC-2

Altera Corporation

Toggle Rate....................................................................................................................................................5-1Airflow...........................................................................................................................................................5-2Temperature................................................................................................................................................. 5-3Heat Sink....................................................................................................................................................... 5-4

Additional Information for the PowerPlay Early Power Estimator for Arria10 User Guide.................................................................................................. 6-1

Document Revision History for the PowerPlay Early Power Estimator for Arria 10 User Guide...................................................................................................................................................................6-1

TOC-3

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Overview of the PowerPlay Early PowerEstimator for Arria 10 1

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This user guide describes the PowerPlay Early Power Estimator (EPE) for Arria® 10.

This user guide provides guidelines for using the PowerPlay EPE, and details about thermal analysis andthe factors contributing to FPGA power consumption. You can calculate FPGA power consumption usingthe Microsoft Excel-based PowerPlay EPE spreadsheet. For more accurate power estimation, use thePowerPlay Power Analyzer in the Quartus® II software.

Altera recommends that you switch from the PowerPlay EPE spreadsheet to the PowerPlay PowerAnalyzer in the Quartus II software once your design is available. The PowerPlay Power Analyzerproduces more accurate results.

Altera recommends using the PowerPlay EPE results as an estimation of power, not as a specification.You must verify the actual power consumption during device operation, because the information issensitive to the actual device design and the environmental operating conditions.

The features of the PowerPlay EPE spreadsheet include:

• Ability to estimate the power consumption of your design before creating the design or during thedesign process

• Ability to import device resource information from the Quartus II software into the PowerPlay EPEspreadsheet with the use of the Quartus II-generated PowerPlay EPE file

• Ability to perform preliminary thermal analysis of your design

Related Information

• PowerPlay Power Analysis Chapter in Volume 3 of the Quartus II Handbook• Arria 10 Core Fabric and General Purpose I/Os Handbook• PowerPlay Early Power Estimators (EPE) and Power Analyzer

Power Model StatusThe power models in the PowerPlay Early Power Estimator for Arria 10 can be in either preliminary orfinal status.

Preliminary power models are created based on simulation results, process data, and other knownparameters; preliminary power models may change over time. Final power models are corelated to theproduction device, and undergo no further changes. The power model status is shown in the Mainworksheet of the PowerPlay EPE spreadsheet.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

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For most designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the followingaccuracies, with final power models:

• PowerPlay Power Analyzer: ± 20% from silicon, assuming that the PowerPlay Power Analyzer uses theValue Change Dump File (.vcd)-generated toggle rates

• PowerPlay EPE spreadsheet: ± 30% from silicon, assuming PowerPlay EPE data imported fromPowerPlay Power Analyzer results using .vcd-generated toggle rates

Toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate-levelsimulation representative of the system operation.

Related InformationPowerPlay Early Power Estimators (EPE) and Power Analyzer

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Setting Up the PowerPlay Early PowerEstimator for Arria 10 2

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System RequirementsThe PowerPlay Early Power Estimator for Arria 10 requires the following software:

• Windows operating system• Microsoft Excel 2003, Microsoft Excel 2007, or Microsoft Excel 2010• Quartus II software version 15.0 or later (if generating a file for importation)

Related InformationOperating System Support

Download and Install the PowerPlay Early Power EstimatorThe PowerPlay Early Power Estimator for Arria 10 is available from the PowerPlay Early Power Estimators(EPE) and Power Analyzer page on the Altera website.

After you read the terms and conditions and click I Agree, you can download the Microsoft Excel (.xlsor .xlsx) file.

By default, the macro security level in Microsoft Excel 2003, Microsoft Excel 2007, and Microsoft Excel2010 is set to High. If the macro security level is set to High, macros are automatically disabled. For thefeatures in the PowerPlay EPE spreadsheet to function properly, you must enable macros.

Related InformationPowerPlay Early Power Estimators (EPE) and Power Analyzer

Changing the Macro Security Level in Microsoft Excel 2003





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To change the macro security level in Microsoft Excel 2003, follow these steps:

1. Click Tools > Options.2. Click Security > Macro Security.3. Select Security Level > Medium in the Security dialog box then click Ok.4. Click Ok in the Options window.5. Close the PowerPlay EPE spreadsheet and reopen it.6. Click Enable Macros in the pop-up window.



1. Click the Office button in the upper left corner of the .xlsx file.2. Click the Excel Options button at the bottom of the menu.3. Click the Trust Center button on the left. Then, click the Trust Center Settings button.4. Click the Macro Settings button in the Trust Center dialog box. Turn on the Disable all macros with

notification option.5. Close the PowerPlay EPE spreadsheet and reopen it.6. Click Options when a security warning appears beneath the Office ribbon.7. Turn on Enable this content in the Microsoft Office Security Options dialog box.



1. Click File2. Click Help > Options3. Click Trust Center > Trust Center Settings4. Click the Macro Settings button in the Trust Center dialog box. Turn on the Disable all macros with

notification option.5. Close the PowerPlay EPE spreadsheet and reopen it.6. Click Enable Content when a security warning appears beneath the Office ribbon.

Estimating Power Consumption

With the PowerPlay Early Power Estimator, you can estimate power consumption at any point in yourdesign cycle. You can use the PowerPlay EPE to estimate the power consumption when you have not yetbegun your design, or if your design is partially complete. Although the PowerPlay EPE can provide apower estimate for your completed design, Altera recommends that you use the PowerPlay PowerAnalyzer in the Quartus II software instead, for a more accurate estimate based on the exact placementand routing information of the completed design.

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Altera Corporation Setting Up the PowerPlay Early Power Estimator for Arria 10

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Estimating Power Consumption Before Starting the FPGA Design

Table 2-1: Advantage and Constraints of Power Estimation before Designing FPGA

Advantage Constraint

You can obtain power estimation before startingyour FPGA design.

• Accuracy depends on your inputs and yourestimation of the device resources; where thisinformation may change (during or after yourdesign is complete), your power estimationresults may be less accurate.

• The PowerPlay EPE spreadsheet uses averagesand not the actual design implementationdetails. The PowerPlay Power Analyzer hasaccess to the full design details. For example, thePowerPlay EPE uses average toggle rates forALM inputs, where the PowerPlay PowerAnalyzer can determine exact toggle rate foreach input, assuming that the PowerPlay PowerAnalyzer uses the Value Change Dump File(.vcd)-generated toggle rates.

To estimate power consumption with the PowerPlay EPE spreadsheet before starting your FPGA design,follow these steps:

1. On the Main worksheet of the PowerPlay EPE spreadsheet, select the target family, device, and packagefrom the Family, Device Grade, Package, and Transceiver Grade drop-down lists.

2. Enter values for each worksheet in the PowerPlay EPE spreadsheet. Different worksheets in thePowerPlay EPE spreadsheet display different power sections, such as clocks and phase-locked loops(PLLs).

3. The calculator displays the total estimated power consumption in the Total (W) and Total AfterSmartVID (W) (if applicable) cells of the Main worksheet.

Estimating Power Consumption While Creating the FPGA Design

If your FPGA design is partially complete, you can import the PowerPlay EPE file (<revision name>_early_pwr.csv) generated by the Quartus II software to the PowerPlay EPE spreadsheet. After importing theinformation from the <revision name>_early_pwr.csv into the PowerPlay EPE spreadsheet, you can edit thePowerPlay EPE spreadsheet to reflect the device resource estimates for your final design.

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Table 2-2: Advantages and Constraints of Power Estimation if your FPGA Design is Partially Complete

Advantage Constraint

• You can perform power estimation early in theFPGA design cycle.

• Provides the flexibility to automatically fill in thePowerPlay Early Power Estimator spreadsheetbased on the Quartus II software compilationresults.

• Accuracy depends on your inputs and yourestimation of the device resources; where thisinformation may change (during or after yourdesign is complete), your power estimationresults may be less accurate.

• The PowerPlay EPE spreadsheet uses averagesand not the actual design implementationdetails. The PowerPlay Power Analyzer hasaccess to the full design details. For example, thePowerPlay EPE uses average toggle rates forALM inputs, where the PowerPlay PowerAnalyzer can determine exact toggle rate foreach input, assuming that the PowerPlay PowerAnalyzer uses the Value Change Dump File(.vcd)-generated toggle rates.

Importing a File

To estimate power consumption with the PowerPlay EPE spreadsheet if your FPGA design is partiallycomplete, you can import a file.

Importing a file saves you time and effort otherwise spent on manually entering information into thePowerPlay EPE. You can also manually change any of the values after importing a file.

Generating the PowerPlay EPE File

To generate the PowerPlay EPE file, follow these steps:

1. Compile the partial FPGA design in the Quartus II software.2. On the Project menu, click Generate PowerPlay Early Power Estimator File to generate the <revision

name>_early_pwr.csv in the Quartus II software.

Importing Data into the PowerPlay EPE Spreadsheet

You must import the PowerPlay EPE file into the PowerPlay EPE spreadsheet before modifying anyinformation in the PowerPlay EPE spreadsheet. Also, you must verify all your information after importinga file.

Importing a file from the Quartus II software populates all input values on the Main worksheet that werespecified in the Quartus II software.

Input values imported into the PowerPlay EPE spreadsheet are the values taken from the Quartus IIsoftware as per the design. You can manually edit the values in the PowerPlay EPE spreadsheet to suityour design requirements.

To import data into the PowerPlay EPE spreadsheet, follow these steps:

1. In the PowerPlay EPE spreadsheet, Click Import CSV.2. Browse to a PowerPlay EPE file generated from the Quartus II software and click Open. The file has a

name of <revision name>_early_pwr.csv.3. After the file is imported, the mouse cursor changes from busy to normal. If there are any warnings

during the importation, the PowerPlay EPE produces the EPE Import Warnings dialog box. Analyze

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the warnings carefully to ensure that they are expected. If any of the warnings are unexpected, youmust manually modify the corresponding fields in the PowerPlay EPE after the importation iscompleted. You can copy all warning messages to the clipboard for future reference by clicking Copyto Clipboard. Click OK to dismiss the EPE Import Warnings dialog box.

Related Information

• Arria 10 EPE - Common Worksheet Elements on page 4-2• Arria 10 EPE - Main Worksheet on page 4-3

Estimating Power Consumption After Completing the FPGA Design

If your design is complete, Altera strongly recommends using the PowerPlay Power Analyzer in theQuartus II software. The PowerPlay Power Analyzer provides the most accurate estimate of device powerconsumption. The PowerPlay Power Analyzer uses toggle rates from simulation, user assignments, andplacement-and-routing information to provide accurate power estimates.

Related InformationPowerPlay Power Analysis Chapter in Volume 3 of the Quartus II Handbook

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PowerPlay Early Power Estimator for Arria 10Graphical User Interface 3

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The graphical user interface (GUI) of the PowerPlay Early Power Estimator for Arria 10 consists of inputfields for data entry, output fields for display of results and messages, and buttons to trigger actions. Somefields can serve as both inputs and outputs, and are referred to as input/output fields.

Most input and output fields have tooltips that explain the field's purpose. Fields with tooltips have a redtriangle in the top right corner of the field label. Hover your mouse over the label to display the tooltip.

PowerPlay EPE Input FieldsInput fields let you enter information about the device, board, and design for which you want to calculatepower estimates. Some input fields let you type values directly, and others let you select from a list ofvalues on a dropdown menu.

Direct Entry Input Fields

Some fields allow you to type values directly into the field. Such fields are often used for data that has alarge range of possible values, such as clock frequencies or resource counts.

If the value you enter does not pass legality checks, or is inappropriate for the field, the system displays anerror message. The error message may indicate the conditions under which a value is invalid, and specifya valid range of values. If a specific type of numerical value is expected and you enter a text value or awrong numerical type, the error message will indicate that the entered value cannot be converted to theexpected data type.

Many fields have restrictions based on the selected family and device. To better understand restrictions onfield values, refer to the relevant field description in this user guide, to the tooltip in the appropriate EPEworksheet, or to the Arria 10 Device Handbook.

Note: Although the PowerPlay Early Power Estimator restricts many field values, the restrictions are notexhaustive. In order to provide power estimates at early design stages, when many details of thedesign are still unknown, the EPE uses a simplified device model that does not account for allpossible restrictions. The EPE may accept as legal some values that might not be accepted as legalby the Quartus II software.

Dropdown Input Fields

Input fields that have a limited number of valid values often employ a dropdown menu. A dropdownmenu is denoted by a downward-pointing arrow that appears when you click in the field. Click in the field





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a second time to display the list of allowed values. Click the desired value to select it and populate thefield. An example dropdown input field is shown in the following figure:

Figure 3-1: Dropdown Input Field

You can also type a value directly into an input field that has a dropdown menu. To directly enter a value,select the field and press F2, and then type the desired value. The value that you enter must be identical toone of the available values on the dropdown menu, otherwise you will receive an error message.

Figure 3-2: Value Entered is Not Valid

You can click Retry in the error dialog to enter a new value, or click Cancel to revert back to the last legalvalue. Clicking Help invokes the generic Excel help window.

PowerPlay EPE Output FieldsOutput fields display estimated values for power, current, temperature, or resource utilization for a designspecification that you have entered into the Early Power Estimator.

Some output fields, such as thermal power estimates in the Main and Report worksheets, may displayvalues in red to indicate an error in the design specification. If you encounter results displayed in red,review the relevant worksheet for errors or utilization values exceeding 100%. Correct any errors to obtainreliable power and temperature estimates.

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PowerPlay EPE Input/Output FieldsCertain fields may serve as input fields in some configurations, and output fields in others.

For example, you may enter a Pin Clock Frequency value manually for some I/O modes, while in other I/Omodes Pin Clock Frequency is calculated automatically based on values of other input fields.

If you enter a value into an input/output field when it is serving as an output, there is no effect. The valuereverts to the calculated value.

PowerPlay EPE Field ShadingThe PowerPlay Early Power Estimator for Arria 10 employs shading to distinguish between input andoutput fields, and to help identify fields with only one allowed value.

Figure 3-3: Input Fields with Shading

Regular input fields, such as Device, Device Grade and Package have white shading. White shading alsodenotes input/output fields.

Input fields that currently have only one allowed value, such as Transceiver Grade in this example, havegray shading. In this example, there is only one supported transceiver grade for the selected combinationof device, device grade and package. A different combination of device, device grade and package maysupport more than one transceiver grade, in which case the Transceiver Grade field shading would turnwhite.

Output fields, such as Power Model Status, or PSTATIC have pale green shading. Some output fields, suchas TOTAL (W), employ pale blue shading for emphasis.

PowerPlay EPE Input Field DependenciesThe value you specify for some input fields may affect the allowed values for other fields.

For example, the device package that you select may determine what transceiver grades are selectable. Ifyou change the selected device package, and the currently selected transceiver grade is still legal for thenew package, the Transceiver Grade value does not change. However, if the currently selected transceivergrade is not compatible with the selected device package, the Transceiver Grade value automaticallychange to one of the legal values.

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Changes that you make in one worksheet may affect values on another worksheet, because of dependen‐cies between input fields. For example, if you select a device that does not support the current I/Ostandard specified in the I/O worksheet, that I/O standard will automatically change to one that issupported by the new device.

In general, the PowerPlay Early Power Estimator for Arria 10 does not automatically change an inputvalue unless it is necessary to preserve the legality of the input. Changes in one field have minimal impacton other fields, while ensuring that overall combination of field values are legal. However, this cansometimes lead to unanticipated results. Consider the following example:

Assume that Dev1 is selected in the Main worksheet, and I/O standard IO1 is selected in the I/Oworksheet. Assume also that device Dev1 supports I/O standards IO1 and IO2. Suppose that you changethe device selection to Dev2, which supports only one I/O standard, IO2. As a result of you changing thedevice selection, the I/O standard in the I/O worksheet will change to IO2. If you then reverted the deviceselection back to Dev1, the I/O standard would not change, because IO2 is a legal I/O standard value forthe device Dev1. The important point to note, is that the changing of device from Dev1 to Dev2 and backagain, had the—potentially unintended—consequence of changing the I/O standard in the I/O worksheet.

Note: In most cases, field dependencies are limited to the same worksheet, and often even within thesame row. However, device, device grade, package and transceiver grade selection can have a muchwider impact, as illustrated above. A simple way to verify that no unintended changes resultedfrom changing a device is to use the Export CSV function to export the EPE state before and afterthe change in device selection. You can then compare the two CSV files using a third-party diffutility to identify any fields that have changed.

PowerPlay EPE ButtonsThe PowerPlay Early Power Estimator for Arria 10 provides buttons for resetting the EPE, for importingor exporting a comma-separated value (.csv) file, and for navigating between worksheets.

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PowerPlay Early Power Estimator Worksheetsfor Arria 10 4

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The PowerPlay Early Power Estimator (EPE) for Arria 10 is an Excel-based spreadsheet that allows you toenter information into worksheets based on architectural features. The EPE then reports, in watts,subtotals of the power consumed by each architectural feature.

For more information about each architectural feature refer to the respective worksheets.

Arria 10 EPE - Common Worksheet Elements on page 4-2The PowerPlay Early Power Estimator for Arria 10 is divided into multiple worksheets, each allowingentry of a subset of FPGA resources. Some elements are common to more than one worksheet.

Arria 10 EPE - Main Worksheet on page 4-3The Main worksheet of the PowerPlay Early Power Estimator for Arria 10 allows you to enter device,package, and cooling information, and displays thermal power and thermal analysis information.

Arria 10 EPE - Logic Worksheet on page 4-12The Logic worksheet of the PowerPlay Early Power Estimator for Arria 10 allows you to enter logicresources for all modules in your design.

Arria 10 EPE - RAM Worksheet on page 4-16Each row in the RAM worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a designmodule with RAM blocks of the same type, same data width, same RAM depth (if applicable), same RAMmode, and the same port parameters.

Arria 10 EPE - DSP Worksheet on page 4-20Each row in the DSP worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a DSPdesign module where all instances have the same configuration, clock frequency, toggle percentage, andregister usage.

Arria 10 EPE - Clock Worksheet on page 4-23Each row in the Clock worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a clocknetwork or a separate clock domain.

Arria 10 EPE - PLL Worksheet on page 4-25Each row in the PLL worksheet of the PowerPlay Early Power Estimator for Arria 10 represents one ormore PLLs in the device.

Arria 10 EPE - I/O Worksheet on page 4-26Each row in the I/O worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a designmodule where the I/O pins have the same I/O standard, input termination, current strength or outputtermination, data rate, clock frequency, output enable static probability, and capacitive load.





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Arria 10 EPE - I/O-IP Worksheet on page 4-31Each row in the I/O-IP worksheet of the PowerPlay Early Power Estimator for Arria 10 represents adesign module.

Arria 10 EPE - XCVR Worksheet on page 4-32The XCVR worksheet of the PowerPlay Early Power Estimator for Arria 10 allows you to enter XCVRresources and their settings for all modules in your design.

Arria 10 EPE - HPS Worksheet on page 4-37The HPS worksheet of the PowerPlay Early Power Estimator for Arria 10 applies to Arria 10 devices withHPS.

Arria 10 EPE - Report Worksheet on page 4-38The Report worksheet shows all the information and power estimation results from the PowerPlay EarlyPower Estimator for Arria 10.

Arria 10 EPE - Enpirion Worksheet on page 4-42Each row in the Regulator Selection table of the Enpirion worksheet of the PowerPlay Early PowerEstimator for Arria 10 represents the power solution for a single regulator group.

Arria 10 EPE - Common Worksheet ElementsThe PowerPlay Early Power Estimator for Arria 10 is divided into multiple worksheets, each allowingentry of a subset of FPGA resources. Some elements are common to more than one worksheet.

Total Thermal Power

The Total Thermal Power field estimates the total thermal power consumed by all FPGA resources in thespecific worksheet. Some worksheets may also provide a breakdown of the components contributing tothe Total Thermal Power.

Resource Utilization

Most worksheets contain one or more fields that provide an estimate of the percentage resource utiliza‐tion for the modules in the specific worksheet. Such values are calculated based on the maximum availableresources of a given type for a selected device. If resource utilization exceeds 100%, the value ishighlighted in red to alert you that the current device may not be able to support the resources enteredinto the worksheet. Additionally, the thermal power value displayed in the Main and Report worksheetsis displayed in red for any worksheet whose utilization exceeds 100%.

Power Rail Current Consumption

Most worksheets include a table showing the dynamic current consumption (and standby currentconsumption, if applicable) for all power rails used by the FPGA resources in the specific worksheet. Thesame power rail may appear in multiple worksheets, and the total dynamic and standby current in theReport worksheet is the sum of all corresponding currents for a given rail at a given voltage in individualworksheets. The Report worksheet also includes static currents, which are not reported in individualworksheets.

Errors and Warnings

Error and warning fields are used to display error and warning messages alerting users to issues with theinformation entered into this or another related worksheet. If there are error messages in the current

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worksheet, the thermal power value displayed in the Main and Report worksheets corresponding to thecurrent worksheet will be highlighted in red to indicate an error message. For accurate power estimates,all error messages should be resolved.

Related Information

• Arria 10 EPE - Main Worksheet on page 4-3• Arria 10 EPE - Report Worksheet on page 4-38

Arria 10 EPE - Main WorksheetThe Main worksheet of the PowerPlay Early Power Estimator for Arria 10 allows you to enter device,package, and cooling information, and displays thermal power and thermal analysis information.

Figure 4-1: Arria 10 PowerPlay EPE Main Worksheet

The required parameters depend on whether the junction temperature is manually entered or autocomputed.

Table 4-1: Input Parameter Information

Parameter Description

Family Select the device family.

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Device Select your device.

Larger devices consume more static power and have higher clockdynamic power. All other power components are unaffected bydevice selection.

Device Grade Select the combination of Operating Temperature, Speed Grade,and Power Option used.

• Operating Temperature: Extended (TJ = 0C to 100C),Industrial (TJ = -40C to 100C), Commercial (TJ = 0C to 85C),Automotive (TJ = -40C to 125C)

• FPGA Core Fabric Speed Grade: 1 (fastest), 2 or 3.• Power Option: S (Standard), L (Low), or M (VCC power

manager)

Package Select the device package.

Larger packages provide a larger cooling surface and more contactpoints to the circuit board, thus they offer lower thermalresistance. Package selection does not affect dynamic powerdirectly.

Transceiver Grade Select the transceiver grade.

Note: For information on transceiver grades, refer to Arria 10Device Variants and Packages, in the Arria 10 DeviceOverview.

Power Characteristics Select typical or theoretical worst-case silicon process.

There is a process variation from die-to-die. This variationprimarily affects static power consumption.

If you choose Typical power characteristics, estimates are basedon average power consumed by typical silicon. For FPGA boardpower supply design, choose Maximum for worst-case values. Toenable the Enpirion device selection, you must set the PowerCharacteristics to Maximum.

VCC Voltage (mV) Select the voltage of the VCC power rail, in mV.SmartVoltage ID Select to activate the SmartVID regulator power-saving feature.Power Model Status Indicates whether the power model for the device is in preliminary

or final status.Junction Temp, TJ Select whether Junction Temperature (TJ) should be computed

automatically or provided by the user.Ambient Temp, TA (°C)/JunctionTemp, TJ (C)

Enter the air temperature near the device. This value can rangefrom –40°C to 125°C, depending on the device grade selected. Ifyou turn on the Auto Computed TJ option, you can enter theambient temperature in this field; otherwise, enter the actualjunction temperature.

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Cooling Solution Select your cooling solution with associated airflow.

Representative examples of heat sinks and airflows are provided;larger heat sinks provide lower thermal resistance, and thus lowerjunction temperature. If the heat sink and airflow is known,consult the data sheet, choose “Custom”, and in the Theta JAJunction-Ambient field, enter a junction to ambient valueaccording to your system.

θJA Junction-Ambient If you have specified a custom cooling solution, enter theJunction-Ambient value in °C/W. This value is used to computethe final junction temperature if you have selected AutoCompute.

Board Thermal Model This field is applicable in cases where no heat sink is used.

Select the type of board model to be used in thermal analysis.Available values are:

• None (Conservative). If you select this model, the systemassumes that no heat is dissipated through the board. Thisresults in a pessimistic calculated junction temperature.

• Typical. If you select this model, the system assumes thecharacteristics of a typical customer board stack, which is basedon the selected device and package.

• Custom. If you select this model, you must enter anappropriate value for Theta JB, in the field below.

You should perform a detailed thermal simulation of your systemto determine the final junction temperature. This two-resistorthermal model is for early estimation only.

θJB Junction-Board If you specify a custom Board Thermal Model, enter the ThetaJunction-Board value (in °C/W), in this field.

Board Temp, TB (°C) If you specified a custom or typical Board Thermal Model, enterthe board temperature to be used in thermal calculations (in °C).

Thermal power is the power dissipated in the device. Total thermal power is the sum of the thermal powerof all the resources used in the device, including the static, standby, and dynamic power. Total thermalpower includes only the thermal component for the I/O worksheet and does not include external powerdissipation, such as from voltage-referenced termination resistors.

The static power (PSTATIC) is the thermal power dissipated on the chip, independent of user clocks.PSTATIC includes the static power from all FPGA functional blocks, except for I/O DC bias power andtransceiver DC bias power, which are included in the standby power of the I/O and XCVR worksheets,respectively. PSTATIC is the only thermal power component that varies with junction temperature, selecteddevice, and power characteristics (process).



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Table 4-2: Thermal Power (W) Information

Column Heading Description

Logic Displays the dynamic power consumed by adaptivelogic modules (ALMs), flipflops (FFs) andassociated routing. Click the 'Logic' button to seedetails.

RAM Displays the dynamic power consumed by RAMsand associated routing. Click the 'RAM' button tosee details.

DSP Displays the dynamic power consumed by digitalsignal processing (DSP) blocks and associatedrouting. Click the 'DSP' button to see details.

Clock Displays the dynamic power consumed by clocknetworks. Click the 'Clock' button to see details.

PLL Displays the dynamic power consumed by phase-locked loops (PLLs). Click the 'PLL' button to seedetails.

I/O Displays the thermal power consumed by I/O pinsand I/O subsystems. Click the 'I/O' button to seedetails.

XCVR Displays the total power consumed by transceiverblocks. Click the 'XCVR' button to see details.

HPS Displays the total power consumed by the hardprocessor system (HPS). Click the 'HPS' button tosee details.

Pstatic Displays the static power consumed regardless ofclock frequency. This includes static powerconsumed by I/O and transceiver blocks, but doesnot include standby power. Pstatic is affected byjunction temperature, selected device, and powercharacteristics.

TOTAL (W) Displays the total power dissipated as heat from theFPGA. Does not include power dissipated in off-chip termination resistors. See the Report worksheetfor power supply currents drawn from the FPGAsupply rails. Total power dissipation in the FPGAmay differ from the sum of power on all rails due toseveral factors including, but not limited to, thepower dissipated in off-chip termination resistors.


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SmartVID Power Savings Displays the total power reduction (static anddynamic) resulting from the lower voltage that ismade possible by SmartVID. This power reductionis dependent on the user design and devicecharacteristics. The combination of these factorsmay result in different static and dynamic powersavings, so the exact dynamic and staticcomponents are not identified separately, and thepower reduction reported here is a worst-caseresult. This field is applicable only to devices thatsupport the SmartVID feature, and only if theSmartVoltage ID setting is set to On.

TOTAL After SmartVID (W) Displays the total power dissipated as heat from theFPGA after the power reduction due to theSmartVID feature is taken into account.

Note: If any thermal power value is highlighted in red, it indicates an error in the design specification.Review the relevant worksheet for errors or utilization values exceeding 100%. Correct any errorsto obtain reliable power and temperature estimates.

The Thermal Analysis section displays the junction temperature (TJ) and the maximum allowed ambienttemperature (TA) values.

Table 4-3: Thermal Analysis Information


Junction Temp, TJ (°C) If you specified a value for Junction Temp (TJ), thevalue in this field is equal to the value that youspecified.

If you specified Auto Compute for Junction Temp(TJ), this field displays the estimated device junctiontemperature based on the thermal parametersprovided. The junction temperature is determinedby dissipating the total thermal power through thetop of the chip and through the board.

Maximum Allowed TA (°C) / Maximum Allowed TJ(C)

If you specified a value for Junction Temp (TJ), thevalue in this field is the maximum allowable devicejunction temperature (in °C), based on the specifieddevice grade.

If you specified Auto Compute for Junction Temp(TJ), this field provides a guideline for themaximum ambient temperature (in °C) to whichthe device can be subjected, without exceeding themaximum allowable junction temperature, based onthe specified cooling solution and device grade.



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You can directly enter or automatically compute the junction temperature based on the informationprovided. To enter the junction temperature, select User Entered in the Junction Temp field in the InputParameters section. To automatically compute the junction temperature, select Auto Compute in thesame field.

When automatically computing the junction temperature, the ambient temperature, cooling solution,board thermal model, and board temperature of the device determine the junction temperature in °C.Junction temperature is the estimated operating junction temperature based on your device and thermalconditions.

You can consider the device as a heat source and the junction temperature is the temperature of thedevice. While the temperature typically varies across the device, to simplify the analysis, you can assumethat the temperature of the device is constant regardless of where it is measured.

Power from the device can be dissipated through different paths. Different paths become significantdepending on the thermal properties of the system. The significance of power dissipation paths varydepending on whether or not a heat sink is used for the device.

Not Using a Heatsink

When you do not use a heat sink, the major paths of power dissipation are from the device to the air. Youcan refer to this as a junction-to-ambient thermal resistance. In this case, there are two significantjunction-to-ambient thermal resistance paths:

• From the device through the case to the air• From the device to the board

Figure 4-2: Thermal Representation without a Heat Sink

Case

Thermal Representation without Heat Sink

Board

Device

θJA

In the model used in the PowerPlay EPE spreadsheet, power is dissipated through the case and board. TheθJA values are calculated for differing air flow options accounting for the paths through the case andthrough the board.

Figure 4-3: Thermal Model in the PowerPlay EPE Spreadsheet without a Heat Sink

TJ

JA

TA

Power (P)

HeatSource

θ


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The ambient temperature does not change, but the junction temperature changes depending on thethermal properties and total power dissipation, which in turn is affected by junction temperature. Thejunction temperature calculation is an iterative process.

The following equation shows the total power calculated based on the total θJA value, ambient, andjunction temperatures.

Using a Heat Sink

When you use a heat sink, the major paths of power dissipation are from the device through the case,thermal interface material, and heat sink. There is also a path of power dissipation through the board. Thepath through the board has less impact than the path to air.

Figure 4-4: Thermal Representation with a Heat Sink

Heat Sink

CaseDevice

Board

Thermal interface material

θJA

θJC

θSA

Thermal Representation with Heat Sink

θCS

BOTTOM

In the model used in the PowerPlay EPE spreadsheet, power is dissipated through the board or throughthe case and heat sink. The junction-to-board thermal resistance (θJA BOTTOM) refers to the thermalresistance of the path through the board. Junction-to-ambient thermal resistance (θJA TOP) refers to thethermal resistance of the path through the case, thermal interface material, and heat sink.



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Figure 4-5: Thermal Model for the PowerPlay EPE Spreadsheet with a Heat Sink

TJ

TB

Power (P1)

Heat Source

Power (P2)

TJ

TC

TS

TA

θJA BOTTOM

θJC

θCS

θSA

If you want the PowerPlay EPE spreadsheet thermal model to take the θJA BOTTOM into consideration, setthe Board Thermal Model parameter to either Typical or Custom. Otherwise, set the Board ThermalModel parameter to None (conservative). In this case, the path through the board is not considered forpower dissipation and a more conservative thermal power estimate is obtained.

The addition of the junction-to-case thermal resistance (θJC), the case-to-heat sink thermal resistance(θCS) and the heat sink-to-ambient thermal resistance (θSA) determines the θJA TOP, as shown by thefollowing equation.

θJA TOP = θJC+ θCS + θSA

Based on the device, package, airflow, and heat sink solution selected in the Input Parameters section, thePowerPlay EPE spreadsheet determines the θJA TOP.

If you use a low, medium, or high profile heat sink, select the airflow from the values of Still Air and airflow rates of 100 lfm (0.5 m/s), 200 lfm (1.0 m/s), and 400 lfm (2.0 m/s). If you use a custom coolingsolution, enter the custom θJA value. You must incorporate the airflow and junction to case resistance intothe custom θJA value. You can obtain these values from the heat sink manufacturer.

The ambient temperature does not change, but the junction temperature changes depending on thethermal properties. Calculating the junction temperature is an iterative process because a change injunction temperature affects the thermal device properties, due to a change in power dissipation. Thosethermal device properties are used to calculate junction temperature.

The total power is calculated based on the total θJA value, ambient, and junction temperatures with thefollowing equation.


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Table 4-4: Control Button Descriptions

Button Name Description

Logic Opens the Logic worksheet to display details of thedynamic power consumed by adaptive logicmodules (ALMs), flipflops, and associated routing.

RAM Opens the RAM worksheet to display details of thedynamic power consumed by RAMs and associatedrouting.

DSP Opens the DSP worksheet to display details of thedynamic power consumed by digital signalprocessing blocks and associated routing.

Clock Opens the Clock worksheet to display details of thedynamic power consumed by clock networks andassociated routing.

PLL Opens the PLL worksheet to display details of thedynamic power consumed by phase-locked loopsand associated routing.

I/O Opens the I/O worksheet to display details of thethermal power consumed by I/O pins and I/Osubsystems.

XCVR Opens the XCVR worksheet to display details of thetotal power consumed by transceiver blocks.

HPS Opens the HPS worksheet to display details of thetotal power consumed by the hard processor system(HPS).

Reset Resets the PowerPlay Early Power Estimator todefault values; any parameters that you havespecified are lost.

Import CSV Allows you to import parameters from a comma-separated value file.

Export CSV Allows you to export parameters to a comma-separated value file.

View Report Displays the Report worksheet.Manage Power Rail Configuration Displays the Power Rail Configuration table, on the

Report worksheet.Manage Power Regulators Displays the Regulator Selection table, on the

Enpirion worksheet.



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Related Information

• Arria 10 Device Variants and Packages• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

Arria 10 EPE - Logic WorksheetThe Logic worksheet of the PowerPlay Early Power Estimator for Arria 10 allows you to enter logicresources for all modules in your design.

Figure 4-6: Logic Worksheet of the PowerPlay Early Power Estimator

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Table 4-5: General Settings in the Logic Worksheet

Input Parameter Description

High-Speed Tile Usage Select the High-Speed Tile Usage setting. This valuecan be Typical Design, Typical High-PerformanceDesign, or Atypical High-Performance Design.

• Typical Design represents a design with 10% ormore timing margin.

• Typical High-Performance Design represents anaverage design with no timing margin. Thesedesigns have a few near-critical timing paths.

• Atypical High-Performance Design represents a90th percentile design with no timing margin.These designs have many near-critical timingpaths.

This setting affects static power consumption(PSTATIC) found in the Main worksheet of thePowerPlay EPE spreadsheet. It also has a smallimpact on the dynamic power consumed by thelogic resources entered in the Logic worksheet ofthe PowerPlay EPE spreadsheet.

Note: When you import a design from theQuartus II software, the PowerPlay EarlyPower Estimator imports a precise valuefor high-speed tile usage, and the valueof this setting changes to Imported.

Table 4-6: Logic Worksheet Information


Module Specify a name for each module of the design. Thisis an optional entry.

#Half ALMs Enter twice the number of Adaptive Logic Modules(ALMs) used in your design.

# FFs Enter the number of flipflops in the module.

Clock routing power is calculated separately on theClock worksheet of the PowerPlay EPE spreadsheet.

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Clock Freq (MHz) Enter a clock frequency (in MHz). This value islimited by the maximum frequency specification forthe device family.

Note: When you import a design from theQuartus II software, some imported halfALMs and flipflops may have a clockfrequency of 0 MHz; this can occur forone of two reasons:

• The Quartus II software did not havesufficient information to determineclock frequency due to incompleteclock constraints.

• The Quartus II software exported acomma-separated value (.csv) filecontaining half ALMs and flipflopsthat are unused, but which reside inused LABs. Such ALMs and flipflopshave a clock frequency of 0 MHz.

Toggle % Enter the average percentage of clock cycles whenthe block output signals change values. Togglepercentage is multiplied by clock frequency todetermine the number of transitions per second.For example, 100 MHz frequency with a 12.5%toggle rate, means that each LUT or flipflop outputtoggles 12.5 million times per second (100MHz ×12.5%).

The toggle percentage ranges from 0 to 100%.Typically, the toggle percentage is 12.5%, which isthe toggle percentage of a 16-bit counter. Most logiconly toggles infrequently; therefore, toggle rates ofless than 50% are more realistic. To ensure you donot underestimate the toggle percentage, use ahigher toggle percentage.

For example, a T flipflop (TFF) with its input tied toVCC has a toggle rate of 100% because its output ischanging logic state on every clock cycle. Refer tothe 4-Bit Counter Example below for a moredetailed analysis.

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Routing Factor Indicates the extent of the routing power of theoutputs.

Characteristics that have a large power impact andare captured by this factor include the following:

• the fanout of the outputs• the number of routing resources used• the relative power usage of the different types of

routing resources used

Thermal Power (W) - Routing Indicates the power dissipation due to estimatedrouting (in W).

Routing power depends on placement and routing,which is a function of design complexity. The valuesshown are representative of routing power based onobserved behavior across more than 100 real-worlddesigns.

Use the Quartus II PowerPlay Power Analyzer foraccurate analysis based on the exact routing used inyour design.

Thermal Power (W) - Block Indicates the power dissipation due to internaltoggling of the ALMs (in W).

Logic block power is a combination of the functionimplemented and the relative toggle rates of thevarious inputs. The PowerPlay EPE spreadsheetuses an estimate based on observed behavior acrossmore than 100 real-world designs.

Use the Quartus II PowerPlay Power Analyzer foraccurate analysis based on the exact synthesis ofyour design.

Thermal Power (W) - Total Indicates the estimated power (in W), based onyour inputs. It is equal to the routing power andblock power.

User Comments Enter any comments. This is an optional entry.

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Figure 4-7: 4-Bit Counter Example

TFFPFN

T Q

CLRN

TFFPFN

T Q

CLRN

TFFPFN

T Q

CLRN

TFFPFN

T Q

CLRN

VCC VCC VCCVCC

cout2cout1cout0clockcout3

OUTPUT cout0cout0

OUTPUT cout3cout3

OUTPUT cout2cout2

OUTPUT cout1cout1

The cout0 output of the first TFF has a toggle percentage of 100% because the signal toggles on everyclock cycle. The toggle percentage for the cout1 output of the second TFF is 50% because the outputtoggles every two clock cycles. Similarly, the toggle rate for the cout2 and cout3 outputs are 25% and12.5%, respectively. Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 +12.5)/4 = 46.875%.

For more information about logic block configurations, refer to the Logic Array Blocks and Adaptive LogicModules chapter of the Arria 10 Device Handbook.

Related Information

• Logic Array Blocks and Adaptive Logic Modules in Arria 10 Devices• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

Arria 10 EPE - RAM WorksheetEach row in the RAM worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a designmodule with RAM blocks of the same type, same data width, same RAM depth (if applicable), same RAMmode, and the same port parameters.

Each row in the RAM worksheet of the PowerPlay EPE spreadsheet can also represent a logical RAMmodule that can be implemented using more than one physical RAM block. The PowerPlay EPEspreadsheet implements each logical RAM module with the minimum number of physical RAM blocks,in the most power-efficient way possible, based on the specified logical width and depth.

You must know how your RAM is implemented by the Quartus II Compiler when you are selecting theRAM block mode. For example, if a ROM is implemented with two ports, it is considered a true dual-portmemory and not a ROM. Single-port and ROM implementations use only one port. Simple dual-port andtrue dual-port implementations use both Port A and Port B.

Note:

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• The PowerPlay Early Power Estimator reports MLAB power in the RAM worksheet. Howeverthe PowerPlay Power Analyzer reports MLAB power as Combinational cell and Register cellblock type in the Thermal Power Dissipation by Block Type section of the power report.

• The PowerPlay Power Analyzer reports LAB clock power as Register cell block type in theThermal Power Dissipation by Block Type section of the power report. The PowerPlay EarlyPower Estimator reports LAB clock power in either the Clock or RAM worksheet, depending onwhether the LAB is used to implement logic or used as MLAB, respectively.

Figure 4-8: RAM Worksheet of the PowerPlay Early Power Estimator

Table 4-7: RAM Worksheet Information


Module Enter a name for the RAM module in this row. Thisis an optional value.

RAM Type Select the implemented RAM type.

You can find the RAM type in the Type column ofthe Quartus II Compilation Report. In the Compila‐tion Report, select Fitter and click ResourceSection. Click Fitter RAM Summary.

# RAM Blocks Enter the number of RAM blocks in the modulethat use the same type and mode and have the sameparameter for each port. The parameters for eachport are as follows:

• Clock frequency in MHz• Percentage of time the RAM is enabled• Percentage of time the port is writing as opposed

to reading

You can find the number of RAM blocks in eitherthe MLAB cells or M20K blocks column of theQuartus II Compilation Report. In the CompilationReport, select Fitter and click Resource Section.Click Fitter RAM Summary.

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Data Width Enter the width of the data for the RAM block. Thisvalue is limited based on the RAM type. You canfind the width of the RAM block in the Port AWidth or the Port B Width column of the Quartus IICompilation Report. In the Compilation Report,select Fitter and click Resource Section. ClickFitter RAM Summary.

For RAM blocks that have different widths for PortA and Port B, use the larger of the two widths.

RAM Depth Enter the depth of the RAM block in number ofwords.

You can find the depth of the RAM block in thePort A Depth or the Port B Depth column of theQuartus II Compilation Report. In the CompilationReport, select Fitter and click Resource Section.ClickFitter RAM Summary.

RAM Mode Select from the following modes:

• Single Port• Simple Dual Port• True Dual Port• Simple Dual Port with ECC• ROM

The mode is based on how the Quartus II Compilerimplements the RAM. If you are unsure how yourmemory module is implemented, Alterarecommends compiling a test case in the requiredconfiguration in the Quartus II software. You canfind the RAM mode in the Mode column of theQuartus II Compilation Report. In the CompilationReport, select Fitter and click Resource Section.Click Fitter RAM Summary.

A single-port RAM has one port with a read and awrite control signal. A simple dual-port RAM hasone read port and one write port. A true dual-portRAM has two ports, each with a read and a writecontrol signal. ROMs are read-only single-portRAMs.

Port A - Clock Freq (MHz) Enter the clock frequency for Port A of the RAMblocks (in MHz). This value is limited by themaximum frequency specification for the RAM typeand device family.

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Port A - Enable % The average percentage of time the Port A clockenable is active, regardless of activity on RAM dataand address inputs. This number must be apercentage between 0% and 100%. RAM power isprimarily consumed when a clock event occurs.Using a clock enable signal to disable a port whenno read or write operation is occurring can result insignificant power savings.

Port A - Read % Enter the percentage of time Port A of the RAMblock is in read mode. This field is applicable onlyfor single port and true dual port RAMs.

This value must be a percentage number between 0and 100%.

Port A - Write % Enter the average percentage of time Port A of theRAM block is in write mode. This field is applicableonly for single port, dual port and true dual portRAMs.

This value must be a percentage number between 0and 100%. The default value is 50%.

Port B - Clock Freq (MHz) Enter the clock frequency for Port B of the RAMblocks (in MHz).

Port B - Enable % Enter the average percentage of time the input clockenable for Port B is active, regardless of the activityon the RAM data and address inputs. The enablepercentage ranges from 0 to 100%.

RAM power is primarily consumed when a clockevent occurs. Using a clock-enable signal to disablea port when no read or write operation is occurringcan result in significant power savings.

Port B - Read % Enter the percentage of time Port B of the RAMblock is in read mode. This field is applicable onlyto dual port and true dual port RAMs and ROMs.

This value must be a percentage number between 0and 100%. This field is only available for Arria 10devices.

Port B - Write % Enter the percentage of time Port B of the RAMblock is in write mode. This field is only availablefor true dual-port mode.

This value must be a percentage number between 0and 100%.

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Toggle % The percentage of clock cycles when the blockoutput signal changes value. This value is multipliedby the clock frequency and the enable percentage todetermine the number of transitions per second.This value affects only routing power.

50% corresponds to a randomly changing signal. Arandom signal changes states only half the time.

Thermal Power (W) - Routing Indicates the power dissipation due to estimatedrouting (in W).

Routing power depends on placement and routing,which is a function of design complexity. The valuesshown represent the routing power estimate basedon observed behavior across more than 100 real-world designs.

Use the Quartus II PowerPlay Power Analyzer foraccurate analysis based on the exact routing used inyour design.

Thermal Power (W) - Block Indicates the power dissipation due to internaltoggling of the RAM (in W).

Use the Quartus II PowerPlay Power Analyzer foraccurate analysis based on the exact RAM modes inyour design.

Thermal Power (W) - Total Indicates the estimated power (in W), based onyour inputs. Total power is equal to the sum ofrouting power and block power.


Related Information

• Embedded Memory Blocks in Arria 10 Devices• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

Arria 10 EPE - DSP WorksheetEach row in the DSP worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a DSPdesign module where all instances have the same configuration, clock frequency, toggle percentage, andregister usage.

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Figure 4-9: DSP Worksheet of the PowerPlay Early Power Estimator

Table 4-8: DSP Worksheet Information


Module Enter a name for the DSP module in this column.This is an optional value.

Configuration Select the DSP block configuration for the module.# of Instances Enter the number of DSP block instances that have

the same configuration, clock frequency, togglepercentage, and register usage. This value is notnecessarily equal to the number of dedicated DSPblocks you use. For example, it is possible to use two18 × 18 simple multipliers that are implemented inthe same DSP block in the FPGA devices. In thiscase, the number of instances would be two.

To determine the maximum number of instancesyou can fit in the device for any particular mode,follow these steps:

1. Open the “Variable Precision DSP Blocks”chapter of the Arria 10 Device Handbook.

2. In the “Number of DSP Blocks” table, take themaximum number of DSP blocks available in thedevice for the mode of operation.

3. Divide the maximum number by the “# ofMults” for that mode of operation from the“DSP Block Operation Modes” table.

4. Use the resulting value for the “# of Instances” inthe PowerPlay EPE spreadsheet.

Clock Freq (MHz) Enter the clock frequency for the module (in MHz).This value is limited by the maximum frequencyspecification for the device family.

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Toggle % Enter the average percentage of DSP data outputstoggling on each clock cycle. The toggle percentageranges from 0 to 50%. The default value is 12.5%.For a more conservative power estimate, use ahigher toggle percentage.

Fifty percent corresponds to a randomly changingsignal, because half the time the signal changes from0 to 0 or from 1 to 1. This is considered the highestmeaningful toggle rate for a DSP block.

Preadder? Select Yes if the PreAdder function of the DSPblock is turned on.

Coefficient? Select Yes if the Coefficient function of the DSPblock is turned on.

Registered Stages Select number of the registered stages. Moreregistered stages increase DSP fMAX but lowerpower consumption.

• 0—None• 1—Input• 2—Input and Output• 3—Input, Output, and Multiplier• 4—Input, Output, Multiplier, and Floating-Point

Adder

Thermal Power (W)–Routing Indicates the power dissipation due to estimatedrouting (in W).

Routing power depends on placement and routing,which is a function of design complexity. The valuesshown represent the routing power estimate basedon observed behavior across more than 100 real-world designs.

Thermal Power (W)–Block Indicates the estimated power consumed by theDSP blocks (in W).

Thermal Power (W)–Total Indicates the estimated power (in W), based onyour inputs. It is the total power consumed by theDSP blocks and is equal to the routing power andblock power.


Related Information

• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

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Arria 10 EPE - Clock WorksheetEach row in the Clock worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a clocknetwork or a separate clock domain.

Arria 10 devices support global, regional, and periphery clock networks. The PowerPlay EPE spreadsheetdoes not distinguish between global or regional clocks because the difference in power is not significant.

Figure 4-10: Clock Worksheet of the PowerPlay Early Power Estimator

Table 4-9: Clock Worksheet Information


Domain Specify a name for the clock domain in this row.This is an optional value.

Clock Freq (MHz) Enter the frequency of the clock domain. This valueis limited by the maximum frequency specificationfor the device family.

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Total Fanout Enter the total number of flipflops, RAMs, digitalsignal processing (DSP) blocks, and I/O pins fed bythis clock.

Power consumed by MLAB clocks is accounted forin the RAM worksheet; therefore, clock fanout onthis worksheet does not include any MLABs drivenby this clock domain.

The number of resources driven by every globalclock and regional clock signal is reported in theFan-out column of the Quartus II CompilationReport. In the Compilation Report, select Fitter andclick Resources Section. Select Global & OtherFast Signals Summary and observe the Fan-outvalue.

Global Enable % Enter the average percentage of time that the entireclock tree is enabled. Each global clock buffer has anenable signal that you can use to dynamically shutdown the entire clock tree.

Local Enable % Enter the average percentage of time that clockenable is high for destination flipflops.

Local clock enables for flipflops in ALMs arepromoted to LAB-wide signals. When a givenflipflop is disabled, the LAB-wide clock is disabled,cutting clock power and the power for down-streamlogic. This worksheet models only the impact onclock tree power.

Utilization Factor Represents the impact of the clock network configu‐ration on power.

Characteristics that have a large impact on powerand are captured by this factor include thefollowing:

• whether the network is widely spread out• whether the fanout is small or large• the clock settings within each LAB

Total Power (W) Indicates the total power dissipation due to clockdistribution (in W).


Note: The PowerPlay Power Analyzer reports LAB clock power as Register cell block type in the ThermalPower Dissipation by Block Type section of the power report. The PowerPlay Early Power Estimatorreports LAB clock power in either the Clock or RAM worksheet, depending on whether the LAB isused to implement logic or used as MLAB, respectively.

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For more information about the clock networks of Arria 10 devices, refer to the Clock Networks and PLLschapter of the Arria 10 Device Handbook.

Related Information

• Clock Networks and PLLs in Arria 10 Devices• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

Arria 10 EPE - PLL WorksheetEach row in the PLL worksheet of the PowerPlay Early Power Estimator for Arria 10 represents one ormore PLLs in the device.

For Arria 10 devices, the supported PLL types are IOPLL, fPLL, ATX PLL, and CMU PLL.

Figure 4-11: PLL Worksheet of the PowerPlay Early Power Estimator

Table 4-10: PLL Worksheet Information


Module Specify a name for the PLL in this column. This isan optional value.

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PLL Type Select whether the PLL is an IOPLL, fPLL, ATXPLL, or CMU PLL.

# PLL Blocks Enter the number of PLL blocks with the samecombination of parameters.

# Counters Enter the number of counters of the PLL. For fPLL,this includes C counter, L counter, and feedback.This field is not applicable for ATX PLLs and CMUPLLs.

VCCR_GXB and VCCT_GXB Voltage Specify the voltage of the VCCR_GXB and VCCT_GXBrails. This field is not applicable for I/O PLLs.

fPLL/IO PLL VCO or ATX/CMU PLL Output Freq(MHz)

For fPLLs and I/O PLLs, enter the internal VCOoperating frequency. For CMU and ATX PLLs,enter the PLL output frequency. When using anfPLL as a transmitter PLL for XCVR channels, VCOfrequency has to be such that required fPLL outputfrequency can be achieved using a legal value of thecounter used for HSSI clock output.

Total Power (W) Shows the total estimated power for this row (in W).


For more information about the PLLs available in Arria 10 devices, refer to the Clock Networks and PLLschapter of the Arria 10 Device Handbook.

Related Information

• Clock Networks and PLLs in Arria 10 Devices• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

Arria 10 EPE - I/O WorksheetEach row in the I/O worksheet of the PowerPlay Early Power Estimator for Arria 10 represents a designmodule where the I/O pins have the same I/O standard, input termination, current strength or outputtermination, data rate, clock frequency, output enable static probability, and capacitive load.

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Figure 4-12: I/O Worksheet of the PowerPlay Early Power Estimator

When using the PowerPlay EPE spreadsheet, it is assumed you are using external termination resistors asrecommended for SSTL and high-speed transceiver logic HSTL. If your design does not use externaltermination resistors, choose the LVTTL/ LVCMOS I/O standard with the same VCCIO and similarcurrent strength as the terminated I/O standard. For example, if you are using the SSTL-2 Class II I/Ostandard with a 16 mA current strength, you must select 2.5 V as the I/O standard and 16 mA as thecurrent strength in the PowerPlay EPE spreadsheet.

To use on-chip termination (OCT), select the Current Strength/Output Termination option in the EPEspreadsheet.

The power reported for the I/O signals includes thermal and external I/O power. The total thermal poweris the sum of the thermal power consumed by the device from each power rail, as shown in the followingequation.

Figure 4-13: Total Thermal Power

thermal power = thermal PVCCP + thermal PVCCR + thermal PVCCIO

The following figure shows the I/O power consumption. The ICCIO power rail includes both the thermalPIO and the external PIO.

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Figure 4-14: I/O Power Representation

VCCP VCCR VCCIO

ICCP ICCR ICCIO

Thermal PVCCP Thermal PR Thermal PIO External PIO

The VREF pins consume minimal current (typically less than 10 μA) and is negligible when comparedwith the current consumed by the general purpose I/O (GPIO) pins; therefore, the PowerPlay EPEspreadsheet does not include the current for VREF pins in the calculations.

Table 4-11: I/O Worksheet Information


Module Specify a name for the I/O in this column. This is anoptional value.

Application Specify the application for this I/O row. GPIO andSerDes interfaces can be instantiated using thisfield. Use the IP worksheet to instantiate EMIFinterfaces.

Bank Type Specifies the type of I/O bank for this row. AnLVDSIO bank supports I/O standards up to 1.8V aswell as LVDS I/O standards. 3V I/O banks supportI/O standards up to 3.0V but not LVDS I/Ostandards.

DDR Rate Specifies the clock rate of PHY logic. Determinesthe clock frequency of PHY logic in relation to thememory clock frequency.

For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz,a quarter rate interface means that the PHY logic inthe FPGA runs at 200MHz.

I/O Buffer Settings - I/O Standard Specifies the I/O standard used by the I/O pins inthis module.


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I/O Buffer Settings - Input Termination Specifies the input termination setting for the inputand bidirectional pins in this module.

I/O Buffer Settings - Current Strength/OutputTermination

Specifies the current strength or output terminationsetting for the output and bidirectional pins in thismodule. Current strength and output terminationare mutually exclusive.

I/O Buffer Settings - Slew Rate Specifies the slew rate setting for the output andbidirectional pins in this module. Using a lowerslew rate setting helps reduce switching noise butmay increase delay.

I/O Buffer Settings - VOD Setting Specifies the differential output voltage (VOD) forthe output and bidirectional pins in the module. Asmaller number indicates a smaller VOD whichreduces static power.

I/O Buffer Settings - Pre-Emphasis Setting Specifies the pre-emphasis setting for the outputand bidirectional pins in this module. A smallernumber indicates a smaller pre-emphasis whichreduces dynamic power.

I/O Buffer Settings - # Input Pins Specifies the number of input-only I/O pins in thismodule. Differential pin pairs count as one pin.

I/O Buffer Settings - # Output Pins Specifies the number of output-only I/O pins in thismodule. Differential pin pairs count as one pin.

I/O Buffer Settings - # Bidir Pins Specifies the number of bidirectional I/O pins inthis module. Differential pin pairs count as one pin.

The I/O pin is treated as an output when its outputenable signal is active and is treated as an inputwhen the output enable signal is disabled.

An I/O pin configured as a bidirectional pin, butused only as an output, consumes more power thanif it were configured as an output-only pin, due tothe toggling of the input buffer every time theoutput buffer toggles (they share a common pin).

I/O Buffer Settings - Data Rate Indicates whether I/O value will change once(Single-Data Rate) or twice (Double-Data Rate) percycle.

I/O Buffer Settings - Registered Pin Indicates whether the pin is registered or not.I/O Buffer Settings - Toggle % Percentage of clock cycles when the I/O signal

changes value. This value is multiplied by clockfrequency to determine the number of transitionsper second. If DDR is selected, the toggle rate ismultiplied by an additional factor of two.

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I/O Buffer Settings - OE % For modules with Input Termination set to OFF,enter the average percentage of time that:

• Output I/O is enabled• Bidirectional I/O is an output and enabled

During the remaining time:

• Output I/O is tri-stated• Bidirectional I/O is an input

Input Termination cannot be active while theOutput I/O is enabled, so for modules with InputTermination not set to OFF, enter the averagepercentage of time that On-Chip Termination isinactive (that is, 1-percentage that the On-ChipTermination is active).This number must be apercentage between 0% and 100%.

I/O Buffer Settings - Load (pF) Specifies pin loading external to the chip (in pF).Applies only to outputs and bidirectional pins. Pinand package capacitance is already included in theI/O model. Include only off-chip capacitance.

SerDes-DPA Settings - SerDes-DPA Mode Selects the mode of SerDes-DPA block.SerDes-DPA Settings - Data Rate (Mbps) The maximum data rate of the SerDes channels in

Mbps.SerDes-DPA Settings - # SerDes Channels The number of channels running at the data rate of

this SerDes domain.SerDes-DPA Settings - Serialization Factor Number of parallel data bits for each serial data bit.I/O Subsystem Clocks - Pin Clock/Memory ClockFrequency (MHz)

Clock frequency (in MHz). 100 MHz with a 12.5%toggle percentage would mean that each I/O pintoggles 12.5 million times per second (100 MHz *12.5%).

I/O Subsystem Clocks - Periphery Clock Freq(MHz)

The I/O subsystem internal PHY clock frequency.This is an output-only field.

In SerDes applications, the PHY clock frequency isa function of the SerDes rate and serializationfactor.

In external memory interface (EMIF) applications,the PHY clock frequency is a function of thememory clock frequency and DDR rate of the EMIFIP.


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I/O Subsystem Clocks - VCO Clock Freq (MHz) The internal VCO operating frequency. This is anoutput-only field.

In SerDes applications, VCO frequency is a functionof SerDes Data rate.

In external memory interface (EMIF) applications,the VCO frequency is a function of the memoryclock frequency of the EMIF IP. The VCOfrequency is not applicable in GPIO mode.

Pin Thermal Power (W) - Digital Power dissipated in the digital domain of the I/O-subsystem including GPIO, EMIF controller andSerDes controller.

Pin Thermal Power (W) - Analog Power dissipated in the analog domain of the I/O-subsystem, for example, I/O buffers.


For more information about the I/O standard termination schemes, refer to I/O and High Speed I/Os inArria 10 Devices.

Related Information

• I/O and High Speed I/O in Arria 10 Devices• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

Arria 10 EPE - I/O-IP WorksheetEach row in the I/O-IP worksheet of the PowerPlay Early Power Estimator for Arria 10 represents adesign module. The I/O-IP worksheet is used to instantiate external memory interface and HPS IPssupported in Arria 10. The I/O-IP worksheet populates other EPE worksheets with resources used by aselected IP.

Analog I/O power and digital power of hard memory controllers and HPS IPs entered on this tab arereported in the Analog Power and Digital Power fields of the I/O worksheet. If the IP uses other resourcetypes (for example Logic or PLL), the power is reported on the corresponding worksheet.

Figure 4-15: I/O-IP Worksheet of the PowerPlay Early Power Estimator

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I/O-IP Worksheet Information


Module Specify a name for the IP in this column. Themodule name depends on the selected IP type. Ithelps to cross-reference each IP module and itscorresponding auto-populated entries on otherworksheets.

IP Specifies the name of the IP in the design.Voltage Specifies the I/O voltage of the signaling between

periphery device and interface.Data Width (Bits) Specifies the interface data width of the specific IP

(in bits).Data Group Width Specifies the number of DQ pins per data group.Memory Device(s) Specifies the number of memory devices connected

to the interface.Address Width Specifies the address width. This value is used to

derive the total number of address pins required.DDR Rate Specifies the clock rate of user logic. Determines the

clock frequency of user logic in relation to thememory clock frequency. For example, if thememory clock sent from the FPGA to the memorydevice is toggling at 800MHz, a "Quarter rate"interface means that the user logic in the FPGAruns at 200MHz.

PHY Rate Specifies the clock rate of PHY logic. Determinesthe clock frequency of PHY logic in relation to thememory clock frequency. For example, if thememory clock sent from the FPGA to the memorydevice is toggling at 800MHz, a "Quarter rate"interface means that the PHY logic in the FPGAruns at 200MHz.

Memory Clock Freq (MHz) Specifies the frequency of memory clock (in MHz).PLL Reference Clock Freq (MHz) Specifies the PLL Reference Clock Frequency (in

MHz).User Comments Enter any comments. This is an optional entry.

Related Information


Arria 10 EPE - XCVR WorksheetThe XCVR worksheet of the PowerPlay Early Power Estimator for Arria 10 allows you to enter XCVRresources and their settings for all modules in your design. The power of transceiver I/O pins is included

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in this worksheet. Transmitters and receivers assume 100 Ω termination. The power of transmitter PLLs isnot included in this worksheet, but is specified in the PLL worksheet instead.

Figure 4-16: XCVR Worksheet of the PowerPlay Early Power Estimator

The PowerPlay Early Power Estimator does not include power estimates for the On-Die Instrumentation(ODI) XCVR block. To estimate power for transceiver channels that include the ODI block, use theQuartus II PowerPlay Power Analyzer.

The Early Power Estimator makes the following simplifying assumptions about the transceiver clocknetwork and the blocks used:

• x6 clock lines are used for all GX channels. GT channels use dedicated GT clock lines. (Refer to theArria 10 Transceiver PHY User Guide for details on the clock line types.)

• For each duplex (both receiver and transmitter active) and transmitter-only row in the XCVRworksheet, there is one master CGB and one reference clock pin per 6 channels. Each row has at leastone master CGB and at least one reference clock pin. Rows with receiver-only channels assume there isone reference clock pin per 6 channels, but no master CGBs. Each row has at least one reference clockpin.

For example, a single-channel duplex design assumes one master CGB and one reference clock pin.The same is true if 6 channels are entered on one row. However, if 6 channels are entered into 6 rows(1 channel per row), each row assumes one master CGB and one reference clock pin, for a total of sixmaster CGBs and six reference clock pins. Consequently, entering the same number of identicalchannels into individual rows results in a slightly different power estimate than if all channels areentered into one row.

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Table 4-12: General Settings in the XCVR Worksheet


Treatment of Unused HSSI Banks Specifies how transceiver banks not actively used bychannels should be treated when calculating staticpower. You can select one of the following options:

• Power Down Unused Side; Minimize Leakage• Power Down Unused Side; Minimize Number of

Supply Voltages• Power Up Unused Side; Minimize Leakage• Power Up Unused Side; Minimize Number of

Supply Voltages

If all high-speed serial interface (HSSI) banks onone side are not used, they can all be powered downor remain powered up. You can select the voltagefor unused-but-powered banks to minimize staticpower (that is, leakage), or to minimize the numberof power supply voltages required.

For example, if active transceiver channels useVCCR_GXB=1.0V and 1.1V, selecting MinimizeLeakage will assume the unused-but-poweredbanks use VCCR_GXB=0.9V, which is the lowestsupported voltage (assuming that the currentlyselected device supports this voltage). SelectingMinimize Number of Supply Voltages will assumethe unused-but-powered banks use VCCR_GXB=1.0V, which is the lowest voltage used by activechannels, thus eliminating the need for the 0.9Vpower supply on VCCR_GXB.

If you select Power Down Unused Side, unusedHSSI banks on the side that has active channels arestill powered. This is because HSSI banks cannot bepowered down individually; only the whole HSSIside can be powered down. For more details, referto the Arria 10 GX, GT, and SX Device Family PinConnection Guidelines.

Each row in the XCVR worksheet represents a separate transceiver domain. Enter the followingparameters for each transceiver domain:

Table 4-13: XCVR Worksheet Information


Module Specifies a name for the module. This is an optionalvalue.


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# of Channels Specifies the number of channels used in thistransceiver domain. Each row represents onetransceiver domain. These channels are groupedtogether in one transceiver bank, or two or moreadjacent transceiver banks and clocked by one ormore common transmitter PLLs.

Note: For PCI Express protocols with Hard IP,the Hard IP block supports x1, x2, x4,and x8 modes. For each row, a minimumnumber of PCI Express Hard IP blocksare instantiated to support the number ofchannels entered. For example, if 5channels are entered, 2 Hard IP blocksare instantiated (one in x4 and one in x1mode).

PCS/HIP Mode Specifies the mode in which the PCS and HIP blockoperates. This mode depends on the communica‐tion protocol or standard that the channels on thisrow implement.

VCCR_GXB and VCCT_GXB Voltage Specifies the voltage of the VCCR_GXB and VCCT_GXBrails. Allowed values depend on the selected deviceand selected data rate.

Operation Mode Specifies whether the hardware is configured in fullduplex transceiver mode (Receiver andTransmitter) or in Receiver Only or TransmitterOnly mode. Allowed values depend on the selectedPCS/HIP mode.

Data Rate (Mbps) Specifies the data rate (in Mbps) for the transceiver.Allowed values depend on the selected protocol,selected device, and the VCCR_GXB and VCCT_GXBvoltages.

PCS/PMA Interface Width Specify the width of the parallel data bus betweenPCS and PMA.

Application Select the application type from Chip-to-Chip,Backplane, or Custom. Select Custom to enablemanual editing of advanced channel options for thecurrent row.

VOD Setting The output differential voltage (VOD) setting of thetransmitter channel PMA. To enable this setting,select Custom in the Application column.

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VOD Voltage The output differential voltage (VOD) of thetransmitter channel PMA (in mV). This voltagedepends on the VOD setting and the VCCT_GXBvoltage. For the purpose of power calculation, it isassumed that the transmitter uses a terminationresistance of 100 Ohms.

Pre-Emphasis Setting–First Pre-Tap Specifies the pre-emphasis setting used by thetransmitter channel PMA. Allowed values forindividual taps depend on selected VOD setting andselected values of other pre-emphasis taps. Toenable these settings, select Custom in the Applica‐tion column.

Pre-Emphasis Setting–Second Pre-TapPre-Emphasis Setting–First Post-TapPre-Emphasis Setting–Second Post-Tap

DFE Specify mode of the decision feedback equalizer(DFE). Allowed values depend on the selected datarate. To enable this setting, select Custom in theApplication column.

Adaptation Specify if the adaptation feature is used. This optionshould be enabled if the channels use either CTLEadaptation or DFE adaptation.To enable thissetting, select Custom in the Application column.

Equalizer Stages Specify whether the continuous time linearequalizer (CTLE) uses high data rate mode (S1Mode) or high gain mode (Non-S1 Mode). Allowedvalues depend on the selected data rate. To enablethis setting, select Custom in the Applicationcolumn.

Transmitter High-Speed Compensation Specifies if the power distribution network (PDN)induced inter-symbol interference (ISI) compensa‐tion is enabled in the TX driver. To enable thissetting, select Custom in the Application column.

Digital Power (W) The total power of the transmitter channel PCS,receiver channel PCS, and PCI Express Hard IPblocks used by all channels on this row (in W).

Analog Power (W) The total power of all analog circuitry on this row(in W). This power excludes power of PCS and PCIExpress Hard IP blocks, whose power is provided inthe Digital Power column, and transmitter PLLs,whose power is provided in the PLL worksheet.


For more information about the transceiver architecture of the supported device families, refer to theTransceiver PHY User Guide for Arria 10.

Related Information

• Arria 10 Transceiver PHY User Guide


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https://documentation.altera.com/#/link/nik1398707230472/nik1398706768037/en-us



Arria 10 EPE - HPS WorksheetThe HPS worksheet of the PowerPlay Early Power Estimator for Arria 10 applies to Arria 10 devices withHPS.

To enable parameter entry into the HPS worksheet, first turn ON the HPS System Switch in the HPSworksheet. For Arria 10 devices, select your peripheral modules in the I/O-IP worksheet. The power of therespective peripheral, except the corresponding I/O power, is shown in this HPS worksheet. To evaluateHPS I/O power, HPS peripherals should be instantiated using the I/O-IP worksheet.

Figure 4-17: HPS Worksheet of the PowerPlay Early Power Estimator

Table 4-14: HPS Worksheet Information

Module Parameters Description

Hard ProcessorSystem

HPS System Switch Turns the HPS system on and off. This selection affects thePSTATIC power.

Total HPS Power(W)

Specifies the total power dissipated by the maximum availableactive processors (in W).

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Module Parameters Description

CPU1/2

Frequency Specifies the operating frequency of the CPU.

Application Select the available benchmark application.

To make changes to user mode utilization, select custom applica‐tion. Total User mode utilization (ALU + L1 + L2) must be <100% per core.

For Arria 10 devices, total utilization of a CPU cannot exceed100%. An error message is displayed if the total utilizationexceeds 100%.

Application Mode Select the available application mode. This setting is onlyapplicable to some applications.

Total Utiliza‐tion (%)

-- Total Utilization for both CPU1 and CPU2. This value rangesfrom 0% to 200%.

CPU1/2Utilization (%)

ALU ALU activity for the specified CPU. This value is determined byApplication and Application mode from both CPU1 and CPU2.To customize the CPU's activity, select Custom from theApplication dropdown menu.

L1 L1 activity for the specified CPU. This value is determined byApplication and Application mode from both CPU1 and CPU2.To customize the CPU's activity, select Custom from theApplication dropdown menu.

L2 L2 activity for the specified CPU. This value is determined byApplication and Application mode from both CPU1 and CPU2.To customize the CPU's activity, select Custom from theApplication dropdown menu.

Related Information


Arria 10 EPE - Report WorksheetThe Report worksheet shows all the information and power estimation results from the PowerPlay EarlyPower Estimator for Arria 10.

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Figure 4-18: Report Worksheet of the PowerPlay Early Power Estimator

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Table 4-15: Power Rail Configuration Settings in the Report Worksheet


Power Rail Configuration Selects a power rail configuration for assignment ofsupply rails to regulator groups.

To enable this field, you must set the PowerCharacteristics setting in the Main worksheet toMaximum.

Choose Custom to manually enter regulator groupselection, or to modify the results of automaticselection.

The Report worksheet provides current requirements for each voltage rail, expressed in terms of staticcurrent, standby current, dynamic current, and total current.

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Table 4-16: Current and Power Regulator Requirements Per Voltage Rail

Module Parameter Description

User Mode Current Require‐ment

Power Supply Indicates the power supply railname and voltage applied to thespecified rail (in V).

Static Current (A) Indicates the component ofcurrent consumed from thespecified power rail wheneverthe power is applied to the rail,independent of circuit activity(in A). This current is dependenton device size, device grade,power characteristics andjunction temperature.

Standby Current (A) Indicates the component ofactive current drawn from thespecified power rail by allmodules on all worksheets,independent of signal activity (inA). This current is independentof device size, device grade,power characteristics andjunction temperature. Standbycurrent includes, but is notlimited to, I/O and transceiverDC bias current.

Dynamic Current (A) Indicates the component ofactive current drawn from thespecified power rail due to signalactivity of all modules on allworksheets (in A). This currentdepends on device size, but isindependent of device grade,power characteristics andjunction temperature.

Total Current (A) Indicates the total currentconsumed from the specifiedpower rail (in A). This value isthe sum of static, standby anddynamic current.

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Module Parameter Description

Power Regulator Settings Regulator Group Indicates the number of theregulator group to which thissupply rail is assigned. Theregulator group numberscorrespond to the groupnumbers shown in the Enpirionworksheet. If one of theautomatic assignment modes isselected in the Power RailConfiguration field, the regulatorgroup numbers also correspondto the group numbers in the pinconnection guidelines. Tomanually edit fields in thiscolumn, select Custom underPower Rail Configuration.

Manual edits may be necessaryto correct grouping errors thatmay result from automaticassignment. To create a newregulator group, enter aregulator group number that ishigher than any other groupnumber already in use.

Related Information


Arria 10 EPE - Enpirion WorksheetEach row in the Regulator Selection table of the Enpirion worksheet of the PowerPlay Early PowerEstimator for Arria 10 represents the power solution for a single regulator group.

Enpirion power devices are available that satisfy the power requirements for the power rails on AlteraFPGA devices. Power devices are selected based on load current, input and output voltages, and power-delivery configuration.

Regulator groups are created by combining rails that can be allowably supplied from the same source.Enpirion device selection is enabled when Power Characteristics in the Main worksheet is set toMaximum, and the Regulator Group section of the Report worksheet is set up correctly with nogrouping errors.

In the following figure, a 12-V off-line regulator supplies input power for Groups 1 and 5. The 3-Vregulator supplying Group 5 also acts as an intermediate bus supplying input power for Groups 2, 3, and4.

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Figure 4-19: Enpirion Worksheet of the PowerPlay EPE Spreadsheet

Table 4-17: Enpirion Worksheet Information


Group The regulator group number for this regulator. Theregulator group numbers correspond to the groupnumbers shown in the Report worksheet.

Regulator Input Voltage (V) Specifies the input voltage for the regulator. Thisfield is filled automatically if you specify a non-zeroParent Group.

Regulator Current Draw (A) Specifies the required input current to the regulator.It is assumed that all regulators have a currentefficiency of 85%.

Voltage (V) Specifies the output voltage for the regulator.Load Current (A) Specifies the load current required by the pins from

the regulator.Load Current Margin Margin added to the load current to account for

component variability. Altera recommends thedefault value of 30% to assure the thermal capabilityof the solution over the full range of device variationand operating conditions. However, in certain caseswhen characteristics and conditions are fullydefined, reducing the margin may lead to a morecost-effective solution. Exercise caution whenchanging these values.

Parent Group Specifies the group number of the regulator thatsupplies input voltage to the regulator in the currentrow. This value is applicable only when the inputvoltage is provided by another regulator on thisworksheet.

Regulator Type In some cases, a linear regulator (LDO) may be agood choice to supply one of the group voltages.The efficiency of an LDO is the ratio of outputvoltage to input voltage. In the figure, Group 2 canbe efficiently supplied by an LDO. If desired, selectLinear in the row for Group 2.

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POK Select Yes to select a regulator with a Power OK(POK) output to assist with sequencing.

Suggested Enpirion Part Suggested Enpirion part is automatically populatedwith the part number of the device that most closelymatches the Load Current (A), Regulator Typeand POK selections. The dropdown can be used tooptionally select devices with equivalent or highercurrent capabilities.

To finalize regulator selection, evaluate the VRMvoltage ripple specification and efficiency againstthe FPGA device requirement from the appropriatedatasheets.

Pin Compatible Parts Pin compatible parts are devices with equivalent orhigher current capabilities that can be placed on thesame PCB footprint as the Suggested EnpirionPart. Additional components or changes tocomponent values may be required when using apin compatible part.

Related Information

• Arria 10 EPE - Report Worksheet on page 4-38• PowerPlay Early Power Estimator for Arria 10 Graphical User Interface on page 3-1• Arria 10 EPE - Common Worksheet Elements on page 4-2

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Factors Affecting the Accuracy of thePowerPlay Early Power Estimator for Arria 10 5

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Many factors can affect the estimated values displayed in the PowerPlay Early Power Estimator for Arria10 spreadsheet. In particular, the input parameters entered concerning toggle rates, airflow, temperature,and heat sinks must be accurate to ensure that the system is modeled correctly in the PowerPlay EPEspreadsheet.

Toggle Rate

The toggle rates specified in the PowerPlay Early Power Estimator for Arria 10 spreadsheet can have alarge impact on the dynamic power consumption displayed. To obtain an accurate estimate, you mustinput toggle rates that are realistic. Determining realistic toggle rates requires knowing what kind of inputthe FPGA is receiving and how often it toggles.

To get an accurate estimate if the design is not complete, isolate the separate modules in the design byfunction, and estimate the resource usage along with the toggle rates of the resources. The easiest way toaccomplish this is to leverage previous designs to estimate the toggle rates for modules with similarfunction.

The input data in the following figure is encoded for data transmission and has a roughly 50% toggle rate.

Figure 5-1: Decoder and Encoder Block Diagram

Decoder RAM Filter Modulator Encoder

Mod Input

Data

In this case, you must estimate the following:

• Data toggle rate• Mod input toggle rate• Resource estimate for the Decoder, RAM, Filter, Modulator, and Encoder module• Toggle rate for the Decoder, RAM, Filter, Modulator, and Encoder module





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You can generate these estimates in many ways. If you used similar modules in the past with data inputsof roughly the same toggle rates, you can leverage that information. If MATLAB simulations are availablefor some blocks, you can obtain the toggle rate information from the simulations. If the HDL is availablefor some of the modules, you can simulate them to obtain toggle rates.

If the HDL is complete, the best way to determine toggle rates is to simulate the design. The accuracy oftoggle rate estimates depends on the accuracy of the input vectors. Therefore, determining whether or notthe simulation coverage is high gives you a good estimate of how accurate the toggle rate information is.

The Quartus II software can determine toggle rates of each resource used in the design if you provideinformation from simulation tools. Designs can be simulated in many different tools and the informationprovided to the Quartus II software through a Signal Activity File (.saf). The Quartus II PowerPlay PowerAnalyzer provides the most accurate power estimate.

Airflow

It is often difficult to place the device adjacent to the fan providing the airflow. The path of the airflowmight traverse a length on the board before reaching the device, thus diminishing the actual airflow thedevice receives. The following figure shows a fan that is placed at the end of the board. The airflow at theFPGA is weaker than the airflow at the fan.

Figure 5-2: Airflow and FPGA Position

FAN

FPGA

You must also consider blocked airflow. The following figure shows a device blocking the airflow from theFPGA, significantly reducing the airflow seen at the FPGA. The airflow from the fan also has to coolboard components and other devices before reaching the FPGA.

Figure 5-3: Airflow with Component and FPGA Positions

FAN

FPGADevice

If you are using a custom heat sink, you do not need to enter the airflow directly into the PowerPlay EPEspreadsheet but it is required to enter the θSA value for the heat sink with the knowledge of what theairflow is at the device. Most heat sinks have fins located above the heat sink to facilitate airflow. Thefollowing figure shows the FPGA with a heat sink.

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2015.03.02

Altera Corporation Factors Affecting the Accuracy of the PowerPlay Early Power Estimator for Arria 10

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Figure 5-4: Airflow and Heat Sinks

FAN

FPGA

Heat Sink FinsHeat Sink

When placing the heat sink on the FPGA, the direction of the fins must correspond with the direction ofthe airflow. A top view shows the correct orientation of the fins.

Figure 5-5: Heat Sink (Top View)

FAN

Heat Sink Fins

These considerations can influence the airflow at the device. When entering information into thePowerPlay EPE spreadsheet, you have to consider these implications to get an accurate airflow value at theFPGA.

Temperature

To calculate the thermal information of the device correctly, you must enter the ambient air temperaturefor the device in the PowerPlay Early Power Estimator for Arria 10 spreadsheet. Ambient temperaturerefers to the temperature of the air around the device. The temperature of the air around the device isusually higher than the ambient temperature outside of the system. To get an accurate representation ofambient temperature for the device, you must measure the temperature as close to the device as possiblewith a thermocouple device.

Entering the incorrect ambient air temperature can drastically alter the power estimates in the PowerPlayEPE spreadsheet. The following figure shows a simple system with the FPGA housed in a box. In this case,the temperature is very different at each of the numbered locations.

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Figure 5-6: Temperature Variances

FAN

1

2

3

4

FPGA

For example, location 3 is where the ambient temperature pertaining to the device should be obtained forinput into the PowerPlay EPE spreadsheet. Locations 1 and 2 are cooler than location 3 and location 4 islikely close to 25 °C if the ambient temperature outside the box is 25 °C. Temperatures close to devices ina system are often in the neighborhood of 50–60 °C but the values can vary significantly. To obtainaccurate power estimates from the PowerPlay EPE spreadsheet, you must get a realistic estimate of theambient temperature near the FPGA device.

Heat Sink

The following equations show how to determine power when using a heat sink.

Figure 5-7: Total Power

Figure 5-8: Junction–to–Ambient Thermal Resistance

θJA = θJC+ θCS + θSA

You can obtain the junction-to-case thermal resistance ( θJC) value that is specific to the FPGA from thedata sheet. The case-to-heat-sink thermal resistance (θCS) value refers to the material that binds the heatsink to the FPGA and is approximated to be 0.1 °C/W. You can obtain the heat sink-to-ambient thermalresistance (θSA) value from the manufacturer of the heat sink. Ensure that you obtain this value for theright conditions for the FPGA, which include analyzing the correct heat sink information at theappropriate airflow at the device.

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Altera Corporation Factors Affecting the Accuracy of the PowerPlay Early Power Estimator for Arria 10

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Additional Information for the PowerPlay EarlyPower Estimator for Arria 10 User Guide 6

2015.03.02


Document Revision History for the PowerPlay Early Power Estimator forArria 10 User Guide

Date Version Changes

March 2015 2015.03.02 Initial release.





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