ebts volume 2 – base radios - motorola iden

Technical Manual

iDEN

Enhanced Base Trans-ceiver System (EBTS)

Volume 2 of 3
Base Radios 68P80801E35-E
1-Dec-06

RF SUB-SYSTEM

Notice to Users

No part of this publication, or any software included with it, may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, including but not limited to, photocopying, electronic, mechanical, recording or otherwise, without the express prior written permission of the copyright holder. Motorola, Inc. provides this document “AS IS” without warranty of any kind, either expressed or implied, including but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Motorola reserves the rights to make changes or improvements in the equipment, software, or specifications described in this document at any time without notice. These changes will be incorporated in new releases of this document.

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The software described in this document is the property of Motorola, Inc. It is furnished under a duly executed license agreement and may be used and/or disclosed only in accordance with the terms of the said agreement.

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© 2006 - Motorola, Inc. All Rights Reserved REV 12/15/06

Contact Information

Motorola, Inc.Networks business1501 Shure Dr.Arlington Heights, IL 60004U.S.A

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

While reasonable efforts have been made to assure the accuracy of this document, this document may contain technical or typographical errors or omissions. Motorola, Inc. and its subsidiaries and affiliates disclaim responsibility for any labor, materials, or costs incurred by any person or party as a result of using this document. Motorola, Inc., any of its subsidiaries or affiliates shall not be liable for any damages (including, but not limited to, consequential, indirect, incidental, or special damages or loss of profits or data) even if they were foreseeable and Motorola has been informed of their potential occurrence, arising out of or in connection with this document or its use. Motorola, Inc. reserves the right to make changes without notice to any products or services described herein and reserves the right to make changes from time to time in content of this document and substitute the new document therefor, with no obligation to notify any person or party of such changes or substitutions.

Table of Contents0

List of Tables ................................................................................... iv

List of Figures ................................................................................ viii

About This Volume

Audience Profile .............................................................................. vi

Related Manuals ............................................................................ vii

Customer Network Resolution Center ........................................... viii

Manuals On-line .............................................................................. ix

Reporting Manual Errors ..................................................................x

Conventions .................................................................................... xi

Product Specific Safety Notices ..................................................... xii

General Safety .............................................................................. xiii

Revision History ...........................................................................xviii

Base Radio

Overview ...................................................................................... 1-2

Legacy Single Carrier 800 MHz Base Radio Overview ................ 1-3

Generation 2 Single Channel 800 MHz Base Radio Overview .... 1-8

QUAD Channel 900 MHz Base Radio Overview ........................ 1-15


QUAD+2 Base Radio Overview ................................................. 1-25

Base Radio Controllers

Overview ...................................................................................... 2-2

800 MHz Legacy Base Radio Controller ...................................... 2-3

Enhanced Base Radio Controller ............................................... 2-15

900 MHz QUAD Channel Base Radio Controller ....................... 2-28


Base Radio Transceiver

Overview ...................................................................................... 3-2

QUAD+2 Channel Base Radio Transceiver ................................. 3-3

Base Radio Exciter

Overview ...................................................................................... 4-2

800 Legacy MHz Exciter – TLN3337 ............................................ 4-3

Low Noise 800 MHz Exciter ......................................................... 4-8

QUAD Channel 900 MHz Exciter ............................................... 4-12

Enhanced Base Transceiver System (EBTS)

1-Dec-06 68P80801E35-E i

Table of Contents 0


Power Amplifier

Overview ...................................................................................... 5-2

Power Amplifier Overview ............................................................ 5-3

PA Theory of Operation ............................................................... 5-7

Power Supply

Overview ...................................................................................... 6-2

Single Channel DC Power Supply Overview ................................ 6-3

DC Power Supply for QUAD Channel Base Radios ..................... 6-6

DC Power Supply for QUAD+2 Channel Base Radios ................ 6-9

Receiver

Overview ...................................................................................... 7-2

800 MHz 3X Receiver – CLN1283 ............................................... 7-3

800 MHz QUAD Receiver - CLN1283900 MHz QUAD Receiver - DLN1201 ........................................ 7-10

Fan Assembly

Overview ...................................................................................... 8-2

Troubleshooting

Overview ...................................................................................... 9-2

Troubleshooting Preliminaries ...................................................... 9-3

Legacy Single Channel Base Radio FRU Replacement Procedures .................................................... 9-6

Legacy Single Channel BR Station Verification Procedures ........ 9-9

Legacy Single Channel Base Radio Backplane ......................... 9-22

Generation 2 Single Channel Base Radio FRU Replacement Procedures .................................................. 9-42

Generation 2 Single Channel BR Station Verification Procedures .............................................................. 9-45

Generation 2/EBRC Single Channel Base Radio Backplane ..... 9-66

QUAD Channel Base Radio/Base Radio FRU Replacement Procedures .................................................. 9-82

QUAD Base Radio Station Verification Procedures ................... 9-86

QUAD Channel BR Backplane ................................................. 9-117

QUAD Base Radio Signals ....................................................... 9-132


ii 68P80801E35-E 1-Dec-06

Table of Contents0

QUAD+2 Channel Base Radio/Base Radio FRU Replacement Procedures ................................................ 9-136

QUAD+2 Base Radio Station Verification Procedures ............. 9-142

QUAD+2 Channel BR Backplane ............................................. 9-178

QUAD+2 Base Radio Signals .................................................. 9-190

Parts and Suppliers

Overview ......................................................................................A-2

Surge Arrestors ............................................................................A-3

RF Attenuators .............................................................................A-5

Emergency Generator ..................................................................A-7

Portable Generator Connection ...................................................A-8

Site Alarms ...................................................................................A-9

Cabinet Mounting Hardware .......................................................A-11

Cable Connections .....................................................................A-12

Battery System Connections ......................................................A-13

Intercabinet Cabling ...................................................................A-16

Equipment Cabinet Power Connections .....................................A-18

Other Recommended Suppliers .................................................A-20

Spare Parts Ordering .................................................................A-22


1-Dec-06 68P80801E35-E iii

Volume 2

List of Tables

List of Tables 0

Table 1-1 FRU Number to Kit Number Cross Reference ....................................... 1-2Table 1-2 BR General Specifications ..................................................................... 1-4Table 1-3 Transmit Specifications .......................................................................... 1-5Table 1-4 Receive Specifications ........................................................................... 1-5Table 1-5 EBRC Compatibility................................................................................ 1-9Table 1-6 Generation 2 BR General Specifications.............................................. 1-11Table 1-7 Transmit Specifications ........................................................................ 1-12Table 1-8 Receive Specifications ......................................................................... 1-13Table 1-9 QUAD Channel 900 MHz BR General Specifications .......................... 1-16Table 1-10 QUAD Channel 900 MHz BR Transmit Specifications ......................... 1-17Table 1-11 QUAD Channel 900 MHz Receive Specifications ................................ 1-17Table 1-12 QUAD Channel 800 MHz BR General Specifications .......................... 1-21Table 1-13 QUAD Channel 800 MHz Transmit Specifications ............................... 1-22Table 1-14 QUAD Channel 800 MHz Receive Specifications ................................ 1-22Table 1-15 QUAD+2 Channel BR General Specifications ..................................... 1-27Table 1-16 QUAD+2 Channel BR Transmit Specifications .................................... 1-28Table 1-17 QUAD+2 Channel Receive Specifications ........................................... 1-29

Table 2-1 FRU Number to Kit Number Cross Reference ....................................... 2-2Table 2-2 Legacy BR Controller Indicators............................................................. 2-5Table 2-3 Legacy BR Controller Controls............................................................... 2-6Table 2-4 Pin-outs for the STATUS Connector ...................................................... 2-6Table 2-5 Legacy BR Controller Circuitry ............................................................... 2-7Table 2-6 Host Glue ASIC Functions ..................................................................... 2-8Table 2-7 EBRC Compatibility.............................................................................. 2-15Table 2-8 EBRC Indicators................................................................................... 2-19Table 2-9 EBRC Controls ..................................................................................... 2-20Table 2-10 Pin-outs for the STATUS Connector .................................................... 2-20Table 2-11 EBRC Circuitry ..................................................................................... 2-21Table 2-12 900 MHz QUAD Channel BR Controller Indicators .............................. 2-29Table 2-13 900 MHz QUAD Channel BR Controller Controls ................................ 2-31Table 2-14 Pin-outs for the STATUS Connector .................................................... 2-31Table 2-15 900 MHz QUAD Channel BR Controller Circuitry ................................ 2-32Table 2-16 800 MHz QUAD Channel BR Controller Indicators .............................. 2-40Table 2-17 800 MHz QUAD Channel BR Controller Controls ................................ 2-42Table 2-18 Pin-outs for the STATUS Connector .................................................... 2-42Table 2-19 BR Controller Circuitry.......................................................................... 2-43

Table 3-1 FRU Number to Kit Number Cross Reference ....................................... 3-2Table 3-2 Transceiver Connections........................................................................ 3-6Table 3-3 XCVR Front Switch Functions................................................................ 3-7Table 3-4 QUAD+2 Channel Base Radio Status and Alarm LED Indications ........ 3-7Table 3-5 QUAD+2 Channel Base Radio Transceiver LED Indications................. 3-7Table 3-6 QUAD+2 Channel Base Radio Band State ............................................ 3-8Table 3-7 Control Section Circuitry......................................................................... 3-9Table 3-8 Exciter Board Circuitry.......................................................................... 3-17


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Volume 2

List of Tables

Table 3-9 Receiver Circuitry ................................................................................. 3-20

Table 4-1 FRU Number to Kit Number Cross Reference ....................................... 4-2Table 4-2 Exciter Circuitry ...................................................................................... 4-4Table 4-3 Exciter Circuitry ...................................................................................... 4-9Table 4-4 900 MHz Exciter Circuitry..................................................................... 4-13Table 4-5 Exciter Circuitry .................................................................................... 4-17

Table 5-1 FRU Number to Kit Number Cross Reference ....................................... 5-2Table 5-2 Power Amplifier Circuitry ........................................................................ 5-7

Table 6-1 FRU Number to Kit Number Cross Reference ....................................... 6-2Table 6-2 DC Power Supply Indicators .................................................................. 6-4Table 6-3 DC Power Supply Specifications............................................................ 6-4Table 6-4 DC Power Supply Circuitry..................................................................... 6-5Table 6-5 DC Power Supply Indicators .................................................................. 6-7Table 6-6 DC Power Supply Specifications............................................................ 6-7Table 6-7 DC Power Supply Circuitry..................................................................... 6-8Table 6-8 Power Supply Indicators....................................................................... 6-10Table 6-9 Power Supply ON/OFF Switch ............................................................. 6-10Table 6-10 DC Power Supply Specifications.......................................................... 6-10Table 6-11 Power Supply Circuitry ......................................................................... 6-11

Table 7-1 FRU Number to Kit Number Cross Reference ....................................... 7-2Table 7-2 Receiver FRUs ....................................................................................... 7-4Table 7-3 800 MHz Base Radio Receiver Board/BR Backplane Compatibility ...... 7-4Table 7-4 900 MHz Base Radio Receiver Board/BR Backplane Compatibility ...... 7-4Table 7-5 Receiver ROM Compatibility .................................................................. 7-5Table 7-6 Receiver Circuitry ................................................................................... 7-7Table 7-7 QUAD Receiver Circuitry...................................................................... 7-12

Table 8-1 FRU Number to Kit Number Cross Reference ....................................... 8-2

Table 9-1 Recommended Test Equipment............................................................. 9-3Table 9-2 Legacy BR 40W, 800 MHz PA Transmitter Parameters ...................... 9-12Table 9-3 Legacy BR 70W, 800 MHz PA Transmitter Parameters ...................... 9-16Table 9-4 Legacy Base Radio Backplane Connectors ......................................... 9-22Table 9-5 Legacy BR RF Connector Code........................................................... 9-24Table 9-6 Legacy BR P1 Connector Pin-outs....................................................... 9-24Table 9-7 Legacy BR P1 Connector Pin-outs....................................................... 9-25Table 9-8 Legacy BR P2 Connector Pin-outs....................................................... 9-27Table 9-9 Legacy BR P3 Connector Pin-outs....................................................... 9-28Table 9-10 Legacy BR P2 Connector Pin-outs....................................................... 9-29Table 9-11 Legacy BR P3 Connector Pin-outs....................................................... 9-30Table 9-12 Legacy BR P5 Connector Pin-outs....................................................... 9-30Table 9-13 Legacy BR P6 Connector Pin-outs....................................................... 9-32Table 9-14 Legacy BR P7 Connector Pin-outs....................................................... 9-33Table 9-15 Legacy BR P8 Connector Pin-outs....................................................... 9-34Table 9-16 Legacy BR P13 Connector Pin-outs..................................................... 9-34Table 9-21 Legacy BR P9 Connector Pin-outs....................................................... 9-35


1-Dec-06 68P80801E35-E v

Volume 2

List of Tables

Table 9-17 Legacy BR SMA Connectors- Receivers ............................................. 9-35Table 9-18 Legacy BR Blind Mates - BRC ............................................................. 9-35Table 9-19 Legacy BR Blind Mates - Exciter.......................................................... 9-35Table 9-20 Legacy BR Blind Mates - PA ................................................................ 9-35Table 9-22 Legacy Base Radio Signal Descriptions .............................................. 9-39Table 9-23 Generation 2 BR Transmitter Parameters............................................ 9-49Table 9-24 BR Backplane Signal Descriptions....................................................... 9-66Table 9-25 Generation 2 Base Radio Backplane Connectors................................ 9-68Table 9-26 P1 Gen 2/BR Connector Pin-outs ........................................................ 9-70Table 9-27 Gen 2 BR P2 Rx Signal Connector Pinouts ......................................... 9-72Table 9-28 Gen 2 BR P3 3X Receiver Pin-outs ..................................................... 9-72Table 9-29 Gen 2 BR P5 Exciter Connector Pin-outs ............................................ 9-73Table 9-30 Gen 2 BR P6 PA Connector Pin-outs................................................... 9-74Table 9-31 Gen 2 BR P7 External Alarm Connector Pin-outs................................ 9-76Table 9-32 Gen 2 BR P8 External RS232 Connector Pin-outs .............................. 9-77Table 9-33 Gen2 BR P9 Power Connector ............................................................ 9-77Table 9-34 Gen 2 BR P11 Ethernet Connector Pinout........................................... 9-80Table 9-35 Gen 2 BR P12 DC In Connector .......................................................... 9-80Table 9-36 Gen 2 BR P13 Connector Pin-outs ...................................................... 9-81Table 9-37 Gen 2 BR SMA Connectors- Receivers ............................................... 9-81Table 9-38 Gen 2 BR Blind Mates - BRC............................................................... 9-81Table 9-39 Gen 2 BR Blind Mates - Exciter............................................................ 9-81Table 9-40 Gen 2 BR Blind Mates - PA.................................................................. 9-81Table 9-41 QUAD BR Transmitter Parameters ...................................................... 9-91Table 9-42 QUAD BR Backplane Connectors...................................................... 9-117Table 9-43 EXBRC P1 Pinout, Signal and Power ................................................ 9-119Table 9-44 EXBRC P13 Pinout, Exciter from PA ................................................. 9-120Table 9-45 EXBRC P14 Pinout, Exciter to PA...................................................... 9-120Table 9-46 EXBRC P15 Pinout, Ethernet............................................................. 9-121Table 9-47 RX1 P2 Pinout, Signal and Power...................................................... 9-121Table 9-48 RX1 P3 Pinout, RF Input and Output Connection .............................. 9-122Table 9-49 RX2 P4 Pinout, Signal and Power...................................................... 9-122Table 9-50 RX2 P5 Pinout, RF Input and Output Connection .............................. 9-123Table 9-51 RX3 P6 Pinout, Signal and Power...................................................... 9-123Table 9-52 RX3 P7 Pinout, RF Input and Output Connection .............................. 9-124Table 9-53 RX4 P8 Pinout, Signal and Power...................................................... 9-125Table 9-54 RX4 P9 Pinout, RF Input and Output Connection .............................. 9-125Table 9-55 QUAD BR PA P10 Pinout, Signal and Power .................................... 9-126Table 9-56 EXBRC P16 Pinout, PA from Exciter ................................................. 9-127Table 9-57 EXBRC P17 Pinout, PA to Exciter...................................................... 9-127Table 9-58 EXBRC P18 Pinout, PA RF OUT ....................................................... 9-127Table 9-59 QUAD BR Backplane Coaxial and DC............................................... 9-128Table 9-60 QUAD BR Backplane Alarm 25 Pin Dsub (P23) ................................ 9-128Table 9-61 QUAD BR Backplane RS-232 9 Pin Dsub (P22)................................ 9-129Table 9-62 QUAD PS Power and Signal (P11) .................................................... 9-130Table 9-63 QUAD BR 48 Vdc Battery Power (P12) ............................................. 9-131Table 9-64 QUAD Base Radio Signal Descriptions.............................................. 9-132Table 9-65 QUAD+2 BR Transmitter Parameters ................................................ 9-147Table 9-66 QUAD+2 BR Backplane Connectors.................................................. 9-178Table 9-67 XCVR Digital Connector (P1011 and P1012)..................................... 9-180


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Volume 2

List of Tables

Table 9-68 XCVR RF Connector (P1013) ............................................................ 9-183Table 9-69 PA DC Connector (J1000).................................................................. 9-183Table 9-70 PA RF Connector (P1010) ................................................................. 9-184Table 9-71 RF (SMA) Connector (P1002, P1003, and P1004) ............................ 9-185Table 9-72 5MHz/1PPS - Time/Frequency (P1000)............................................. 9-185Table 9-73 Site Control Ethernet 10Base2 (P1001) ............................................. 9-185Table 9-74 For Future Use - Ethernet/Reference (J1002 & J1003) ..................... 9-186Table 9-75 Peripheral - 25-pin Dsub (P1005)....................................................... 9-186Table 9-76 DC I/O (J1001) ................................................................................... 9-187Table 9-77 AC Connector (AC) ............................................................................ 9-188Table 9-78 Aux I/O (P1006).................................................................................. 9-189Table 9-79 QUAD+2 DC Input (P1008)................................................................ 9-189Table 9-80 QUAD+2 Fan Power/Alarm (P1009) .................................................. 9-189Table 9-81 QUAD+2 Base Radio Signal Descriptions ......................................... 9-190


1-Dec-06 68P80801E35-E vii

Volume 2

List of Figures

List of Figures 0

Figure 1-1 Legacy Base Radio (Typical) ................................................................................ 1-3Figure 1-2 Generation 2 Base Radio (Typical) ...................................................................... 1-8Figure 1-3 QUAD Channel 900 MHz Base Radio (Typical) ................................................. 1-15Figure 1-4 QUAD Channel 800 MHz Base Radio (Typical) ................................................. 1-20Figure 1-5 QUAD+2 Base Radio (Typical) .......................................................................... 1-25Figure 1-6 QUAD+2 Base Radio (with Access Panel opened) ........................................... 1-26Figure 1-7 QUAD+2 Base Radio (with Fan Cover removed) .............................................. 1-26Figure 1-8 800 MHz Legacy Base Radio Functional Block Diagram.................................... 1-33Figure 1-9 Generation 2 Single Channel 800 MHz Base Radio Functional Block Diagram. 1-34Figure 1-10 800 and 900 MHZ QUAD Channel Base Radio Functional Block Diagram........ 1-35Figure 1-11 QUAD+2 Channel Base Radio Functional Block Diagram.................................. 1-36

Figure 2-1 Legacy Base Radio Controller, version CLN1469 (with cover removed) .............. 2-3Figure 2-2 Legacy Base Radio Controller, version CLN1472 (with cover removed) ............. 2-4Figure 2-3 Legacy BR Controller (Front View) ....................................................................... 2-4Figure 2-4 Enhanced Base Radio Controller, version CLN1653 (with cover removed) ...... 2-18Figure 2-5 EBRC (Front View) ............................................................................................. 2-18Figure 2-6 900 MHz QUAD Channel Base Radio Controller, version DLN1203

(with cover removed) ......................................................................................... 2-28Figure 2-7 900 MHz QUAD Channel BR Controller (Front View)......................................... 2-29Figure 2-8 800 MHz QUAD Channel Base Radio Controller, version CLN1469

(with cover removed) ......................................................................................... 2-39Figure 2-9 800 MHz QUAD Channel BR Controller (Front View) ........................................ 2-40Figure 2-10 800/900 MHz Base Radio Controller Functional Block Diagram (Sheet 1 of 2) . 2-51Figure 2-11 800/900 MHz Base Radio Controller Functional Block Diagram (Sheet 2 of 2).. 2-52Figure 2-12 Enhanced Base Radio Controller Functional Block Diagram (Sheet 1 of 2) ....... 2-53Figure 2-13 Enhanced Base Radio Controller Functional Block Diagram (Sheet 2 of 2) ....... 2-54Figure 2-14 800 and 900 MHz QUAD Channel Base Radio Controller

Functional Block Diagram (Sheet 1 of 2) ........................................................... 2-55Figure 2-15 800 and 900 MHz QUAD Channel Base Radio Controller

Functional Block Diagram (Sheet 2 of 2) ........................................................... 2-56

Figure 3-1 800/900 MHz QUAD+2 Channel Transceiver (Front View) .................................. 3-3Figure 3-2 800/900 MHz QUAD+2 Transceiver Information Flow.......................................... 3-4Figure 3-3 800/900 MHz QUAD+2 QUAD+2 Transceiver (with access door opened)........... 3-5Figure 3-4 800/900 MHz QUAD+2 Transceiver Backplane (Rear View) ............................... 3-6Figure 3-5 Controller Section (with housing removed) ........................................................ 3-10Figure 3-6 Exciter Board (with housing removed) ............................................................... 3-18Figure 3-7 Receiver Board (with housing removed) ............................................................. 3-21Figure 3-8 QUAD+2 Control Section Functional Block Diagram ......................................... 3-25Figure 3-9 QUAD+2 Exciter Functional Block Diagram ....................................................... 3-26Figure 3-10 QUAD+2 Receiver Board Functional Block Diagram ......................................... 3-27

Figure 4-1 800 MHz Exciter (with cover removed) ................................................................ 4-3Figure 4-2 Low Noise 800 MHz Exciter (with cover removed) .............................................. 4-8Figure 4-3 900 MHz QUAD Channel Exciter (with cover removed) .................................... 4-12


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Volume 2

List of Figures

Figure 4-4 800 MHz QUAD Channel Exciter (with cover removed) .................................... 4-16Figure 4-5 Legacy Exciter Functional Block Diagram ......................................................... 4-21Figure 4-6 Low Noise Exciter Functional Block Diagram .................................................... 4-22Figure 4-7 800 and 900 MHz Exciter Board Functional Block Diagram .............................. 4-23

Figure 5-1 40W - 800 MHz PA – TLF2020 (cover removed).................................................. 5-4Figure 5-2 70W - 800 MHz PA – TLN3335 (cover removed) ................................................ 5-5Figure 5-3 800/900 MHz QUAD PA ...................................................................................... 5-6Figure 5-4 QUAD+2 PA ......................................................................................................... 5-6Figure 5-5 40W - 800 MHz PA Functional Block Diagram .................................................. 5-17Figure 5-6 70W - 800 MHz PA Functional Block Diagram .................................................. 5-18Figure 5-7 800 MHz QUAD Power Amplifier Functional Block Diagram ............................. 5-19Figure 5-8 900 MHz QUAD Power Amplifier Functional Block Diagram ............................. 5-20Figure 5-9 QUAD+2 Power Amplifier Functional Block Diagram ........................................ 5-21

Figure 6-1 Single Channel DC Power Supply ....................................................................... 6-3Figure 6-2 Quad Carrier Power Supply ................................................................................. 6-6Figure 6-3 Quad+2 Power Supply (Front and Rear Views) ................................................... 6-9Figure 6-4 DC Power Supply Functional Block Diagram (Sheet 1 of 2) .............................. 6-15Figure 6-5 DC Power Supply Functional Block Diagram (Sheet 2 of 2) .............................. 6-16Figure 6-6 QUAD DC Power Supply Functional Block Diagram (Sheet 1 of 2) ................... 6-17Figure 6-7 QUAD DC Power Supply Functional Block Diagram (Sheet 2 of 2) ................... 6-18Figure 6-8 QUAD+2 DC Power Supply Functional Block Diagram ..................................... 6-19

Figure 7-1 3X Receiver (with cover removed) ....................................................................... 7-3Figure 7-2 QUAD Receiver (with housing removed) ........................................................... 7-10Figure 7-3 3X Receiver Functional Block Diagram ............................................................. 7-15Figure 7-4 800 and 900 MHz QUAD Receiver Functional Block Diagram .......................... 7-16

Figure 8-1 Fan Assembly ...................................................................................................... 8-2

Figure 9-1 Procedure One Troubleshooting Flowchart ......................................................... 9-4Figure 9-2 Procedure Two Troubleshooting Flowchart ......................................................... 9-5Figure 9-3 Transmitted Signal Spectrum (800 MHz Legacy BR) ........................................ 9-14Figure 9-4 Transmitted Signal Spectrum (800 MHz Legacy BR) ........................................ 9-17Figure 9-5 Legacy Base Radio Backplane Connectors ....................................................... 9-23Figure 9-6 Generation 2 Carrier Spectrum........................................................................... 9-50Figure 9-7 Generation 2 BR w/ RFDS Verification Test Setup............................................. 9-56Figure 9-8 RX Verification Test Setup.................................................................................. 9-59Figure 9-9 Generation 2 Base Radio Backplane Connectors ............................................. 9-70Figure 9-10 800 MHz QUAD Carrier Spectrum...................................................................... 9-92Figure 9-11 900 MHz QUAD Carrier Spectrum ..................................................................... 9-93Figure 9-12 QUAD BR w/ RFDS Verification Test Setup ...................................................... 9-96Figure 9-13 QUAD BR Rx Verification Test Setup. .............................................................. 9-107Figure 9-14 QUAD Base Radio Backplane Connectors ...................................................... 9-118Figure 9-15 800 MHz QUAD+2 Carrier Spectrum ............................................................... 9-148Figure 9-16 900 MHz QUAD+2 Carrier Spectrum ............................................................... 9-149Figure 9-17 QUAD+2 BR w/ RFDS Verification Test Setup ................................................ 9-152Figure 9-18 QUAD+2 BR Rx Verification Test Setup .......................................................... 9-165Figure 9-19 QUAD+2 Base Radio Backplane Connectors (Module-Side) .......................... 9-179


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Volume 2

List of Figures

Figure 9-20 QUAD+2 Base Radio Backplane Connectors (External) ................................. 9-180

Figure A-1 Portable Generator Connector .............................................................................A-8


x 68P80801E35-E 1-Dec-06

About This Volume

Volume 2 of the Enhanced Base Transceiver System (EBTS) manual, Base Radios, provides the experienced service technician with an overview of the EBTS operation and functions, and contains information regarding the 800 MHz, 900 MHz, 800/900 MHz QUAD Channel, and 800/900 MHz QUAD+2 Channel base radios.

The EBTS has three major components: Generation 3 Site Controller (Gen 3 SC) or integrated Site Controller (iSC) Base Radios (BRs) RF Distribution System (RFDS)

Installation and testing is described in Volume 1, System Installation and Testing, and RFDS are described in Volume 3, RF Distribution Systems (RFDS). Detailed information about the Gen 3 SC is contained in the Gen 3 SC Supplement Manual, 68P80801E30. Detailed information about the iSC is contained in the iSC Supplement Manual, 68P81098E05

The information in this manual is current as of the printing date. If changes to this manual occur after the printing date, they will be documented and issued as Schaumburg Manual Revisions (SMRs).


1-Dec-06 68P80801E35-E -v

About This Volume Volume 2

Audience Profile

Audience Profile 0

The target audience of this document includes field service technicians responsible for installing, maintaining, and troubleshooting the EBTS.

In keeping with Motorola’s field replaceable unit (FRU) philosophy, this manual provides sufficient functional information to the FRU level. Please refer to the appropriate section of this manual for removal and replacement instructions.


-vi 68P80801E35-E 1-Dec-06

Volume 2 About This Volume

Related Manuals

Related Manuals 0

The following publications may be required to supplement the information contained in this manual:

Number Title Description

68P80801E30Generation 3 Site Controller(Gen 3 SC) - System Manual

Provides detailed information about the Gen 3 SC including a description of major subsystems, components, installation, testing, troubleshooting, and other information

68P81098E05Integrated Site Controller (iSC)System Manual

Provides detailed information about the iSC including a description of major subsystems, components, installation, testing, troubleshooting, and other information.

68P81089E50Motorola Standards and Guidelines for Communications Sites

A useful reference for the installation of fixed network equipment. This manual provides guidelines and procedures to ensure the quality of Motorola radio equipment installation, integration, optimization, and maintenance. Field service personnel should be familiar with the guidelines and procedures contained in this publication.

68P81131E90iDEN Guide to Motorola Acronyms and Terms

A useful reference for Motorola used Acronyms and Terms.


1-Dec-06 68P80801E35-E -vii


Customer Network Resolution Center

Customer Network Resolution Center 0

The Customer Network Resolution Center (CNRC) is a integral part of the network support process.

Before performing any major changes or optimization on the system, please contact the CNRC. Notify the CNRC with the nature of the change and the schedule for the change. This will allow CNRC to have the correct technical support engineers on call in case they are needed.

Please refer to the Customer Guide to iDEN Customer Network Resolution Center (CNRC) (WP2000-003) for more information regarding: Procedures for calling CNRC Classification of trouble tickets The escalation processes

This document is located on the iDEN extranet website at the URL:

http://mynetworksupport.motorola.com

The CNRC can be contacted at the following telephone numbers:

United States and Canada

1-800- 499-6477

International1-847-704-9800

Note Toll-free international access codes are available for many locations. Please refer to Appendix E of the Customer Guide to iDEN Customer Network Resolution Center (WP2000-003) for a list of these access codes and dialing instructions.


-viii 68P80801E35-E 1-Dec-06


Manuals On-line

Manuals On-line 0

This manual is available on the World Wide Web at mynetworksupport, the iDEN customer site. This site was created to provide secure access to critical iDEN Infrastructure information. This web site features a library of iDEN Infrastructure technical documentation such as bulletins, system release documents and product manuals.

The documents are located on the secured extranet website at the URL:

https://mynetworksupport.motorola.com

For information on obtaining an account on this site, go to:

https://membership.motorola.com/motorola


1-Dec-06 68P80801E35-E -ix


Reporting Manual Errors

Reporting Manual Errors 0

If you locate an error or identify a deficiency in this manual, please take the time to contact us at the following email address:

[email protected]

Be sure to include your name, fax or phone number, the complete manual title and part number, the page number where the error is located, and any comments you may have regarding what you have found.

Thank you for your time. We appreciate any comments from the users of our manuals.


-x 68P80801E35-E 1-Dec-06


Conventions

Conventions 0

Software submenu commands—Table > Table Designer

new terms—mobile subscriber

keystrokes—Ctrl+Alt+Delete, Return

mouse clicks—click, double-click user input—Type delete

screen output—DAP is starting....

Hardware CD-ROM

Safety This manual contains safety notices (alerts). Alerts are based on the standards that apply to graphics on Motorola equipment. Specific procedural notices are stated in the procedures as required and have specific visual representations. The representations are:

! DANGER

INDICATES AN IMMINENTLY HAZARDOUS SITUATION WHICH, IF NOT AVOIDED, WILL RESULT IN DEATH OR SERIOUS INJURY.

! WARNING

Indicates a potentially hazardous situation which, if not avoided, could result in death or serious injury.

! CAUTION

Indicates a potentially hazardous situation which, if not avoided, could result in minor or moderate injury.

CAUTIONWithout the alert symbol indicates a potentially hazardous situation which, if not avoided, may result in property damage.

Important Indicates an item of the essence of a topic that is indispensable. Note Indicates something of notable worth or consequence.


1-Dec-06 68P80801E35-E -xi


Product Specific Safety Notices

Product Specific Safety Notices 0

The specific procedural safety precautions are stated in the procedures and are also listed here.


-xii 68P80801E35-E 1-Dec-06


General Safety

General Safety 0

Important Remember Safety depends on you!!

General safety precautions must be observed during all phases of operation, service, and repair of the equipment described in this manual. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment.

The following general safety precautions must be observed during all phases of operation, service, and repair of the equipment described in this manual. The safety precautions listed below represent warnings of certain dangers of which we are aware. You should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Read and follow all warning notices and instructions marked on the product or included in this manual before installing, servicing or operating the equipment. Retain these safety instructions for future reference. Also, all applicable safety procedures, such as Occupational, Safety, and Health Administration (OSHA) requirements, National Electrical Code (NEC) requirements, local code requirements, safe working practices, and good judgement must be used by personnel.

Refer to appropriate section of the product service manual for additional pertinent safety information.

Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modifications of equipment.

Identify maintenance actions that require two people to perform the repair. Two people are required when: A repair has the risk of injury that would require on person to perform first

aid or call for emergency support. An example would be work around high voltage sources. A second person may be required to remove power and call for emergency aid if an accident occurs to the first person.

Use the National Institute of Occupational Safety and Health (NIOSH) listing equation to determine whether a one or two person lift is required when a system component must be removed and replaced in its rack.

If troubleshooting the equipment while power is applied, be aware of the live circuits.

DO NOT operate the transmitter of any radio unless all RF connectors are secure and all connectors are properly terminated.


1-Dec-06 68P80801E35-E -xiii


General Safety

All equipment must be properly grounded in accordance with Motorola Standards and Guidelines for Communication Sites “R56” (6881089E50) and specified installation instructions for safe operation. Slots and openings in the cabinet are provided for ventilation. To ensure reliable operation of the product and protect it from overheating, these slots and openings must not be blocked or covered.

Only a qualified technician familiar with similar electronic equipment should service equipment.

Some equipment components can become extremely hot during operation. Turn off all power to the equipment and wait until sufficiently cool before touching.

Human Exposure Compliance

This equipment is designed to generate and radiate radio frequency (RF) energy by means of an external antenna. When terminated into a non-radiating RF load, the base station equipment is certified to comply with Federal Communications Commission (FCC) regulations pertaining to human exposure to RF radiation in accordance with the FCC Rules Part 1 section 1.1310 as published in title 47 code of federal regulations and procedures established in TIA/EIA TSB92, Report on EME Evaluation for RF Cabinet Emissions Under FCC MPE Guidelines, Compliance to FCC regulations of the final installation should be assessed and take into account site specific characteristics such as type and location of antennas, as well as site accessi-bility of occupational personnel (controlled environment) and the general public (uncontrolled environment). This equipment should only be installed and maintained by trained technicians. Licensees of the FCC using this equipment are responsible for insuring that its installation and operation comply with FCC regulations Part 1 section 1.1310 as published in title 47 code of federal regulations.

Whether a given installation meets FCC limits for human exposure to radio frequency radiation may depend not only on this equipment but also on whether the “environments” being assessed are being affected by radio frequency fields from other equipment, the effects of which may add to the level of exposure. Accordingly, the overall exposure may be affected by radio frequency generating facilities that exist at the time the licensee’s equipment is being installed or even by equipment installed later. Therefore, the effects of any such facilities must be considered in site selection and in determining whether a particular installation meets the FCC requirements.

FCC OET Bulletin 65 provides materials to assist in making determinations if a given facility is compliant with the human exposure to RF radiation limits. Determining the compliance of transmitter sites of various complexities may be accomplished by means of computational methods. For more complex sites direct measurement of power density may be more expedient. Additional


-xiv 68P80801E35-E 1-Dec-06


General Safety

information on the topic of electromagnetic exposure is contained in the Motorola Standards and Guidelines for Communications Sites publication. Persons responsible for installation of this equipment are urged to consult the listed reference material to assist in determining whether a given installation complies with the applicable limits.

In general the following guidelines should be observed when working in or around radio transmitter sites: All personnel should have electromagnetic energy awareness training. All personnel entering the site must be authorized. Obey all posted signs. Assume all antennas are active. Before working on antennas, notify owners and disable appropriate

transmitters. Maintain minimum 3 feet clearance from all antennas. Do not stop in front of antennas. Use personal RF monitors while working near antennas. Never operate transmitters without shields during normal operation. Do not operate base station antennas in equipment rooms.

For installations outside of the U.S., consult with the applicable governing body and standards for RF energy human exposure requirements and take necessary steps for compliance with local regulations.

References

TIA/EIA TSB92 “Report on EME Evaluation for RF Cabinet Emissions Under FCC MPE Guidelines”, Global Engineering Documents: http://globl.ihs.com/

FCC OET Bulletin 65 “Evaluating Compliance with FCC Guidelines for Human Exposure to Radio Frequency Electromagnetic Fields”; http://www.fcc.gov/oet/rfsaftey/

Motorola Standards and Guidelines for Communications Sites, Motorola manual 68P81089E50

IEEE Recommended Practice for the Measure of Potentially Hazardous Electromagnetic Fields-- RF and Microwave, IEEE Std. C95.3-1991, Publication Sales, 445 Hoes Lane, P.O. Box 1331, Piscattaway, NJ 08855-1331

IEEE Standard for Safety Levels with Respect to Human Exposure to Radio Frequency Electromagnetic Fields, 3 kHz to 300 Iscattaway, NY 08855-1331GHz, IEEE C95.1-1991, Publication Sales, 445 Hoes Lane, P.O. Box 1331


1-Dec-06 68P80801E35-E -xv


General Safety

Keep Away From Live Circuits

! DANGER

HAZARDOUS VOLTAGE, CURRENT, AND ENERGY LEVELS ARE PRESENT IN THIS PRODUCT. POWER SWITCH TERMINALS CAN HAVE HAZARDOUS VOLTAGES PRESENT EVEN WHEN THE POWER SWITCH IS OFF. DO NOT OPERATE THE SYSTEM WITH THE COVER REMOVED. ALWAYS REPLACE THE COVER BEFORE TURNING ON THE SYSTEM.

Operating personnel must: Not remove equipment covers. Only Factory Authorized Service Personnel

or other qualified maintenance personnel may remove equipment covers for internal subassembly, or component replacement, or any internal adjustment.

Not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed.

Always disconnect power and discharge circuits before touching them.

Ground the Equipment

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical earth ground. The power cable must be either plugged into an approved three-contact electrical outlet or used with a three-contact to two-contact adapter. The three-contact to two-contact adapter must have the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable must meet International Electrotechnical Commission (IEC) safety standards.

Electro-Static Discharge

Motorola strongly recommends that you use an anti-static wrist strap and a conductive foam pad when installing or upgrading the system. Electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to Electro-Static Discharge (ESD). After removing the component from the system or its protective wrapper, place the component flat on a grounded, static-free surface, and in the case of a board, component-side up. Do not slide the component over any surface.

If an ESD station is not available, always wear an anti-static wrist strap that is attached to an unpainted metal part of the system chassis. This will greatly reduce the potential for ESD damage.


-xvi 68P80801E35-E 1-Dec-06


General Safety

Do Not Operate In An Explosive Atmosphere

Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a definite safety hazard.

Do Not Service Or Adjust Alone

Do not attempt internal service or adjustment, unless another person, capable of rendering first aid and resuscitation, is present.

Use Caution When Exposing Or Handling a Cathode-Ray Tube

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. The CRT should be handled only by qualified maintenance personnel, using approved safety mask and gloves.

Do Not Substitute Parts Or Modify Equipment

Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification of equipment. Contact Motorola Warranty and Repair for service and repair to ensure that safety features are maintained.


1-Dec-06 68P80801E35-E -xvii


Revision History

Revision History 0

Date Issue Description of Changes

1-Dec-06 -EUpdated with QUAD+2 information.Updated with DMS cabinet configuration.


-xviii 68P80801E35-E 1-Dec-06

Chapter 1

Base Radio

In This Chapter Topic See Page

Overview ...................................................................................... 1-2

Legacy Single Carrier 800 MHz Base Radio Overview ................ 1-3

Generation 2 Single Channel 800 MHz Base Radio Overview .... 1-8



QUAD+2 Base Radio Overview ................................................. 1-25


1-Dec-06 68P80801E35-E 1-1

Base Radio Volume 2

Overview

Overview 1

This chapter provides an overview of the 800 MHz Legacy, 800 MHz Gener-ation 2 Single Channel, 800 MHz and 900 MHz QUAD Channel, and 800/900 MHz QUAD+2 Base Radios (BRs) along with technical information.

FRU Number to Kit Number Cross Reference

The Single Carrier Base Radio section covers the 800 MHz Legacy and 800 MHz Generation 2 versions of the Base Radio (BR). Information is presented generally for all models. Information that is model specific noted in the text.

For Generation 2 BR, both the 800 MHz Exciter and the 800 MHz Low Noise Exciter modules are supported subject to Table 1-5.

For QUAD Channel 800 MHz BR use, all Single Carrier BR modules have undergone redesign. Therefore, Single Carrier BR modules are incompatible with the QUAD Channel 800 MHz BR. QUAD Channel 800 MHz BR modules are incompatible with the Single Carrier BR. Note Do not attempt to insert QUAD Channel 800 MHz BR modules into

a Single Carrier BR or Single Carrier BR modules into a QUAD Channel 800 MHz BR.

Note For QUAD Channel 900 MHz BR use, all Single Carrier BR modules are incompatible with the 900 MHz QUAD Channel BR. 900 MHz QUAD Channel BR modules are incompatible with the Single Carrier BR.

Note Do not attempt to insert QUAD Channel 900 MHz BR modules into a Single Carrier BR or Single Carrier BR modules into a QUAD Channel 900 MHz BR.

Table 1-1 FRU Number to Kit Number Cross Reference

DescriptionFRU

NumberKit

Number

Single Channel 800 MHz BRC TLN3334 CLN1469

Single Channel BRC (MCI) TLN3425 CLN1472

Enhanced Base Radio Controller DLN6446 CLN1653

900 MHz QUAD Channel EX/CNTL DLN1203 CLF6242

800 MHz QUAD Channel EX/CNTL CLN1497 CLF1560

800/900 MHz QUAD+2 Channel XCVR DLN6654 PCUF1001


1-2 68P80801E35-E 1-Dec-06

Volume 2 Base Radio

Legacy Single Carrier 800 MHz Base Radio Overview

Legacy Single Carrier 800 MHz Base Radio Overview 1

The BR provides reliable digital RF communications capabilities in a compact software-controlled design. Increased channel capacity is provided through voice compression techniques and Time Division Multiplexing (TDM).

The BR contains the five FRUs listed below: Base Radio Controller (BRC) Exciter Power Amplifier Power Supply (DC) Receiver

The modular design of the BR also offers increased shielding and provides easy handling. All FRUs connect to the backplane through blindmate connectors. Figure 1-1 shows the front view of the BR.

Figure 1-1 Legacy Base Radio (Typical)


1-Dec-06 68P80801E35-E 1-3

Base Radio Volume 2


Legacy Single Carrier Base Radio Controls and Indicators

The Power Supply and BRC contain controls and indicators that provide a means for monitoring various status and operating conditions of the BR, and also aid in fault isolation. The controls and indicators for both modules are discussed in the Power Supply and BRC sections of this chapter.

The Power Supply contains two front panel indicators; the BRC contains eight front panel indicators. The Power Supply contains a power switch used to apply power to the BR. The BRC contains a RESET switch used to reset the BR.

Legacy Single Carrier Base Radio Performance Specifications

Legacy Single Channel BR General Specifications

General specifications for the BR are listed in Table 1-2.

Table 1-2 BR General Specifications

Specification Value or Range

Dimensions:HeightWidthDepth

5 EIA Rack Units (RU)19" (482.6 mm)16.75" (425 mm)

Operating Temperature 32° to 104° F (0° to 40° C)

Storage Temperature -22° to 140° F (-30° to 60° C)

Rx Frequency Range:800 MHz iDEN 806 - 821 MHz

Tx Frequency Range:800 MHz iDEN 851 - 866 MHz

Tx – Rx Spacing:800 MHz iDEN 45 MHz

Channel Spacing 25 kHz

Frequency Generation Synthesized

Digital Modulation M-16QAM

Power Supply Inputs:VDC -48 VDC (-41 - 60 VDC)

Diversity Branches Up to 3


1-4 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


Legacy Single Channel BR Transmit Specifications

The BR transmit specifications are listed in Table 1-3.

Legacy Single Channel BR Receive Specifications

The receive specifications are listed in Table 1-4.

Table 1-3 Transmit Specifications


Average Power Output:(800 MHz) 40 W PA (800 MHz) 70 W PA

5-40 W5 - 70 W

Transmit Bit Error Rate (BER) 0.01%

Occupied Bandwidth 18.5 kHz

Frequency Stability * 1.5 ppm

RF Input Impedance 50 Ω (nom.)

FCC Designation (FCC Rule Part 90):(800 MHz) 40 W PA(800 MHz) 70 W PA

ABZ89FC5772ABZ89FC5763

Note * Stability without site reference connected to station.

Table 1-4 Receive Specifications


Static Sensitivity †:800 MHz BR -108 dBm (BER = 8%)

BER Floor (BER = 0.01%) ≥ -80 dBm

IF Frequencies1st IF (All bands):2nd IF:800 MHz

73.35 MHz (1st IF)

450 kHz (2nd IF)



FCC Designation (FCC Rule Part 15):800 MHz BR ABZ89FR5762

Note † Measurement referenced from single receiver input port of BR.Note * Stability without site reference connected to station.


1-Dec-06 68P80801E35-E 1-5

Base Radio Volume 2


Note FCC Compliance Notice: The Base Radio (BR) is FCC Compliant only when used in conjunction with Motorola supplied RF Distribution Systems. Motorola does not recommend that this BR be used without a Motorola approved RF Distribution System. It is the customer’s responsibility to file for FCC approval if the BR is used with a non-Motorola supplied RF Distribution System.

Legacy Single Channel BR Theory of Operation

The BR operates in conjunction with other site controllers and equipment that are properly terminated. The following description assumes such a configu-ration. Figures 1-8 show an overall block diagram of the BR.

Power is applied to the DC Power inputs located on the BR backplane. The DC Power input is connected if -48 VDC or batteries are used in the site.

Power is applied to the BR by setting the Power Supply power switch to the “ON” position. Upon power-up, the BR performs self-diagnostic tests to ensure the integrity of the unit. These tests are primarily confined to the BRC and include memory and Ethernet verification routines.

After the self-diagnostic tests are complete, the BR reports any alarm condi-tions present on any of its modules to the site controller via Ethernet. Alarm conditions may also be verified locally using service computer and the STATUS port located on the front of the BRC.Note Legacy Single Channel Base Radios configured with 3X Receiver

modules and Exciter modules (Version R.01.04.xx or higher) can be upgraded to Generation 2 2 Base Radios by removing the BRC module and replacing it with the EBRC (Enhanced Base Radio Controller) module.

The software resident in EPROM on the BRC registers the BR with the site controller via Ethernet. Once registered, the BR software is downloaded via Ethernet and is executed from RAM. Operating parameters for the BR are included in this download. This software allows the BR to perform call processing functions.

The BR operates in a TDMA (Time Division Multiple Access) mode. This mode, combined with voice compression techniques, provides an increased channel capacity ratio of as much as 6 to 1. Both the receive and transmit signals of the BR are divided into 6 individual time slots. Each receive slot has a corresponding transmit slot; this pair of slots comprises a logical RF channel.

The BR uses diversity reception for increased coverage area and improved quality. The Receiver module within the BR contains up to three receivers. Two Receivers are used with two-branch diversity sites, and three Receivers are used with three-branch diversity sites.


1-6 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


All Receivers within a given BR are programmed to the same receive frequency. The signals from each receiver are fed to the BRC where a diversity combining algorithm is performed on the signals. The resultant signal is processed for error correction and then sent to the site controller via Ethernet with the appropriate control information regarding its destination.

The transmit section of the BR is comprised of two separate FRUs, the Exciter and Power Amplifier (PA). Several PA FRUs are available, covering different applications and power levels; these are individually discussed as applicable in later subsections.

The Exciter processes the information to transmit from the BRC in the proper modulation format. This low level signal is sent to the PA where it is amplified to the desired output power level. The PA is a continuous keyed linear amplifier. A power control routine monitors the output power of the BR and adjusts it as necessary to maintain the proper output level.


1-Dec-06 68P80801E35-E 1-7

Base Radio Volume 2

Generation 2 Single Channel 800 MHz Base Radio Overview

Generation 2 Single Channel 800 MHz Base Radio Overview 1

The BR provides reliable digital RF communication capabilities in a compact software-controlled design. Increased channel capacity is provided through voice compression techniques and Time Division Multiplexing (TDM).

The BR contains the five FRUs listed below: Enhanced Base Radio Controller (EBRC) Exciter or Low Noise Exciter Power Amplifier Power Supply (DC) Receiver

The modular design of the BR also offers increased shielding and provides easy handling. All FRUs connect to the backplane through blindmate connectors. Figure 1-2 shows the front view of the BR.

Figure 1-2 Generation 2 Base Radio (Typical)


1-8 68P80801E35-E 1-Dec-06

Volume 2 Base Radio

Generation 2 Single Channel 800 MHz Base Radio

Generation 2 Single Channel Radio Controls and Indicators

The Power Supply and EBRC contain controls and indicators that provide a means for monitoring various status and operating conditions of the BR, and also aid in fault isolation. The controls and indicators for both modules are discussed in the Power Supply and EBRC sections of this chapter.

The Power Supply contains two front panel indicators; the EBRC contains eight front panel indicators. The Power Supply contains a power switch used to apply power to the BR. The EBRC contains a RESET switch used to reset the BR.

Generation 2/EBRC Compatibility

The Enhanced Base Radio Controller (EBRC) serves as the main controller for the Base Radio. The EBRC provides signal processing and operational control for other Base Radio modules. Figure 1-2 shows a top view of the EBRC module with the cover removed. The EBRC module consists of two printed circuit boards (EBRC board and LED display board), a slide-in housing, and associated hardware. The EBRC is only compatible with System Software Release SR 9.15 or

later. Any system running a pre-SR 9.15 System Release must be updated to at least SR 9.15 prior to installation.

The EBRC module is compatible with Legacy Base Radios that support multiple receiver module assemblies.

The Generation 2 Base Radio is compatible with all versions of power supplies.

The Generation 2 Base Radio is compatible with all 800 MHz 70W and 40W Power Amplifiers.

The EBRC module is only compatible with Legacy Exciter (containing revision number R1.04.xx and higher) or the Low Noise Exciter.

Table 1-5 EBRC Compatibility

Module Software Revision System Release

Exciter R01.00.xx- R01.03.xx SR10.0 or Greater

Exciter R01.04.xx and higher SR9.15 or Greater

Single Receiver R01.00.xx - R01.02.xx SR10.0 or Greater

Single Receiver R01.03.xx and higher SR9.15 or Greater

3X Receiver all versions SR9.15 or Greater

40W Power Amplifier all versions SR9.15 or Greater

70W Power Amplifier all versions SR9.15 or Greater


1-Dec-06 68P80801E35-E 1-9

Base Radio Volume 2


Determining FRU and Kit Revisions

For Generation 2 BR/EBRC

These commands will return all available FRU and Kit Revision numbers. Use these to determine installation requirements:

1. Connect one end of the RS-232 cable to the service computer.

2. Connect the other end of the RS-232 cable to the Service Access port, located on the front panel of the EBRC module.

3. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the Control Module front panel. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the password motorola, log in to the BR.

4. Collect revision numbers from the station by typing the following command:

5. If all modules return revision numbers of the format “Rxx.xx.xx”, then all revision numbers are present. In that case, verification requires no further action. If revision numbers return as blank, or not in the format “Rxx.xx.xx”, contact your local Motorola representative or Technical Support.

For Legacy Single Channel BR/BRC


2. Connect the other end of the RS-232 cable to the STATUS port, located on the front panel of the BRC.

3. Using the field password, login to the BR.

f ie ld> login -ufield

password: motorola

f ie ld>

f ield> fv -oplatform

f ie ld>


1-10 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


4. Collect revision numbers from the station by typing the following commands:

5. If all modules return revision numbers of the format “Rxx.xx.xx”, then all revision numbers are present and no further action is required. Log out and repeat steps 1. through 4. for each additional BR.If revision numbers were returned as blank or not in the format “Rxx.xx.xx”, contact your local Motorola representative or Technical Support.

Generation 2 Single Channel BR General Specifications

General specifications for the Generation 2 BR are listed in Table 1-6.

BRC>dekeyBRC>test_modeBRC>get brc_rev_noBRC>get rx1_rev_noBRC>get rx2_rev_noBRC>get rx3_rev_no (if BR is 3 branch)BRC>get pa_rev_noBRC>get ex_rev_no

BRC>

Table 1-6 Generation 2 BR General Specifications


Dimensions:HeightWidthDepth

5 EIA Rack Units (RU)19" (482.6 mm)16.75" (425 mm)




Tx Frequency Range:800 MHz iDEN 851 - 870MHz


Channel Spacing 25 kHz



1-Dec-06 68P80801E35-E 1-11

Base Radio Volume 2


Gen 2 Single Channel BR Transmit Specifications

The Generation 2 BR transmit specifications are listed in Table 1-7.

Digital Modulation M-16QAM

Power Supply Inputs:VDC -48 VDC (-41 - 60 VDC)


Table 1-7 Transmit Specifications


Average Power Output:(800 MHz) 40 W PA (800 MHz) 70 W PA

5 - 40 W5- 70 W





FCC Designation (FCC Rule Part 90):(800 MHz Legacy) 40 W PA(800 MHz Legacy) 70 W PA(800 MHz Low Noise Exciter) 40 W PA(800 MHz Low Noise Exciter) 70 W PA

ABZ89FC5772ABZ89FC5763ABZ89FC5772-AABZ89FC5763-A

Note * Stability without site reference connected to station.

Table 1-6 Generation 2 BR General Specifications



1-12 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


Gen 2 Single Channel BR Receive Specifications

The receive specifications are listed in Table 1-8.

Note FCC Compliance Notice: The Base Radio (BR) is FCC Compliant only when used in conjunction with Motorola supplied RF Distribution Systems. Motorola does not recommend that this BR be used without a Motorola approved RF Distribution System. It is the customer’s responsibility to file for FCC approval if the BR is used with a non-Motorola supplied RF Distribution System.

Generation2 Single Channel BR Theory of Operation

The BR operates in conjunction with other site controllers and equipment that are properly terminated. The following description assumes such a configu-ration. Figures 1-9 shows an overall block diagram of the BR.

Power is applied to the DC Power input located on the BR backplane. The DC Power input is connected if -48 VDC or batteries are used in the site.

Power is applied to the BR by setting the Power Supply power switch to the ON position. Upon power-up, the BR performs self-diagnostic tests to ensure the integrity of the unit. These tests are primarily confined to the EBRC and include memory and Ethernet verification routines.

Table 1-8 Receive Specifications




IF Frequencies1st IF (All bands):2nd IF:800MHz

73.35 MHz (1st IF)

450 kHz (2nd IF)




Note † Measurement referenced from single receiver input port of BR.Note * Stability without site reference connected to station.


1-Dec-06 68P80801E35-E 1-13

Base Radio Volume 2


After the self-diagnostic tests are complete, the BR reports any alarm condi-tions present on any of its modules to the site controller via Ethernet. Alarm conditions may also be verified locally using service computer and the STATUS port located on the front of the EBRC.

The software resident in Flash Memory on the EBRC registers the BR with the site controller via Ethernet. Once registered, the BR software is downloaded via resident FLASH- or Ethernet and is executed from RAM. Operating parameters for the BR are included in this download. This software allows the BR to perform call processing functions.

The BR operates in a TDMA (Time Division Multiple Access) mode. This mode, combined with voice compression techniques, provides an increased channel capacity ratio of as much as 6 to 1. Both the receive and transmit signals of the BR are divided into 6 individual time slots. Each receive slot has a corresponding transmit slot; this pair of slots comprises a logical RF channel.

The BR uses diversity reception for increased coverage area and improved quality. The Receiver module within the BR contains up to three receivers. Two Receivers are used with two-branch diversity sites, and three Receivers are used with three-branch diversity sites.

All Receivers within a given BR are programmed to the same receive frequency. The signals from each receiver are fed to the EBRC where a diversity combining algorithm is performed on the signals. The resultant signal is processed for error correction and then sent to the site controller via Ethernet with the appropriate control information regarding its destination.

The transmit section of the BR is comprised of two separate FRUs, the Exciter and Power Amplifier (PA). Several PA FRUs are available, covering different applications and power levels; these are individually discussed as applicable in later subsections.

The Exciter processes the information to transmit from the EBRC in the proper modulation format. This low level signal is sent to the PA where it is amplified to the desired output power level. The PA is a continuous keyed linear amplifier. A power control routine monitors the output power of the BR and adjusts it as necessary to maintain the proper output level.


1-14 68P80801E35-E 1-Dec-06

Volume 2 Base Radio

QUAD Channel 900 MHz Base Radio Overview

QUAD Channel 900 MHz Base Radio Overview 1

The QUAD Channel 900 MHz BR provides reliable, digital BR capabilities in a compact, software-controlled design. Voice compression techniques, time division multiplexing (TDM) and multi-carrier operation provide increased channel capacity.

The QUAD Channel 900 MHz BR contains the four FRUs listed below: QUAD Channel 900 MHz EX /Cntl QUAD Channel 900 MHz Power Amplifier QUAD Channel 800 MHz and 900 MHz Power Supply (DC) QUAD Channel 900 MHz Receiver (qty. 4)

The modular design of the QUAD Channel 900 MHz BR also offers increased shielding and provides easy handling. All FRUs connect to the backplane through blindmate connectors. Note Both the 800 MHz QUAD and 900 MHz QUAD Base Radios use the

same backplane and cardcage but call out different FCC ID numbers.

Figure 1-3 shows the front view of the BR.

Figure 1-3 QUAD Channel 900 MHz Base Radio (Typical)

!"

!

RX4

RX3

RX2

RX1


1-Dec-06 68P80801E35-E 1-15

Base Radio Volume 2


QUAD Channel 900 MHz Base Radio Controls and Indicators

Power Supply and EX / CNTL controls and indicators monitor BR status and operating conditions, and also aid in fault isolation. The Power Supply and EX / CNTL sections of this chapter discuss controls and indicators for both modules.

The Power Supply has two front panel indicators. The EX / CNTL has twelve front panel indicators. The Power Supply power switch applies power to the BR. The EX / CNTL RESET switch resets the BR.

QUAD Channel 900 MHz Base Radio Performance Specifications

QUAD Channel 900 MHz Base Radio General Specifications

Table 1-9 lists general specifications for the BR.

Table 1-9 QUAD Channel 900 MHz BR General Specifications


Dimensions:HeightWidthDepthWeight

5 EIA Rack Units (RU)19" (482.6 mm)16.75" (425 mm)85 lbs. (38.6 kg)






Carrier Spacing 25 kHz

Carrier Capacity* 1, 2, 3 or 4


Digital Modulation QPSK, M-16QAM, and M-64QAM

Power Supply Inputs:VDC -48 VDC (-41 to -60 VDC)


Note * Multi-carrier operation must utilize adjacent, contiguous RF carriers.


1-16 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


QUAD Channel 900 MHz Base Radio Transmit Specifications

Table 1-10 lists the BR transmit specifications.

QUAD Channel 900 MHz Base Radio Receive Specifications

Table 1-11 lists the receive specifications.

Table 1-10 QUAD Channel 900 MHz BR Transmit Specifications


Low average output power per

carrier

High average output power per

carrierAverage Power Output:

(900 MHZ) Single Carrier 5.0W 52.0W

(900 MHz) Dual Carrier 2.5W 26.0W

(900 MHz) Triple Carrier 1.7W 16.1W

(900 MHz) QUAD Carrier 1.3W 10.5W





FCC Designation (FCC Rule Part 90):900 MHz QUAD BR ABZ89FC5798

Note * Transmit frequency stability locks to an external site reference, which controls ultimate frequency stability to a level of 50 ppb.

Table 1-11 QUAD Channel 900 MHz Receive Specifications




IF Frequencies1st IF (All bands):2nd IF:

73.35 MHz (1st IF)450 kHz (2nd IF)



1-Dec-06 68P80801E35-E 1-17

Base Radio Volume 2


Note FCC Compliance Notice: The QUAD Channel 900 MHz Base Radio (BR) is FCC Compliant only when used with Motorola-supplied RF Distribution Systems. Motorola does not recommend using this BR without a Motorola- approved RF Distribution System. If customer uses the BR with a non-Motorola supplied RF Distribution System, the customer is responsible for filing for FCC approval.

QUAD Channel 900 MHz Base Radio Theory of Operation

The QUAD Channel 900 MHz BR operates with other site controllers and equipment and must be properly terminated. The following description assumes such a configuration. Figure 1-10 show an overall block diagram of the QUAD Channel 900 MHz BR.

Power is applied to the DC Power inputs located on the QUAD Channel 900 MHz BR backplane. The DC Power input is connected if -48 VDC or batteries are used in the site.

Power is applied to the BR by setting the Power Supply power switch to the ON position. Upon power-up, the QUAD Channel 900 MHz BR performs self-diagnostic tests to ensure the integrity of the unit. These tests, which include memory and Ethernet verification routines, primarily examine the EX / CNTL.

After completing self-diagnostic tests, the QUAD Channel 900 MHz BR reports alarm conditions on any of its modules to the site controller via Ethernet. Alarm conditions may also be verified locally. Local verification involves using the service computer and the STATUS port located on the front of the QUAD Channel 900 MHz EX / CNTL.

The software resident in FLASH on the EX / CNTL registers the BR with the site controller via Ethernet. After BR registration on initial power-up, the BR software downloads via resident FLASH or Ethernet and executes from RAM. The download includes operating parameters for the QUAD Channel 900 MHz BR. These parameters allow the QUAD Channel 900 MHz BR to perform call processing functions.



Note † Measurement referenced from single receiver input port of BR.Note * Stability without site reference connected to station. Receive frequency stability locks to an external site reference, which controls ultimate frequency stability to a level of 50 ppb.




1-18 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


After software downloads to the BR via Ethernet, FLASH memory stores the software object. Upon future power-ups, the software object in FLASH loads into RAM for execution.

The BR operates in a TDMA (Time Division Multiple Access) mode. This mode, combined with voice compression techniques, increases channel capacity by a ratio of as much as six to one. TDMA divides both the receive and transmit signals of the BR into six individual time slots. Each receive slot has a corresponding transmit slot. This pair of slots comprises a logical RF channel.

The BR uses diversity reception for increased coverage area and improved quality. The Receiver modules within the QUAD Channel 900 MHz BR contain three receiver paths. Two-branch diversity sites use two Receiver paths, and three-branch diversity sites use three Receiver paths.

All Receiver paths within a given Receiver module are programmed to the same receive frequency. Signals from each receiver arrive at the EX / CNTL module. This module performs a diversity combining algorithm on the signals. The resultant signal undergoes an error-correction process. Then, via Ethernet, the site controller acquires the signal, along with control infor-mation about signal destination.

Two separate FRUs comprise the transmit section of the QUAD Channel 900 MHz BR. These are the Exciter portion of the EX / CNTL and the Power Amplifier (PA). The Exciter processes commands from the CNTL, assuring transmission in the proper modulation format. Then the low-level signal enters the PA. The PA amplifies this signal to the desired output power level. The PA is a continuously keyed linear amplifier. A power control routine monitors the output power of the BR. The routine adjusts the power as necessary to maintain the proper output level.


1-Dec-06 68P80801E35-E 1-19

Base Radio Volume 2


QUAD Channel 800 MHz Base Radio Overview 1

The QUAD Channel 800 MHz BR provides reliable, digital BR capabilities in a compact, software-controlled design. Voice compression techniques, time division multiplexing (TDM) and multi-carrier operation provide increased channel capacity.

The QUAD Channel 800 MHz BR contains the four FRUs listed below: QUAD Channel 800 MHz EX / Cntl QUAD Channel 800 MHz Power Amplifier QUAD Channel 800 MHz/900 MHz Power Supply (DC) QUAD Channel 800 MHz Receiver (qty. 4)

The modular design of the QUAD Channel 800 MHz BR also offers increased shielding and provides easy handling. All FRUs connect to the backplane through blindmate connectors.Note Both the 800 MHz QUAD and 900 MHz QUAD Base Radios use the

same backplane and cardcage but call out different FCC ID numbers.

Figure 1-4 shows the front view of the BR.

Figure 1-4 QUAD Channel 800 MHz Base Radio (Typical)

#

$

RX4

RX3

RX2

RX1


1-20 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


QUAD Channel 800 MHz Base Radio Controls and Indicators

Power Supply and EX / CNTL controls and indicators monitor BR status and operating conditions, and also aid in fault isolation. The Power Supply and EX / CNTL sections of this chapter discuss controls and indicators for both modules.

The Power Supply has two front panel indicators. The EX / CNTL has twelve front panel indicators. The Power Supply power switch applies power to the BR. The EX / CNTL RESET switch resets the BR.

QUAD Channel 800 MHz Base Radio Performance Specifications

QUAD Channel 800 MHz Base Radio General Specifications


Table 1-12 QUAD Channel 800 MHz BR General Specifications



5 EIA Rack Units (RU)19" (482.6 mm)16.75" (425 mm)91 lbs. (40 kg)







Carrier Capacity * 1, 2, 3 or 4



Power Supply Inputs:VDC -48 VDC (-41 to - 60 VDC)




1-Dec-06 68P80801E35-E 1-21

Base Radio Volume 2


QUAD Channel 800 MHz Base Radio Transmit Specifications


QUAD Channel 800 MHz Base Radio Receive Specifications


Table 1-13 QUAD Channel 800 MHz Transmit Specifications


Low average output power per carrier

High average output power per carrierAverage Power Output:

(800 MHZ) Single Carrier 5.0W 52.0W

(800 MHz) Dual Carrier 2.5W 26.0W

(800 MHz) Triple Carrier 1.7W 16.1W

(800 MHz) QUAD Carrier 1.3W 10.5W





FCC Designation (FCC Rule Part 90):800 MHz) QUAD BR ABZ89FC5794






IF Frequencies1st IF (All bands):2nd IF:

73.35 MHz (1st IF)450 kHz (2nd IF)



1-22 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


Note FCC Compliance Notice: The QUAD Channel 800 MHz Base Radio (BR) is FCC Compliant only when used with Motorola-supplied RF Distribution Systems. Motorola does not recommend using this BR without a Motorola- approved RF Distribution System. If customer uses the BR with a non-Motorola supplied RF Distribution System, the customer is responsible for filing for FCC approval.

QUAD Channel 800 MHz Base Radio Theory of Operation

The QUAD Channel 800 MHz BR operates together with other site controllers and equipment that are properly terminated. The following description assumes such a configuration. Figure 1-10 show an overall block diagram of the QUAD Channel 800 MHz BR.

Power is applied to the DC Power inputs located on the QUAD Channel 800 MHz BR backplane. The DC Power input is connected if -48 VDC or batteries are used in the site.

Power is applied to the BR by setting the Power Supply power switch to the ON position. Upon power-up, the QUAD Channel 800 MHz BR performs self-diagnostic tests to ensure the integrity of the unit. These tests, which include memory and Ethernet verification routines, primarily examine the EX / CNTL.

After completing self-diagnostic tests, the QUAD Channel 800 MHz BR reports alarm conditions on any of its modules to the site controller via Ethernet. Alarm conditions may also be verified locally. Local verification involves using the service computer and the STATUS port located on the front of the QUAD 800 MHz EX / CNTL.

The software resident in FLASH on the EX / CNTL registers the BR with the site controller via Ethernet. After BR registration on initial power-up, the BR software downloads via Ethernet and executes from RAM. The download includes operating parameters for the QUAD Channel 800 MHz BR. These parameters allow the QUAD Channel 800 MHz BR to perform call processing functions.


FCC Designation (FCC Rule Part 15):800 MHz QUAD BR ABZ89FR5793





1-Dec-06 68P80801E35-E 1-23

Base Radio Volume 2




The BR uses diversity reception for increased coverage area and improved quality. The Receiver modules within the QUAD Channel 800 MHz BR contain three receiver paths. Two-branch diversity sites use two Receiver paths, and three-branch diversity sites use three Receiver paths.

All Receiver paths within a given Receiver module are programmed to the same receive frequency. Signals from each receiver arrive at the EX / CNTL module. This module performs a diversity combining algorithm on the signals. The resultant signal undergoes an error-correction process. Then, via Ethernet, the site controller acquires the signal, along with control infor-mation about signal destination.

Two separate FRUs comprise the transmit section of the QUAD Channel 800 MHz BR. These are the Exciter portion of the EX / CNTL and the Power Amplifier (PA). The Exciter processes commands from the CNTL, assuring transmission in the proper modulation format. Then the low-level signal enters the PA. The PA amplifies this signal to the desired output power level. The PA is a continuously keyed linear amplifier. A power control routine monitors the output power of the BR. The routine adjusts the power as necessary to maintain the proper output level.


1-24 68P80801E35-E 1-Dec-06

Volume 2 Base Radio

QUAD+2 Base Radio Overview

QUAD+2 Base Radio Overview 1

The QUAD+2 BR provides reliable, digital BR capabilities in a compact, software-controlled design. Voice compression techniques, time division multiplexing (TDM) and multi-carrier operation provide increased channel capacity.

The QUAD+2 BR contains the four FRUs listed below: QUAD+2 Transceiver QUAD+2 Power Amplifier QUAD+2 Power Supply QUAD+2 Fan Module

The modular design of the QUAD+2 BR also offers increased shielding and provides easy handling. All FRUs connect to the backplane through blindmate connectors.

Figure 1-5 shows the front view of the BR. Figure 1-6 shows the front view of the BR with the access panel opened. Figure 1-7 shows the front view of the BR with the fan cover removed.

Figure 1-5 QUAD+2 Base Radio (Typical)

"


1-Dec-06 68P80801E35-E 1-25

Base Radio Volume 2


Figure 1-6 QUAD+2 Base Radio (with Access Panel opened)

Figure 1-7 QUAD+2 Base Radio (with Fan Cover removed)

Transceiver LEDs and Service Ports

Power Amplifier LEDs

Power Amplifier

Transceiver (XCVR)


1-26 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


QUAD+2 Base Radio Controls and Indicators

The Power Supply, Transceiver, and Power Amplifier controls and indicators monitor BR status and operating conditions, and also aid in fault isolation. The Power Supply, Transceiver, and Power Amplifier sections of this chapter discuss controls and indicators for both modules.

The Power Supply has three front panel indicators. The Transceiver has nine front panel indicators. The Power Amplifier has three front panel indicators. The Power Supply power switch applies power to the BR. The XCVR RESET switch resets the BR.

QUAD+2 Base Radio Performance Specifications

QUAD+2 Base Radio General Specifications


Table 1-15 QUAD+2 Channel BR General Specifications



5.25" (133 mm)19" (482.6 mm)18" (483 mm)45 lbs. (20 kg)



Rx Frequency Range: 806 - 825 MHz, 896 - 902 MHz

Tx Frequency Range: 851 - 870 MHz, 935 - 941 MHz

Tx – Rx Spacing:800 MHz iDEN900 MHz iDEN

45 MHz39 MHz


Carrier Capacity* 1, 2, 3, 4, 5 or 6



Power Supply Inputs:VDCVAC

-48 VDC (-43 to -60 VDC)90 to 264 VAC, 47-63 Hz




1-Dec-06 68P80801E35-E 1-27

Base Radio Volume 2


QUAD+2 Base Radio Transmit Specifications


Table 1-16 QUAD+2 Channel BR Transmit Specifications


Low average output power per

carrier

High average output power per

carrierAverage Power Output:

(800/900 MHz) Single Carrier 5.0W 52.0W

(800/900 MHz) Dual Carrier 2.5W 26.0W

(800/900 MHz) Triple Carrier 1.7W 16.1W

(800/900 MHz) QUAD Carrier 1.3W 10.5W

(800/900 MHz) Five Carrier 1W 8.7W

(800/900 MHz) Six Carrier 0.8W 7.3W





FCC Designation (FCC Rule Part 90): ABZ89FC5813



1-28 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


QUAD+2 Channel Base Radio Receive Specifications


Table 1-17 QUAD+2 Channel Receive Specifications


Static Sensitivity †:800/900 MHz BR -108 dBm (BER = 8%)


IF Frequencies1st IF

Channel 1 (800 MHz):Channel 1 (900 MHz):Channel 2 (800 MHz):Channel 2 (900 MHz):Channel 3 (800 MHz):Channel 3 (900 MHz):Channel 4 (800 MHz):Channel 4 (900 MHz):Channel 5 (800 MHz):Channel 5 (900 MHz):Channel 6 (800 MHz):Channel 6 (900 MHz):

2nd IFChannel 1 (800 MHz):Channel 1 (900 MHz):Channel 2 (800 MHz):Channel 2 (900 MHz):Channel 3 (800 MHz):Channel 3 (900 MHz):Channel 4 (800 MHz):Channel 4 (900 MHz):Channel 5 (800 MHz):Channel 5 (900 MHz):Channel 6 (800 MHz):Channel 6 (900 MHz):

73.425 MHz73.3 MHz73.4 MHz:73.325 MHz73.375 MHz73.35 MHz73.35 MHz73.375 MHz73.325 MHz73.4 MHz73.3 MHz73.425 MHz

2.4375 MHz2.3125 MHz2.4125 MHz2.3375 MHz2.3875 MHz2.3625 MHz2.3625 MHz2.3875 MHz2.3375 MHz2.4125 MHz2.3125 MHz2.4375 MHz



FCC Designation (FCC Rule Part 15): ABZ89FR5814



1-Dec-06 68P80801E35-E 1-29

Base Radio Volume 2


Note FCC Compliance Notice: The QUAD+2 Base Radio (BR) is FCC Compliant only when used with Motorola-supplied RF Distribution Systems. Motorola does not recommend using this BR without a Motorola- approved RF Distribution System. If customer uses the BR with a non-Motorola supplied RF Distribution System, the customer is responsible for filing for FCC approval.

QUAD+2 Base Radio Theory of Operation

The QUAD+2 Channel BR operates together with other site controllers and equipment that are properly terminated. The following description assumes such a configuration. Figure 1-11 shows an overall block diagram of the QUAD+2 Channel BR.

Power is applied to the DC Power inputs located on the QUAD+2 Channel BR backplane. The DC Power input is connected if -48 VDC or batteries are used in the site.

Power is applied to the BR by setting the Power Supply power switch to the ON position. Upon power-up, the QUAD+2 Channel BR performs self-diagnostic tests to ensure the integrity of the unit. These tests, which include memory and Ethernet verification routines, primarily examine the EX / CNTL.

After completing self-diagnostic tests, the QUAD+2 Channel BR reports alarm conditions on any of its modules to the site controller via Ethernet. Alarm conditions may also be verified locally. Local verification involves using the service computer and the STATUS port located on the front of the QUAD+2 Channel BR.

The software resident in FLASH on the XCVR registers the BR with the site controller via Ethernet. After BR registration on initial power-up, the BR software downloads via Ethernet and executes from RAM. The download includes operating parameters for the QUAD+2 Channel BR. These param-eters allow the QUAD+2 Channel BR to perform call processing functions.



The BR uses diversity reception for increased coverage area and improved quality. The Receiver modules within the QUAD+2 Channel BR contain three receiver paths. Two-branch diversity sites use two Receiver paths, and three-branch diversity sites use three Receiver paths.


1-30 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


All Receiver paths within the Transceiver module are programmed to the same receiver frequency. Signals from each receiver are diversity combined and undergo error-correction. Then, via Ethernet, the site controller acquires the signal, along with control information about signal destination.

Two separate FRUs comprise the transmit section of the QUAD+2 Channel BR. These are the Exciter and Control (XCVR) portion of the Transceiver and the Power Amplifier (PA). The Exciter processes commands from the CNTL, assuring transmission in the proper modulation format. Then the low-level signal enters the PA. The PA amplifies this signal to the desired output power level. The PA is a continuously keyed linear amplifier. A power control routine monitors the output power of the BR. The routine adjusts the power as necessary to maintain the proper output level.


1-Dec-06 68P80801E35-E 1-31

Base Radio Volume 2


N O T E S . . .


1-32 68P80801E35-E 1-Dec-06

Volume 2 Base Radio


1-33

CITER MODULE

POWER SUPPLY MODULE

ADDRESS DECODE,MEMORY, A/D CONVERTER

LINEAR RFAMPLIFIER

EXCITERIC

IF IN IF OUT

TRANLINIC

INPUT FILTERBOARD

CLOCKGENERATORCIRCUITRY

START-UPINVERTERCIRCUITRY

133 KHZ

267 KHZ

+14.2 VINVERTERCIRCUITRY

133 KHZ

DIAGNOSTICSCIRCUITRY

+14.2 VDCTO BACKPLANE

+5 VDCTO BACKPLANE

+28 VDCTO BACKPLANE

EXTERNALDC INPUT41 - 60 VDC

RF OUT

SPI BUS

2.1

MH

Z

FEEDBACK IN

EBTS284053001JNM

MAIN INVERTERCIRCUITRY

+5 VINVERTERCIRCUITRY

970 MHZVCO/SYNTHFREQUENCY

DOUBLER

237 MHZVCO

1-Dec-06 68P80801E35-E

Figure 1-8 800 MHz Legacy Base Radio Functional Block Diagram

POWER AMPLIFIER MODULE

TO/FROMETHERNET

BASE RADIO CONTROLLERMODULE

EX

DC

SE

RIA

LB

US

TO/FROMSTATUS

PORT(RS-232)

TO/FROMRS-232 PORT

(ON BACKPLANE)

16.8 MHZ

5 MHZ

SP

I B

US

5 MHZEXTERNAL

REFERENCE

FINALLINEARAMPS

SPLITTERLINEARDRIVER


FROMRFDS

(RECEIVERANTENNA)

#3

3X RECEIVER MODULE

MIXERDSP BUS

LPF/PRESELECT/

PREAMP/IMAGE FILTER

VCO/SYNTH

ADDRESS DECODE,MEMORY,

A/D CONVERTER

NON-VOLATILEMEMORY(EEPROM,EPROM)

DRAMSRAM

HOSTµP

ETHERNETINTERFACE

HOSTGLUEASIC

TRANSMITDSP

RECEIVEDSP

SC

I

SS

I

PLL/VCO

SPI BUS

2.1 MHZ

COMBINER

SPI BUS

SPI BUS

SPI BUS

SP

I B

USDA

TA/C

LO

CK

DATA/CLOCK

RF IN

RF OUTRF FEEDBACK

DIGITALATTEN.CIRCUIT

AG

C

SPI BUS

RF IN

CUSTOMRECEIVER

IC

TORFDS

(TRANSMITANTENNA)

TISIC

FROMRFDS

(RECEIVERANTENNA)

#2

MIXERDSP BUS

LPF/PRESELECT/

PREAMP/IMAGE FILTER

RF INDIGITALATTEN.CIRCUIT

CUSTOMRECEIVER

IC

FROMRFDS

(RECEIVERANTENNA)

#1

MIXERDSP BUS

LPF/PRESELECT/

PREAMP/IMAGE FILTER


CUSTOMRECEIVER

IC

BANDPASS

FILTER

BANDPASS

FILTER

BANDPASS

FILTER

IFAMP

IFAMP

IFAMP

BANDPASS

FILTER

BANDPASS

FILTER

BANDPASS

FILTER

3-WAYSPLITTER

NOTES:1. 2-Branch systems must have a 50Ω load (P/N 5882106P03) installed on Antenna Port #3.2. Set the RX_FRU_CONFIG parameter as follows:

2-Branch Systems: 123-Branch Systems: 123

Base Radio Volume 2

1-Dec-06

CITER MODULE

POWER SUPPLY MODULE


LINEAR RFAMPLIFIER

EXCITERIC

IF IN IF OUT

TRANLINIC

INPUT FILTERBOARD



133 KHZ

267 KHZ

+14.2 VINVERTERCIRCUITRY

133 KHZ



+5 VDCTO BACKPLANE

+28 VDCTO BACKPLANE


RF OUT

SPI BUS

2.1

MH

Z

FEEDBACK IN

EBTS284053001JNM

MAIN INVERTERCIRCUITRY

+5 VINVERTERCIRCUITRY

970 MHZVCO/SYNTHFREQUENCY

DOUBLER

237 MHZVCO


1-34 68P80801E35-E

Figure 1-9 Generation 2 Single Channel 800 MHz Base Radio Functional Block Diagram


TO/FROMETHERNET

ENHANCEDBASE RADIO CONTROLLERMODULE

EX

DC

SE

RIA

LB

US

TO/FROMSTATUS

PORT(RS-232)

16.8 MHZ

5 MHZ

SP

I B

US

5 MHZEXTERNAL

REFERENCE

FINALLINEARAMPS

SPLITTERLINEARDRIVER


FROMRFDS

(RECEIVERANTENNA)

#3

3X RECEIVER MODULE

MIXERDSP BUS

LPF/PRESELECT/

PREAMP/IMAGE FILTER

VCO/SYNTH

ADDRESS DECODE,MEMORY,

A/D CONVERTER

PLL/VCO

SPI BUS

2.1 MHZ

COMBINER

SPI BUS

SPI BUS

SPI BUS

SP

I B

USDA

TA

/CL

OC

K

DATA/CLOCK

RF IN

RF OUTRF FEEDBACK

DIGITALATTEN.CIRCUIT

AG

C

SPI BUS

RF IN

CUSTOMRECEIVER

IC

TORFDS

(TRANSMITANTENNA)

FROMRFDS

(RECEIVERANTENNA)

#2

MIXERDSP BUS

LPF/PRESELECT/

PREAMP/IMAGE FILTER


CUSTOMRECEIVER

IC

FROMRFDS

(RECEIVERANTENNA)

#1

MIXERDSP BUS

LPF/PRESELECT/

PREAMP/IMAGE FILTER


CUSTOMRECEIVER

IC

BANDPASS

FILTER

BANDPASS

FILTER

BANDPASS

FILTER

IFAMP

IFAMP

IFAMP

BANDPASS

FILTER

BANDPASS

FILTER

BANDPASS

FILTER

3-WAYSPLITTER

NOTES:1. 2-Branch systems must have a 50Ω load (P/N 5882106P03) installed on Antenna Port #3.2. Set the RX_FRU_CONFIG parameter as follows:

2-Branch Systems: 123-Branch Systems: 123

SDRAMIO

LATCHESEEPROMFLASHBUFFERS

HOSTµP

ETHERNETINTERFACE

RECEIVEDSP

TRANSMITDSP

TISIC

1PPS &SLOTTIMING

Volume 2 Base Radio


1-35


ADDRESS DECODE,MEMORY, ADC

LINEARDRIVER

FINALLINEARAMPS

COMBINER

SPLITTER

RF OUT

TO RFDS(TX ANTENNA)

MIXERIF FILTERAMP, AGC

ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER

RX INTERFACE,ADDRESS DECODE.

MEMORY, DIAGNOSTICS

REAMPLIFIERSPLITTER/ BYPASS

VCO SYNTHSPLITTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


MEMORY, DIAGNOSTICS

EAMPLIFIERSPLITTER/ BYPASS

VCO SYNTHSPLITTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


MEMORY, DIAGNOSTICS

EAMPLIFIERSPLITTER/ BYPASS

VCO SYNTHSPLITTER

CEIVER 2

EIVER 3

CEIVER 1

16.8MHz

1-Dec-06 68P80801E35-E

Figure 1-10 800 and 900 MHZ QUAD Channel Base Radio Functional Block Diagram

16.8MHz2.4MHz

48MHz

Host SPI

Host SPI

16.8M

Hz

STATUSPORT

RS-232

5 MHZEXTERNAL

REFERENCE

ETHERNET

1PPS & SLOT TIMING

RX1 DATA

RX2 DATARX3 DATARX4 DATA

Rx1&

2

Rx3&

4Tx_I Tx_Q

EXCITER-BASE RADIO CONTROLLER

HOSTu’P

SDRAM

RECEIVEDSP

ETHERNET

EEPROM

FLASH

PLL/VCOs

TRANSMITDSP

TISIC

TX RECLOCK

BUFFERS

RX SPI

BASE RADIO CONTROLLER

Exciter

IO LATCHES

RECEIVEDSP

INTERFACE

SPI BUS

DAC VCOs/SynthsIQODCTLINEAR RF

AMPLIFIER

RF IN

RF FEEDBACK

DC POWER SUPPLY MODULE

INPUT FILTER



CLOCKGENERATOR

133 KHZ 267 KHZ133 KHZ

14.2 VCONVERTER

3.3 VCONVERTER

+28 VDCTO BACKPLANE



Main Converter

PRF IN

FROM RFDS(BRANCH 2)

PRRF IN

FROM RFDS(BRANCH 3)

PRRF IN

FROM RFDS(BRANCH 1)

RE

RECRECEIVER 4

RE


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


ABACUSRECEIVER

ICLPF, AMP,

FILTER


MEMORY, DIAGNOSTICS

PREAMPLIFIERSPLITTER/ BYPASS

VCO SYNTHSPLITTER

SPI BUS

SPI BUS

SPI BUS

ADDRESS DECODE,MEMORY, ADC

QUA

D RX

IN D

ISTR

IBUT

ION

RECEIVER 4

Base Radio Volume 2

1-Dec-06

!

!

! "

&#'

!

! "

#

#


1-36 68P80801E35-E

Figure 1-11 QUAD+2 Channel Base Radio Functional Block Diagram

!

!

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3 3

Chapter 2

Base Radio Controllers


Overview ...................................................................................... 2-2

800 MHz Legacy Base Radio Controller ...................................... 2-3

Enhanced Base Radio Controller ............................................... 2-15




1-Dec-06 68P80801E35-E 2-1

Base Radio Controllers Volume 2

Overview

Overview 2

This chapter provides information on Base Radio Controllers (BRCs).


Base Radio Controller (BRC) Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU contains the BRC kit and required packaging. Table 2-1 provides a cross reference between BRC FRU numbers and kit numbers.


DescriptionFRU

NumberKit

Number

Single Channel 800 MHz Base Radio Controller TLN3334 CLN1469

Enhanced Base Radio Controller DLN6446 CLN1653

QUAD Channel 900 MHz Exciter/BR Controller DLN1203 CLF1792

QUAD Channel 800 MHz Exciter/BR Controller CLN1497 CLF1560


2-2 68P80801E35-E 1-Dec-06

Volume 2 Base Radio Controllers

800 MHz Legacy Base Radio Controller

800 MHz Legacy Base Radio Controller 2

800 MHz Legacy Base Radio Controller Overview

The Base Radio Controller (BRC) serves as the main controller for the Base Radio. The BRC provides signal processing and operational control for other Base Radio modules. Figure 2-1 shows a top view of the BRC with the cover removed. The BRC module consists of two printed circuit boards (BRC board and LED/display board), a slide-in housing, and associated hardware.

The operating software and codeplug are contained within the BRC memory. The software defines operating parameters for the BR, such as output power and operating frequency.

The BRC interconnects to the Base Radio backplane using one 96-pin DIN connector and one blindmate RF connector. The BRC is secured in the Base Radio chassis using two Torx screws.F

Model CLN1472 contains an additional Digital Signal Processing power for applications requiring a modified error correction routine (available for a specific customers only). Figure 2-2 shows a top view of the BRC (model CLN1472) with the cover removed.

Figure 2-1 Legacy Base Radio Controller, version CLN1469 (with cover removed)


1-Dec-06 68P80801E35-E 2-3



Figure 2-2 Legacy Base Radio Controller, version CLN1472 (with cover removed)

800 MHz Legacy Base Radio Controller Controls and Indicators

The BRC monitors the functions of other Base Radio modules. The LEDs on the front panel indicate the status of the modules monitored by the BRC. All LEDs on the BRC front panel normally flash on/off three times upon initial power-up. A RESET switch is provided to allow a manual reset of the Base Radio. Figure 2-3 shows the front panel of the BRC.

Figure 2-3 Legacy BR Controller (Front View)

1.5GHZ-A859

#!


2-4 68P80801E35-E 1-Dec-06



Indicators

Table 2-2 lists and describes the BRC LEDs.

Table 2-2 Legacy BR Controller Indicators

LED ColorModule

Monitored Condition Indications

BR Green BR

Solid (on) Station is keyed

Flashing (on)

Station is not keyed

Off Station is out of service or power is removed

PS Red Power Supply

Solid (on)FRU failure indication - Power Supply has a major alarm and is out of service

Flashing (on)

Power Supply has a minor alarm and may be operating at reduced performance

Off Power Supply under normal operation (no alarms)

EX Red Exciter

Solid (on)FRU failure indication - Exciter has a major alarm and is out of service

Flashing (on)

Exciter has a minor alarm and may be operating at reduced performance

OffExciter under normal operation (no alarms)

PA RedPower Amplifier

Solid (on)FRU failure indication - PA has a major alarm and is out of service

Flashing (on)

PA has a minor alarm and may be operating at reduced performance

Off PA under normal operation (no alarms)

CTL Red Controller

Solid (on)FRU failure indication - BRC has a major alarm and is out of service

Flashing (on)

BRC has a minor alarm and may be operating at reduced performance

Off BRC under normal operation (no alarms)

R1R2R3

RedReceiver #1, #2, or #3

Solid (on)FRU failure indication - Receiver (#1, #2, or #3) has a major alarm and is out of service

Flashing (on)

Receiver (#1, #2, or #3) has a minor alarm and may be operating at reduced performance

OffReceiver (#1, #2, or #3) under normal operation (no alarms)


1-Dec-06 68P80801E35-E 2-5



Controls

Table 2-3 lists the controls and descriptions.

STATUS Connector

Table 2-4 the pin-outs for the STATUS connector.

Table 2-3 Legacy BR Controller Controls

Control Description

RESET SwitchA push-button switch used to manually reset the BR.

STATUS connectorA 9-pin connector used for connection of a service computer, providing a convenient means for testing and configuring.

Table 2-4 Pin-outs for the STATUS Connector

Pin-out Signal

1 CD

2 TXD

3 RXD

4 not used

5 GND

6 not used

7 CTS

8 RTS

9 not used


2-6 68P80801E35-E 1-Dec-06



800 MHz Legacy Base Radio Controller Theory of Operation

Table 2-5 briefly describes the BRC circuitry. Figures 2-10 through 2-11 are functional block diagrams of the BRC.

Host Microprocessor

The host microprocessor serves as the main controller for the BR. It operates at a clock speed of 16.5 MHz that is supplied from the Host Glue ASIC. The processor controls the operation of the Base Radio as determined by the station software contained in non-volatile memory. The station software is contained in two EPROMs. The station codeplug is stored in EEPROM.

Table 2-5 Legacy BR Controller Circuitry

Circuit Description

Host Microprocessor and Host Glue ASIC

Contains two integrated circuits that comprise the central controller of the BRC and station

Non-Volatile Memory

Consists of: EPROMs containing the station operating softwareone EEPROM containing the station codeplug data

Volatile Memory

Contains DRAM to store station software used to execute commands. Contains SRAM for general data space used by the host microprocessor

Ethernet InterfaceProvides the BRC with a 10Base2 Ethernet communication port to network both control and compressed voice data

RS-232 InterfaceProvides the BRC with two independent RS-232 serial interfaces

Digital Signal Processors and TISIC

Performs high-speed modulation/demodulation of compressed audio and signaling data

Station Reference Circuitry

Generates the 16.8 MHz and 2.1 MHz reference signal used throughout the station

Input Ports Contains two 16-line input buses that receive miscellaneous inputs from the BR

Output PortsContains three 16-line output buses providing a path for sending miscellaneous control signals to various circuits throughout the BR

Remote Station ShutdownProvides software control to cycle power on the BR


1-Dec-06 68P80801E35-E 2-7



Serial Communication Buses

The microprocessor provides a general-purpose SCC2 serial communications bus.

The SCC2 serial communications bus is an asynchronous RS-232 interface. A 9-pin D-type connector on the BRC front panel provides a port for service personnel to connect a service computer. A service computer allows the downloading of application code or diagnostic software. Service personnel can perform programming and maintenance tasks via Man Machine Interface (MMI) commands. The interface between the SCC2 port and the front panel STATUS connector is via EIA-232 Bus Receivers/Drivers.

Address and Data Bus

The microprocessor is equipped with a 23-line address bus used to access the non-volatile memory, DRAM memory, and provide control via memory mapping for other circuitry in the BRC.

A 16-line data bus transfers data to/from the BRC memory, as well as other BRC circuitry. This data bus is buffered for transfers to and from the non-volatile and DRAM memory.

Host Glue ASIC

The Host Microprocessor controls the operations of the Host Glue ASIC which performs the functions described Table 2-6.

Table 2-6 Host Glue ASIC Functions

Function Description

SPI Bus

Serves as a general-purpose serial communications bus providing communications between the Host Microprocessor and other Base Radio modules

DRAM ControllerProvides signals necessary to access and refresh the DRAM memory

System Reset Generates a BRC Reset upon power up


2-8 68P80801E35-E 1-Dec-06



Non-Volatile Memory

The Base Radio software resides in two 512K x 8 EPROMs. These EPROMs are accessed by the Host Microprocessor via the 19 lines of the 23-line host address bus and the 16-line host data bus.

The data determining the station personality resides in an 8K x 8 codeplug EEPROM. The EEPROM is accessed by the microprocessor via 15 lines of the 23-line host address bus and the 16-line data bus.

Stations are manufactured with default data programmed into the codeplug. Field programming information is downloaded from the network/site controllers. This data includes operating frequencies and output power level. Many of the station parameters may be adjusted but will not be stored within the station. Refer to the Software Commands section of this manual for additional information.

Volatile Memory

Each BRC contains 2MB of DRAM. The BRC downloads the station software code into DRAM for the station to use. Data is lost upon loss of power or reset since the DRAM is volatile memory.

The DRAM also provides short-term storage for data generated and required during normal operation. Read and write operations are performed via the Host Address and Data buses in conjunction with column and row select lines that are controlled by the Host Glue ASIC. DRAM memory locations are sequentially refreshed by the address bus and column row signals from the Host Glue ASIC during normal operation.

Host Microprocessor Clock

Buffers the 33 MHz crystal outputs, performs a divide-by-2, and outputs a clock signal for the Host Microprocessor at 16.5 MHz

Address Decoding

Provides decoding of addressing from Host Microprocessor and generates corresponding chip select signals for various BRC devices, such as DRAM, EPROM, I/O Ports, DSPs, and internal Host Glue ASIC registers

Interrupt Controller

Accepts interrupt signals from various BRC circuits (such as the DSPs), prioritizes the interrupts based on hardware-defined priority ranking, and sends interrupt and priority level information to Host Microprocessor (via IPL lines 1-3)

Table 2-6 Host Glue ASIC Functions

Function Description


1-Dec-06 68P80801E35-E 2-9



Two 32K x 8 fast Static RAM (SRAM) ICs are also provided on the BRC. The SRAM is accessed by the Microprocessor via 15 lines of the 23-line Host Address Bus and the 16-line Data Bus.

Ethernet Interface

The Local Area Network (LAN) Controller for the Ethernet Interface is provided by a 32-bit address, 16-bit data LAN coprocessor. The LAN copro-cessor implements the CSMA/CD access method which supports the IEEE 802.3 10Base2 standard. The LAN coprocessor communicates to the Host Microprocessor via DRAM. Of the LAN coprocessor’s 32 address lines, 22 are used for the Ethernet interface.

The LAN coprocessor supports all IEEE 802.3 Medium Access Control, including the following: framing preamble generation stripping source address generation destination address checking

The LAN coprocessor receives commands from the CPU by reading a specified block in memory. Internal FIFOs of the LAN Controller optimize the microprocessor bus performance.

In addition, the on-chip Direct Memory Access (DMA) controller of the LAN coprocessor transfers data blocks (buffers and frames) from Ethernet to DRAM. This automatic transfer of data by the LAN coprocessor relieves the host CPU of byte transfer overhead.

The Ethernet Serial Interface works directly with the LAN coprocessor to perform the following major functions: 10 MHz transmit clock generation (obtained by dividing the 20 MHz signal

provided by on board crystal) Manchester encoding/decoding of frames electrical interface to the Ethernet transceiver

An isolation transformer provides high voltage protection and isolates the Ethernet Serial Interface (ESI) and the transceiver. The pulse transformer has the following characteristics: Minimum inductance of 75 µH 2000 V isolation between primary and secondary windings 1:1 Pulse Transformer


2-10 68P80801E35-E 1-Dec-06



The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver/receiver for the Ethernet. CTI provides a 10Base2 connection via a coaxial connector on the board. This device minimizes the number of external components necessary for Ethernet operations.

A DC/DC converter provides a constant voltage of -9 VDC for the CTI from a 5 VDC source.

The CTI performs the following functions: Receives and transmits data to the Ethernet coaxial connection Reports any collision detected on the coaxial Disables the transmitter when packets are longer than the legal length

(Jabber Timer)

Digital Signal Processors

The Receive Digital Signal Processor (RXDSP), Transmit Digital Signal Processor (TXDSP), and related circuitry process the station transmit and receive compressed audio/data. This circuitry includes the RXDSP and TXDSP, the TDMA Infrastructure Support IC (TISIC), and the TISIC Interface Circuitry. All signals input to or output from the DSP are in digitized format.

The inputs are digitized receive signals from the Receivers. The outputs are digitized voice audio/data (modulation signals) that are sent from the DSP to the Exciter. The DSPs communicate with the Microprocessor via an 8-bit host data bus on the Host Processor side. Communication is interrupt driven for all DSPs.

The RXDSP operates from a 40 MHz clock provided by an on-board crystal. The RXDSP accepts redigitized signal from the receivers. The RXDSP provides address and data buses to receive digitized audio from the TISIC.

The RXDSP also accesses its DSP program and signal processing algorithms contained in three 32K x 8 SRAM ICs. The RXDSP communicates with the host bus via an 8-bit interface.

Additionally, there is a serial data path to the TXDSP via the Synchronous Serial Interface (SSI) port. A serial control path is also provided from the TXDSP via the Serial Communications Interface (SCI) port.

The TXDSP also operates at a clock speed of 40 MHz, provided by a clock oscillator. The TXDSP sends the digitized signal to the TISIC where it is then passed to the Exciter.

The TXDSP contains its own address and data bus to access its DSP program and signal processing algorithms contained in local memory. The TXDSP memory consists of six 32K x 8 SRAM ICs. The TXDSP communicates with the host bus via an 8-bit interface.


1-Dec-06 68P80801E35-E 2-11



Error Correction Digital Signal Processor (CLN1472 Only)

The Error Correction Digital Signal Processor (U30) used in the Model CLN1472 operates at a clock speed of 60 MHz. An on-board oscillator (Y100) operating at 10 MHz is multiplied internal to the ECDSP to generate the required clock signal.

The main function of the Error Correction Digital Signal Processor (ECDSP) is decoding. It accepts data from the Synchronous Serial Interface (SSI) bus. Various algorithms are performed on the signal before it is sent to the TXDSP via the SSI bus.

The ECDSP contains its own address and data bus to access its DSP program and signal processing algorithms contained in local memory. Two 32K x 8 SRAM ICs (U27 and U31) comprise the ECDSP memory. The ECDSP communicates with the host bus via an 8-bit interface.

TISIC

The TISIC controls all internal DSP operations. This circuit provides a number of functions, including the following: Interfaces with the DSPs via the DSP address and data buses. Accepts a 16.8 MHz signal and a 1 PPS signal from Station

Reference Circuitry. Outputs a 2.1 MHz reference signal used by the Exciter and Receivers. Outputs a 4.8 MHz reference signal used by the Exciter to clock data into

the TRANLIN IC. Accepts differential data from Receiver (RX1 through RX3) via

interface circuitry. Accepts and sends serial data from the Receiver (RX1 through RX3) via

serial data bus. Accepts and formats differential data from the TXDSP for transmission to

the Exciter via interface circuitry. Generates 15 ms and 7.5 ms ticks. These are synchronized to the 1 PPS time

mark from the iSC for routing to the TXDSP and RXDSP, respectively. Generates the Receive SSI (RXSSI) frame sync interrupt for the RXDSP.


2-12 68P80801E35-E 1-Dec-06




The Station Reference Circuitry is a phase-locked loop consisting of a high-stability Voltage Controlled Crystal Oscillator (VCXO) and a Phase Locked Loop IC. The GPS output from the iSC is connected to the 5 MHz/1 PPS A BNC connector on the EBTS junction panel. In this mode, the PLL compares the reference frequency to the 16.8 MHz VCXO output and generates a DC correction voltage. The control voltage enable switch is closed. This allows the control voltage from the PLL to adjust the high-stability VCXO frequency to a stability equivalent to that of the external 5 MHz frequency reference.

The VXCO is continually frequency-controlled by the control voltage from the PLL and outputs a 16.8 MHz clock signal which is applied to the TISIC.

The TISIC divides the 16.8 MHz signal by 8 and outputs a 2.1 MHz signal. This signal is separated and buffered by a splitter. The output signal is then sent to the Exciter and Receivers as a 2.1 MHz reference via the backplane.

The 4.8 MHz reference signal generated by the TISIC is applied to the Exciter module, where it is used to clock data into and out of the TRANLIN IC.

Input Ports

Two general purpose, 16-line input ports provide for various input signals from the BRC and station circuitry. These inputs are sent to the Host Micro-processor.

Input Port P0 In and Port P1 In each consist of 16 lines from circuitry in the BRC, as well as other modules in the station via the backplane. The buses communicate with the buffers to make data available to the Host Micropro-cessor via the Host Data Bus. The DIP switch and the Station Reference Circuitry are typical inputs for these ports.

Output Ports

Three general purpose 16-line output ports provide various control signals from the Host Microprocessor to the BRC and station circuitry via the backplane.

The three output ports, Port P0 Out through Port P2 Out, each consist of 16 lines from the Host Data Bus via latches.

Typical control signals from these output ports vary from the control signals for the eight front panel LEDs and the address select lines for SPI peripherals.


1-Dec-06 68P80801E35-E 2-13



Remote Station Shutdown

The BRC contains circuitry to send a shutdown pulse to the Base Radio Power Supply. After receiving this pulse, the power supply cycles the power for the BR, including the 5.1 VDC, 28.6 VDC and 14.2 VDC distributed through the BR. The BRC generates the shutdown pulse through software control. A remote site uses the shutdown function to perform a hard reset of all modules in the BR.


2-14 68P80801E35-E 1-Dec-06


Enhanced Base Radio Controller

Enhanced Base Radio Controller 2

Enhanced Base Radio Controller Overview

Generation 2 BR/EBRC Compatibility

The Enhanced Base Radio Controller (EBRC) serves as the main controller for the Base Radio. The EBRC provides signal processing and operational control for other Base Radio modules. Figure 2-4 shows a top view of the EBRC with the cover removed. The EBRC module consists of two printed circuit boards (EBRC board and LED display board), a slide-in housing, and associated hardware. The EBRC is only compatible with System Software Release SR 9.15 or

newer. Any system running a pre-SR 9.15 System Release must be updated to at least SR 9.15 prior to installation.

The EBRC is compatible with Legacy Base Radios that support multiple receiver module assemblies.

The Generation 2 Base Radio is compatible with all versions of power supplies.

Determining FRU and Kit Revisions

For Generation 2 BR/EBRC

These commands will return all available FRU and Kit Revision numbers. Use these to determine installation requirements:


2. Connect the other end of the RS-232 cable to the Service Access port, located on the front panel of the EBRC module.

Table 2-7 EBRC Compatibility

Module Software Revision Compatible

Exciter R01.00.xx- R01.03.xx SR 10.0 or Greater

Exciter R01.04.xx and higher SR 9.15 or Greater

Single Receiver R01.00.xx - R01.02.xx SR 10.0 or Greater

Single Receiver R01.03.xx and higher SR 9.15 or Greater

3X Receiver all versions SR 9.15 or Greater

40W Power Amplifier all versions SR 9.15 or Greater

70W Power Amplifier all versions SR 9.15 or Greater


1-Dec-06 68P80801E35-E 2-15



3. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the Control Module front panel. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the password motorola, log in to the BR.



For Legacy Single Channel BR/BRC




:> login -ufield

password: motorola

f ie ld>

f ield> fv -oplatform

f ie ld>


2-16 68P80801E35-E 1-Dec-06





EBRC Description

The EBRC memory contains the operating software and codeplug. The software defines BR operating parameters, such as output power and operating frequency.

The EBRC connects to the Base Radio backplane with one 96-pin Euro connector and one blindmate RF connector. Two Torx screws secure the EBRC in the Base Radio chassis.

Figure 2-4 shows a top view of the EBRC (model CLN1653) with the cover removed. The EBRC module contains the main board, CLN7428 and LED board, CLN7208.

BRC>dekeyBRC>test_modeBRC>get brc_rev_noBRC>get rx1_rev_noBRC>get rx2_rev_noBRC>get rx3_rev_no (if BR is 3 branch)BRC>get pa_rev_noBRC>get ex_rev_no

BRC>


1-Dec-06 68P80801E35-E 2-17



Figure 2-4 Enhanced Base Radio Controller, version CLN1653 (with cover removed)

Enhanced Base Radio Controller Controls and Indicators

The EBRC monitors the functions of other Base Radio modules. The LEDs on the front panel indicate the status of EBRC-monitored modules. The CTL LED on the front panel light momentarily on initial BR power-up and on BR resets. Figure 2-5 shows the front panel of the EBRC.

Figure 2-5 EBRC (Front View)

EBTS316g06701SJW

ENHANCED CONTROLRESETB R P S E X PA C T L R 1 R 2 R 3SERVICE ACCESS


2-18 68P80801E35-E 1-Dec-06



Indicators

Table 2-8 lists and describes the EBRC LEDs.

Table 2-8 EBRC Indicators

LED ColorModule


BR Green BR

Solid (on) Station is keyed

Flashing (on)

Station is not keyed

Off Station is out of service or power is removed

PS RedPower Supply

Solid (on)FRU failure indication - Power Supply has a major alarm and is out of service

Flashing (on)

Power Supply has a minor alarm and may be operating at reduced performance

Off Power Supply under normal operation (no alarms)

EX Red Exciter

Solid (on)FRU failure indication - Exciter has a major alarm and is out of service

Flashing (on)

Exciter has a minor alarm and may be operating at reduced performance

OffExciter under normal operation (no alarms)


Solid (on)FRU failure indication - PA has a major alarm and is out of service

Flashing (on)

PA has a minor alarm and may be operating at reduced performance

Off PA under normal operation (no alarms)

CTL Red Controller

Solid (on)FRU failure indication - BRC has a major alarm and is out of service.

Flashing (on)

BRC has a minor alarm and may be operating at reduced performance

Off BRC under normal operation (no alarms)

R1R2R3

RedReceiver #1, #2, or #3

Solid (on)FRU failure indication - Receiver (#1, #2, or #3) has a major alarm and is out of service

Flashing (on)

Receiver (#1, #2, or #3) has a minor alarm and may be operating at reduced performance

OffReceiver (#1, #2, or #3) under normal operation (no alarms)


1-Dec-06 68P80801E35-E 2-19



Controls


STATUS Connector


Table 2-9 EBRC Controls

Control Description




Pin-out Signal

1 not used

2 TXD

3 RXD

4 not used

5 GND

6 not used

7 not used

8 not used

9 not used


2-20 68P80801E35-E 1-Dec-06



Enhanced Base Radio Controllers Theory of Operation

Table 2-11 briefly describes the EBRC circuitry. Figure 2-12 is a functional block diagram of the EBRC.

Table 2-11 EBRC Circuitry

Circuit Description

Host MicroprocessorContains integrated circuits that comprise the central controller of the EBRC and station

Non-Volatile Memory

Consists of: FLASH containing the station operating softwareEEPROM containing the station codeplug data

Volatile MemoryContains SDRAM to store station software used to execute commands.

Ethernet InterfaceProvides the EBRC with a 10Base2 Ethernet communication port to network both control and compressed voice data

RS-232 InterfaceProvides the EBRC with an RS-232 serial interface

Digital Signal ProcessorsPerforms high-speed modulation/demodulation of compressed audio and signaling data

TISICContains integrated circuits that provide timing reference signals for the station

TX ReclockContains integrated circuits that provide highly stable, reclocked transmit signals and peripheral transmit logic


Generates the 16.8 MHz and 48 MHz reference signals used throughout the station

Input Ports Contains 16 signal input ports that receive miscellaneous inputs from the BR

Output PortsContains 40 signal output ports, providing a path for sending miscellaneous control signals to circuits throughout the BR



1-Dec-06 68P80801E35-E 2-21



MPC860 Host Microprocessor

The MPC860 host microprocessor is the main controller for the BR. The processor operates at a 50-MHz clock speed. The processor controls Base Radio operation according to station software in memory. Station software resides in FLASH memory. For normal operation, the system transfers this software to non-volatile memory. An EEPROM contains the station codeplug.Note At BR power-up, the EBRC LED indicates a major alarm. This

indication continues until BR software achieves a predetermined state of operation. Afterward, the software turns off the EXBRC LED.


The microprocessor provides a general-purpose SMC serial management controller bus.

The SMC serial communications bus is an asynchronous RS-232 interface with no hardware handshake capability. The BRC front panel includes a nine-pin, D-type connector. This connector provides a port where service personnel may connect a service computer. Service personnel can perform programming and maintenance tasks via Man-Machine Interface (MMI) commands. The interface between the SMC port and the front- panel STATUS connector is via EIA-232 Bus Receivers and Drivers.

Host Processor

The microprocessor incorporates 4k bytes of instruction cache and 4k bytes of data cache that significantly enhance processor performance.

The microprocessor has a 32-line address bus. The processor uses this bus to access non-volatile memory and SDRAM memory. Via memory mapping, the processor also uses this bus to control other BRC circuitry.

The microprocessor uses its Chip Select capability to decode addresses and assert an output signal. The eight chip-select signals select non-volatile memory, SDRAM memory, input ports, output ports, and DSPs.

The Host processor... Provides serial communications between the Host Microprocessor and

other Base Radio modules. Provides condition signals necessary to access SDRAM. Accepts interrupt signals from EBRC circuits (such as DSPs). Organizes the interrupts, based on hardware-defined priority ranking. The Host supports several internal interrupts from its Communications

Processor Module. These interrupts allow efficient use of peripheral interfaces.

The Host supports 10 Mbps Ethernet/IEEE 802.3.


2-22 68P80801E35-E 1-Dec-06



Provides a 32-line data bus transfers data to and from EBRC SDRAM and other BRC circuitry. Buffers on this data bus allow transfers to and from non-volatile memory, general input and output ports and DSPs.

Non-Volatile Memory

Base Radio software resides in 2M x 32 bits of FLASH memory. The Host Microprocessor addresses the FLASH memory with 20 of the host address bus’ 32 lines. The host accesses FLASH data over the 32-line host data bus. A host-operated chip-select line provides control signals for these transactions.

The FLASH contains the operating system and application code. The system stores application code in FLASH for fast recovery from reset conditions. Application code transfers from network or site controllers may occur in a background mode. Background mode transfers allow the station to remain operational during new code upgrades.

The data that determines the station personality resides in a 32K x eight bit codeplug EEPROM. The microprocessor addresses the EEPROM with 15 of the host address bus’ 32 lines. The host accesses EEPROM data with eight of the data bus’ 32 lines. A host-operated chip-select line provides control signals for these transactions.

During the manufacturing process, the factory programs the codeplug’s default data. The BRC must download field programming data from network and site controllers. This data includes operating frequencies and output power level. The station permits adjustment of many station parameters, but the station does not store these adjustments. Refer to the Software Commands chapter for additional information.

Volatile Memory

Each BRC contains 8MB x 32 bits of SDRAM. The BRC downloads station software code into SDRAM for station use. SDRAM also provides short-term storage for data generated and required during normal operation. SDRAM is volatile memory. A loss of power or system reset destroys SDRAM data.

The system performs read and write operations over the Host Address and Data buses. These operations involve column and row select lines under control of the Host processor’s DRAM controller. The Host address bus and column row signals sequentially refresh SDRAM memory locations.

Ethernet Interface

The Host processor’s Communications Processor Module (CPM) provides the Local Area Network (LAN) Controller for the Ethernet Interface. The LAN function implements the CSMA/CD access method, which supports the IEEE 802.3 10Base2 standard.


1-Dec-06 68P80801E35-E 2-23




The PCM LAN receives commands from the CPU.

The Ethernet Serial Interface works directly with the CPM LAN to perform the following major functions: 10 MHz transmit clock generation (obtained by dividing the 20 MHz signal

provided by on-board crystal) Manchester encoding/decoding of frames electrical interface to the Ethernet transceiver

An isolation transformer provides high-voltage protection. The transformer also isolates the Ethernet Serial Interface (ESI) and the transceiver. The pulse transformer has the following characteristics: Minimum inductance of 75 µH 2000 V isolation between primary and secondary windings 1:1 Pulse Transformer

The Coaxial Transceiver Interface (CTI) is a coaxial cable line driver and receiver for the Ethernet. CTI provides a 10Base2 connection via a coaxial connector on the board. This device minimizes the number of external compo-nents necessary for Ethernet operations.

A DC/DC converter provides a constant voltage of -9 Vdc for the CTI from a 3.3 Vdc source.

The CTI performs the following functions: Receives and transmits data to the Ethernet coaxial connection Reports any collision that it detects on the coaxial connection Disables the transmitter when packets are longer than the legal length

(Jabber Timer)


2-24 68P80801E35-E 1-Dec-06




The BRC includes two Receive Digital Signal Processors (RXDSPs) and a Transmit Digital Signal Processor (TXDSP). These DSPs and related circuitry process compressed station transmit and receive audio or data. The related circuitry includes the TDMA Infrastructure Support IC (TISIC) and the TISIC Interface Circuitry. The DSPs only accept input and output signals in digitized form.

The RXDSP inputs are digitized receiver signals. The TXDSP outputs are digitized voice audio and data (modulation signals). These signals pass from the DSP to the Exciter portion of the EXBRC. DSPs communicate with the Microprocessor via an eight-bit, host data bus on the host processor side. For all DSPs, interrupts drive communication with the host.

The RXDSP operates from an external 16.8 MHz clock, provided by the local station reference. The RXDSP internal operating clock signal is 150MHz, produced by an internal Phase-Locked Loop (PLL).

The RXDSP accepts digitized signals from the TISIC device through the RxDSP parallel bus. The RXDSP supports a single carrier (single 3 branch receiver) digital data input.

The RXDSP accesses its DSP program and signal-processing algorithms in 128k words of internal memory. The RXDSP communicates with the host bus on an 8-bit interface.

Additionally, a serial control path connects the two RXDSPs and the TXDSP. The Synchronous Communications Interface (SCI) port facilitates this serial control path.

For initialization and control purposes, the RXDSP connects to the TISIC device.

The TXDSP operates at an external clock speed of 16.8 MHz, provided by the EBRC local station reference. The TXDSP internal operating clock is 150MHz, produced by an internal Phase Lock Loop (PLL).

The TXDSP sends one carrier of digitized signal to the TISIC to reformat the date before sending it to the exciter. The exciter converts the digital signal to analog.

The TXDSP contains its own, internal address and data memory. The TXDSP can store 128k words of DSP program and data memory. An eight-bit interface handles TXDSP-to-host bus communications.

TISIC

The TISIC controls internal DSP operations. This circuit provides the following functions:


1-Dec-06 68P80801E35-E 2-25



For initialization and control, interfaces with the RXDSP via the DSP address and data buses.

Accepts a 16.8 MHz signal from Station Reference Circuitry. Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from

the site reference. Demodulates the 1 PPS from the modulated 5 MHz signal Outputs a 1 PPS signal and a windowed version of this signal for network

timing alignment. Outputs a 2.1 MHz reference signal used by the Exciter and Receiver(s). Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS

time mark. The system decodes the time mark from the site reference. Then the system routes the reference to the TXDSP and RXDSP.)

Provides a 4.8 MHz reference signal. This signal is used by the Exciter to clock data into the TRANLIN

Accepts differential data from the Receiver(s) (Rx through Rx3) via the interface circuitry.

Transmits serial control data to the Receiver(s) (Rx through Rx3) via the serial data bus.

Accepts and formats differential data from the TXDSP for transmission to the Exciter via interface circuitry.

Generates the Receiver SSI (RxSSI) frame sync interrupt for the RxDSP.


The Station Reference Circuitry is a phase-locked loop (PLL). This PLL consists of a high-stability, Voltage-Controlled, Crystal Oscillator (VCXO) and a PLL IC. GPS output from the iSC connects to the 5 MHz/1 PPS BNC connector on the BR backplane. Wiring at this connector routes signals to EXBRC station reference circuitry.

The PLL compares the 5 MHz reference frequency to the 16.8 MHz VCXO output. Then the PLL generates a DC correction voltage. The PLL applies this correction voltage to the VCO through an analog gate. The analog gate closes when three conditions coexist: (1) The 5 MHz tests stable. (2) The PLL IC is programmed. (3) Two PLL oscillator and reference signal output alignments occur.

A loss in the 5MHz / 1PPS signal causes the control voltage enable switch to open. This complex PLL control allows the BR to maintain 16.5 MHz capability during short disconnects (of approximately one minute) of the 5 MHz / 1 PPS signal. (For example, during 5 MHz / 1 PPS cable maintenance work.)

When the gate enables, the control voltage from the PLL can adjust the high-stability VCXO frequency. The adjustment can achieve a stability nearly equivalent to that of the external, 5 MHz frequency reference.


2-26 68P80801E35-E 1-Dec-06



The correction voltage from the PLL continuously adjusts the VXCO frequency. The VXCO outputs a 16.8 MHz clock signal. The circuit applies this clock signal to the receiver, and TISIC.

The TISIC divides the 16.8 MHz signal by seven, and outputs a 2.1 MHz signal. This output signal then becomes the 2.1 MHz reference for the Exciter and Receiver(s).

Input Ports

One general-purpose input register provides for EBRC and station circuit input signals. The register has 16 input ports. The Host Data Bus conveys input register data to the Host Microprocessor. Typical inputs include 16.8 Station Reference Circuitry status outputs and reset status outputs.

Output Ports

Two general-purpose output registers distribute control signals from the Host Microprocessor to the BRC and station circuitry. One register has 32 output ports and the other register has 8 output ports. Control signal distribution occurs over the backplane. The Host Data Bus drives the output ports’ latched outputs. Typical control signals include front-panel LED signals and SPI peripheral enable and address lines.


The EBRC contains power supply shutdown circuitry. This circuitry can send a shutdown pulse to the Base Radio Power Supply. BRC software generates the shutdown control pulse.

After receiving a shutdown pulse, the power supply turns off BR power. Shut down power sources include 3.3, 5.1, 28.6 and 14.2 Vdc sources throughout the BR. Due to charges retained by BR storage elements, power supply voltages may not reach zero. The shutdown only assures that the host processor enters a power-on-reset state.

A remote site uses the shutdown function to perform a hard reset of all BR modules.


1-Dec-06 68P80801E35-E 2-27


900 MHz QUAD Channel Base Radio Controller

900 MHz QUAD Channel Base Radio Controller 2

900 MHz QUAD Channel Base Radio Controller Overview

The Base Radio Controller (BRC) provides signal processing and operational control for Base Radio modules. The BRC module consists of a printed circuit board, a slide-in housing, and associated hardware.

The BRC memory contains the operating software and codeplug. The software defines BR operating parameters, such as output power and operating frequency.

The BRC connects to the Base Radio backplane with one 168-pin FutureBus+ connector and one blindmate RF connector. Two Torx screws secure the BRC in the Base Radio chassis.

Figure 2-6 shows a top view of the EX/CNTL (model CLF1560) with the cover removed.

Figure 2-6 900 MHz QUAD Channel Base Radio Controller, version DLN1203 (with cover removed)

900 MHz QUAD Channel Base Radio Controller Controls and Indicators

The BRC monitors the functions of other Base Radio modules. The LEDs on the front panel indicate the status of BRC-monitored modules. All LEDs on the BRC front panel normally flash three times upon initial power-up. A RESET switch allows a manual reset of the Base Radio. Figure 2-7 shows the front panel of the BRC.


2-28 68P80801E35-E 1-Dec-06



Figure 2-7 900 MHz QUAD Channel BR Controller (Front View)

Indicators


QUAD CHANNEL EX/CNTLSTATUSRESET

T X 4T X 4

T X 4T X 4

P S E X / C N T L

PA R E FR X 1

R X 2R X 3

R X 4

EBTS316Q013001JNM

Table 2-12 900 MHz QUAD Channel BR Controller Indicators

LED ColorModule


PS Red Power Supply

Solid (on)FRU failure indication - Power Supply has a major alarm, and is out of service

Flashing (on)

Power Supply has a minor alarm, and may be operating at reduced performance

Off Power Supply is operating normally (no alarms)

EXBRC RedController/Exciter

Solid (on)

FRU failure indication - Controller/Exciter has a major alarm, and is out of service (Note: Upon power-up of the BR, this LED indicates a failed mode until BR software achieves a known state of operation.)

Flashing (on)

Controller/Exciter has a minor alarm, and may be operating at reduced performance

Off Controller/Exciter is operating normally (no alarms)


Solid (on)FRU failure indication - PA has a major alarm, and is out of service

Flashing (on)

PA has a minor alarm, and may be operating at reduced performance

Off PA is operating normally (no alarms)


1-Dec-06 68P80801E35-E 2-29



REF RedController Station Reference

Solid (on)FRU failure indication - Controller Station Reference has a major alarm, and is out of service

Flashing (on)

BRC has a minor alarm, and may be operating in a marginal region

Off BRC is operating normally (no alarms)

RX1RX2RX3RX4

RedReceiver #1, #2, #3, or #4

Solid (on)FRU failure indication - Receiver (#1, #2, #3 or #4) has a major alarm, and is out of service

Flashing (on)

Receiver (#1, #2, #3 or #4) has a minor alarm, and may be operating at reduced performance

OffReceiver (#1, #2, #3 or #4) is operating normally (no alarms)

TX1 Green BR

Solid (on) Station Transmit Carrier #1 is keyed

Flashing (on)

Station Transmit Carrier #1 is not keyed

Off Station is out of service, or power is removed

TX2 Green BR


Flashing (on)



TX3 Green BR


Flashing (on)



TX4 Green BR


Flashing (on)


OffStation is out of service, or power is removed

Table 2-12 900 MHz QUAD Channel BR Controller Indicators (continued)

LED ColorModule



2-30 68P80801E35-E 1-Dec-06



Controls


STATUS Connector


Table 2-13 900 MHz QUAD Channel BR Controller Controls

Control Description




Pin-out Signal

1 not used

2 TXD

3 RXD

4 not used

5 GND

6 not used

7 not used

8 not used

9 not used


1-Dec-06 68P80801E35-E 2-31



900 MHz QUAD Channel Base Radio Controller Theory of Operation

Table 2-15 briefly describes the BRC circuitry. Figure 2-14 is a functional block diagram of the BRC.

Table 2-15 900 MHz QUAD Channel BR Controller Circuitry

Circuit Description

Host MicroprocessorContains integrated circuits that comprise the central controller of the BRC and station

Non-Volatile Memory




RS-232 InterfaceProvides the BRC with an RS-232 serial interface




RX DSP SPIContains integrated circuits that provide DSP SPI capability and peripheral receive logic







2-32 68P80801E35-E 1-Dec-06



Host Microprocessor

The host microprocessor is the main controller for the BR. The processor operates at a 50-MHz clock speed. The processor controls Base Radio operation according to station software in memory. Station software resides in FLASH memory. For normal operation, the system transfers this software to non-volatile memory. An EEPROM contains the station codeplug.Note At BR power-up, the EXBRC LED indicates a major alarm. This





Host Processor

The microprocessor incorporates 4k bytes of instruction cache and 4k bytes of data cache that significantly enhance processor performance.




other Base Radio modules. Provides condition signals necessary to access SDRAM. Accepts interrupt signals from BRC circuits (such as DSPs). Organizes the interrupts, based on hardware-defined priority ranking. The Host supports several internal interrupts from its Communications




1-Dec-06 68P80801E35-E 2-33



Provides a 32-line data bus transfers data to and from BRC SDRAM and other BRC circuitry. Buffers on this data bus allow transfers to and from non-volatile memory, general input and output ports and DSPs.

Non-Volatile Memory





Volatile Memory



Ethernet Interface



2-34 68P80801E35-E 1-Dec-06











(Jabber Timer)


1-Dec-06 68P80801E35-E 2-35






The RXDSPs operate from an external 16.8 MHz clock, provided by the local station reference. The RXDSP internal operating clock signal is 150MHz, produced by an internal Phase-Locked Loop (PLL).

The RXDSPs accept digitized signals from the receivers through Enhanced Synchronous Serial Interface (ESSI) ports. Each of two ESSI ports on a RXDSP supports a single carrier (single receiver) digital data input. The DSP circuitry includes two RXDSPs. These allow processing of up to four carriers (four receivers).

The RXDSP accesses its DSP program and signal-processing algorithms in 128k words of internal memory. The RXDSPs communicate with the host bus over an 8-bit interface.

Each RXDSP provides serial communications to its respective receiver module for receiver control via a Serial Peripheral Interface (SPI). The SPI is a parallel-to-serial conversion circuit, connected to the RXDSP data bus. Each RXDSP communicates to two receive modules through this interface.


For initialization and control purposes, one RXDSP connects to the TISIC device.

The TXDSP operates at an external clock speed of 16.8 MHz, provided by the EXBRC local station reference. The TXDSP internal operating clock is 150MHz, produced by an internal Phase Lock Loop (PLL).

The TXDSP sends up to four carriers of digitized signal to the EX11 exciter. The exciter converts the digital signal to analog. Also at the exciter, a highly stable clock reclocks the digital data. Reclocking enhances transmit signal integrity. Two framed and synchronized data streams result. One data stream is I-data, and the other is the Q-data stream.


2-36 68P80801E35-E 1-Dec-06




TISIC

The TISIC controls internal DSP operations. This circuit provides the following functions: For initialization and control, interfaces with one RXDSP via the DSP

address and data buses. Accepts a 16.8 MHz signal from Station Reference Circuitry. Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from

the site reference. Demodulates the 1 PPS Outputs a 1 PPS signal and a windowed version of this signal for network

timing alignment. Outputs a 2.4 MHz reference signal used by the Exciter. Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS

time mark. The system decodes the time mark from the site reference. Then the system routes the reference to the TXDSP and RXDSPs.)





The correction voltage from the PLL continuously adjusts the VXCO frequency. The VXCO outputs a 16.8 MHz clock signal. The circuit applies this clock signal to the receiver, 48 MHz reference and TISIC.

The receivers use the 16.8MHz as the clock input and synthesizer reference.


1-Dec-06 68P80801E35-E 2-37



The 48 MHz EXBRC synthesizer uses the 16.8 MHz as its synthesizer reference. The 48 MHz synthesizer output is the clock input for the TXDSP I and Q data reclock circuitry.

The TISIC divides the 16.8 MHz signal by seven, and outputs a 2.4 MHz signal. This output signal then becomes the 2.4 MHz reference for the Exciter.

Input Ports

One general-purpose input register provides for BRC and station circuit input signals. The register has 16 input ports. The Host Data Bus conveys input register data to the Host Microprocessor. Typical inputs include 16.8 and 48 MHz Station Reference Circuitry status outputs and reset status outputs.

Output Ports



The BRC contains power supply shutdown circuitry. This circuitry can send a shutdown pulse to the Base Radio Power Supply. BRC software generates the shutdown control pulse.

After receiving a shutdown pulse, the power supply turns off BR power. Shut down power sources include 3.3, 28.6 and 14.2 Vdc sources throughout the BR. Due to charges retained by BR storage elements, power supply voltages may not reach zero. The shutdown only assures that the host processor enters a power-on-reset state.



2-38 68P80801E35-E 1-Dec-06



800 MHz QUAD Channel Base Radio Controller 2

800 MHz QUAD Channel Base Radio Controller Overview

The 800 MHz Base Radio Controller (BRC) provides signal processing and operational control for Base Radio modules. The BRC module consists of a printed circuit board, a slide-in housing, and associated hardware.

The BRC memory contains the operating software and codeplug. The software defines BR operating parameters, such as output power and operating frequency.

The BRC connects to the Base Radio backplane with one 168-pin FutureBus+ connector and one blindmate RF connector. Two Torx screws secure the BRC in the Base Radio chassis.

Figure 2-8 shows a top view of the EX/CNTL (model CLF1560) with the cover removed.

Figure 2-8 800 MHz QUAD Channel Base Radio Controller, version CLN1469 (with cover removed)

800 MHz QUAD Channel Base Radio Controller Controls and Indicators

The BRC monitors the functions of other Base Radio modules. The LEDs on the front panel indicate the status of BRC-monitored modules. All LEDs on the BRC front panel normally flash three times upon initial power-up. A RESET switch allows a manual reset of the Base Radio. Figure 2-9 shows the front panel of the BRC.


1-Dec-06 68P80801E35-E 2-39



Figure 2-9 800 MHz QUAD Channel BR Controller (Front View)

Indicators


QUAD CHANNEL EX/CNTLSTATUSRESET

T X 4T X 4

T X 4T X 4

P S E X / C N T L

PA R E FR X 1

R X 2R X 3

R X 4

EBTS316Q013001JNM

Table 2-16 800 MHz QUAD Channel BR Controller Indicators

LED ColorModule


PS RedPower Supply

Solid (on)FRU failure indication - Power Supply has a major alarm, and is out of service

Flashing (on)

Power Supply has a minor alarm, and may be operating at reduced performance

Off Power Supply is operating normally (no alarms)

EXBRC RedController/Exciter

Solid (on)

FRU failure indication - Controller/Exciter has a major alarm, and is out of service (Note: Upon power-up of the BR, this LED indicates a failed mode until BR software achieves a known state of operation.)

Flashing (on)

Controller/Exciter has a minor alarm, and may be operating at reduced performance

Off Controller/Exciter is operating normally (no alarms)


Solid (on)FRU failure indication - PA has a major alarm, and is out of service

Flashing (on)

PA has a minor alarm, and may be operating at reduced performance

Off PA is operating normally (no alarms)


2-40 68P80801E35-E 1-Dec-06



REF RedController Station Reference

Solid (on)FRU failure indication - Controller Station Reference has a major alarm, and is out of service

Flashing (on)

BRC has a minor alarm, and may be operating in a marginal region

Off BRC is operating normally (no alarms)

RX1RX2RX3RX4

RedReceiver #1, #2, #3, or #4

Solid (on)FRU failure indication - Receiver (#1, #2, #3 or #4) has a major alarm, and is out of service

Flashing (on)

Receiver (#1, #2, #3 or #4) has a minor alarm, and may be operating at reduced performance

OffReceiver (#1, #2, #3 or #4) is operating normally (no alarms)

TX1 Green BR


Flashing (on)



TX2 Green BR


Flashing (on)



TX3 Green BR


Flashing (on)



TX4 Green BR


Flashing (on)


OffStation is out of service, or power is removed

Table 2-16 800 MHz QUAD Channel BR Controller Indicators (continued)

LED ColorModule



1-Dec-06 68P80801E35-E 2-41



Controls


STATUS Connector


Table 2-17 800 MHz QUAD Channel BR Controller Controls

Control Description




Pin-out Signal

1 not used

2 TXD

3 RXD

4 not used

5 GND

6 not used

7 not used

8 not used

9 not used


2-42 68P80801E35-E 1-Dec-06



800 MHz QUAD Channel Base Radio Controller Theory of Operation

Table 2-19 briefly describes the BRC circuitry. Figure 2-14 is a functional block diagram of the BRC.

Table 2-19 BR Controller Circuitry

Circuit Description

Host MicroprocessorContains integrated circuits that comprise the central controller of the BRC and station

Non-Volatile Memory




RS-232 InterfaceProvides the BRC with an RS-232 serial interface




RX DSP SPIContains integrated circuits that provide DSP SPI capability and peripheral receive logic







1-Dec-06 68P80801E35-E 2-43



Host Microprocessor

The host microprocessor is the main controller for the BR. The processor operates at a 50-MHz clock speed. The processor controls Base Radio operation according to station software in memory. Station software resides in FLASH memory. For normal operation, the system transfers this software to non-volatile memory. An EEPROM contains the station codeplug.Note At BR power-up, the EXBRC LED indicates a major alarm. This





MPC860 Host Processor

The MPC860 microprocessor incorporates 4k bytes of instruction cache and 4k bytes of data cache that significantly enhance processor performance.




other Base Radio modules. Provides condition signals necessary to access SDRAM. Accepts interrupt signals from BRC circuits (such as DSPs). Organizes the interrupts, based on hardware-defined priority ranking. The Host supports several internal interrupts from its Communications




2-44 68P80801E35-E 1-Dec-06



Provides a 32-line data bus transfers data to and from BRC SDRAM and other BRC circuitry. Buffers on this data bus allow transfers to and from non-volatile memory, general input and output ports and DSPs.

Non-Volatile Memory





Volatile Memory



Ethernet Interface



1-Dec-06 68P80801E35-E 2-45











(Jabber Timer)


2-46 68P80801E35-E 1-Dec-06






The RXDSPs operate from an external 16.8 MHz clock, provided by the local station reference. The RXDSP internal operating clock signal is 150MHz, produced by an internal Phase-Locked Loop (PLL).

The RXDSPs accept digitized signals from the receivers through Enhanced Synchronous Serial Interface (ESSI) ports. Each of two ESSI ports on a RXDSP supports a single carrier (single receiver) digital data input. The DSP circuitry includes two RXDSPs. These allow processing of up to four carriers (four receivers).

The RXDSP accesses its DSP program and signal-processing algorithms in 128k words of internal memory. The RXDSPs communicate with the host bus over an 8-bit interface.

Each RXDSP provides serial communications to its respective receiver module for receiver control via a Serial Peripheral Interface (SPI). The SPI is a parallel-to-serial conversion circuit, connected to the RXDSP data bus. Each RXDSP communicates to two receive modules through this interface.


For initialization and control purposes, one RXDSP connects to the TISIC device.

The TXDSP operates at an external clock speed of 16.8 MHz, provided by the EXBRC local station reference. The TXDSP internal operating clock is 150MHz, produced by an internal Phase Lock Loop (PLL).

The TXDSP sends up to four carriers of digitized signal to the EX11 exciter. The exciter converts the digital signal to analog. Also at the exciter, a highly stable clock reclocks the digital data. Reclocking enhances transmit signal integrity. Two framed and synchronized data streams result. One data stream is I-data, and the other is the Q-data stream.


1-Dec-06 68P80801E35-E 2-47




TISIC

The TISIC controls internal DSP operations. This circuit provides the following functions: For initialization and control, interfaces with one RXDSP via the DSP

address and data buses. Accepts a 16.8 MHz signal from Station Reference Circuitry. Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from

the site reference. Demodulates the 1 PPS Outputs a 1 PPS signal and a windowed version of this signal for network

timing alignment. Outputs a 2.4 MHz reference signal used by the Exciter. Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS

time mark. The system decodes the time mark from the site reference. Then the system routes the reference to the TXDSP and RXDSPs.)




A loss of the 5 MHz/1PPS signal causes the control voltage enable switch to open. This permits the PLL to free run, which allows the BR to retain a clock for control purposes.


The correction voltage from the PLL continuously adjusts the VXCO frequency. The VXCO outputs a 16.8 MHz clock signal. The circuit applies this clock signal to the receiver, 48 MHz reference and TISIC.


2-48 68P80801E35-E 1-Dec-06




The 48 MHz EXBRC synthesizer uses the 16.8 MHz as its synthesizer reference. The 48 MHz synthesizer output is the clock input for the TXDSP I and Q data reclock circuitry.

The TISIC divides the 16.8 MHz signal by seven, and outputs a 2.4 MHz signal. This output signal then becomes the 2.4 MHz reference for the Exciter.

Input Ports

One general-purpose input register provides for BRC and station circuit input signals. The register has 16 input ports. The Host Data Bus conveys input register data to the Host Microprocessor. Typical inputs include 16.8 and 48 MHz Station Reference Circuitry status outputs and reset status outputs.

Output Ports



The BRC contains power supply shutdown circuitry. This circuitry can send a shutdown pulse to the Base Radio Power Supply. BRC software generates the shutdown control pulse.

After receiving a shutdown pulse, the power supply turns off BR power. Shut down power sources include 3.3, 28.6 and 14.2 Vdc sources throughout the BR. Due to charges retained by BR storage elements, power supply voltages may not reach zero. The shutdown only assures that the host processor enters a power-on-reset state.



1-Dec-06 68P80801E35-E 2-49



N O T E S . . .


2-50 68P80801E35-E 1-Dec-06



2-51

HOST BUFFERED DATA BUS


HOST ADDRESS BUS

HOST DATA BUS

DRAM ADDRESSMULTIPLEXER

COLUMN/ROWSELECT

DRAMCOLUMNADDRESS

DRAMROW

ADDRESS

16.5 MHZ CLK

SERIAL COMMUNICATIONS BUS

SERIAL COMMUNICATIONS BUS

ROWSELECT(RAS*)

COLSELECT(CAS*)

DRAMADDRESS

HOSTGLUEASIC

33 MHZTIMING

CIRCUITRYBUFFERS

EPROM512K X 8

8OMLUG

8M

32K X 8SRAM

A1-A11

A10-A22

19

4

8

STATUS PORT(9 PIN D CONNECTORON BRC FRONT PANEL)

RS-232 PORT(9 PIN D CONNECTORON BACKPLANE)

EIA-232BUS

RECEIVERS/DRIVERS

4

8

MX 8

BUFFERS

SPI BUS

SPI BUSTO/FROM

STATION MODULES3

HOST ADDRESS BUS

ORY

OR / HOST ASIC

HOSTADDRESS

1-23

EIA-232BUS

RECEIVERS/DRIVERS

DRAM MEMORY

BUFFERS

A

EBTS286010397SN

D0-D15

D0-D7

D0-D15

D0-D15

VCC RESET SWITCH(FRONT PANEL)

DRAM1M X 16

1-Dec-06 68P80801E35-E

Figure 2-10 800/900 MHz Base Radio Controller Functional Block Diagram (Sheet 1 of 2)

ETHERNETSERIAL

INTERFACE

ISOLATIONTRANSFORMER TRANSCEIVER

HOST ADDRESS BUS

8K XEEPR

CODEP

32K XSRA

A1-A19

A1-A

A1-A15

HOSTADDRESS

A1-A18

EPRO512K

NON-VOLATILE MEM

HOSTMICRO-

PROCESSOR

HOST MICROPROCESS

VARIOUS INPUTSFROM BRC &

STATION CIRCUITRY

INPUT/OUTPUT PORTS CIRCUITRY

I/O PORT P0 IN

HOST DATA BUS

I/O PORT P0 OUT

I/O PORT P1 OUT

I/O PORT P2 OUT

VARIOUSCONTROL

LINES TO BRC &STATION

CIRCUITRY

FROM HOSTMICROPROCESSOR

I/O PORT P1 IN

BUFFERSBUFFERS16

16

16

16

16

REMOTE STATIONSHUTDOWN CIRCUITRY

SHUTDOWN(TO POWER

SUPPLY)

28V

I/O PORTP2 OUT

FRONT PANEL LEDS

LED CONTROLLINES

(P/O I/O PORTP0 OUT)

BASERADIO

POWERSUPPLY

EXCITER PA CTL R1 R2 R3

8

ETHERNET INTERFACE

CD

RX

TX

CLSN

RCV

TRMT

FROMHOST

MICROPROCESSOR

ADDR BUS

DATA BUS

COPROCESSORADDR BUS

COPROCESSORDATA BUS

10BASE2

COAX

ETHERNETSERIAL

INTERFACE

HOSTINTERFACE

ETHERNETCOPROCESSOR

(82596DX)

D0-D15

LANIIC

SHUTDOWNCIRCUITRY

A1-A15

A1-A15

A2-A23


1-Dec-06

Base Radio ControllerFunctional Block Diagram

Model TLN3424(Includes Front Panel Board)


UFFERED DATA BUS

HOST ADDRESS BUS

HOST DATA BUS

DRAM ADDRESSMULTIPLEXER

COLUMN/ROWSELECT

DRAMCOLUMNADDRESS

DRAMROW

ADDRESS

16.5 MHZ CLK

SERIAL COMMUNICATIONS BUS (SCC2)

SERIAL COMMUNICATIONS BUS (SCC3)

ROWSELECT(RAS*)

COLSELECT(CAS*)

COLSELECT(CAS*)

ROWSELECT(RAS*)

DRAMADDRESS

DRAMADDRESS

HOSTASIC

(U509)

33 MHZTIMING

CIRCUITRY(Y500)

FERS- U110)

ROMK X 8802)

X 8AM

804)

A1-A11

A10-A22

STATUS(9 PIN D CONNECTORON BRC FRONT PANEL)

RS232(9 PIN D CONNECTORON BACKPLANE)

EIA-232BUS

RECEIVERS/DRIVERS

(U901, U902)

SPI BUS

SPI BUSTO/FROM

STATION MODULES3

HOST ADDRESS BUS

IC

DRAM1M X 8(U114)

DRAM1M X 8(U114)

HOSTADDRESS

1-23

EIA-232BUS

RECEIVERS/DRIVERS

(U900)

DYNAMIC RAM

A

BUFFERS(U108 - U110)

BUFFERS(U108 - U110)

6

9

STATIC RAM


2-52 68P80801E35-E

Figure 2-11 800/900 MHz Base Radio Controller Functional Block Diagram (Sheet 2 of 2)

HOST ADDRESS BUS

HOST B

BUF(U107

EP256(U

8K X 8EEPROM

CODEPLUG(U800)

8K X 8SRAM(U803)

8KSR(U

A1-A18

A1-A18

A1-A15

HOSTADDRESS

A1-A23

4

8

EPROM256K X 8(U801)

NON-VOLATILE MEMORY

HOSTMICRO-

PROCESSOR(U701)

HOST MICROPROCESSOR / HOST AS

VARIOUS INPUTSFROM BRC &

STATION CIRCUITRY

INPUT/OUTPUT PORTS CIRCUITRY

I/O PORT P0 IN

HOST DATA BUS I/O PORT P0 OUT

I/O PORT P1 OUT

I/O PORT P2 OUT

I/O PORT P3 OUT

VARIOUSCONTROL

LINES TO BRC &STATION

CIRCUITRY

FROM HOSTMICROPROCESSOR

I/O PORT P1 IN

LATCHES(U602 - U605,U608 - U611)BUFFERS

(U600, U601,U606, U607)

16

16

16

16

16

16

REMOTE STATIONSHUTDOWN CIRCUITRY

SHUTDOWN(TO POWER

SUPPLY)

28V

I/O PORTP3 OUT

FRONT PANEL LEDS (Part of TRN7769)

LED CONTROLLINES

(P/O I/O PORTP0 OUT)

BASERADIO

POWERSUPPLY

EXCITER PA BRC RX1 RX2 RX3

8

ETHERNET INTERFACE

CD

RX

TX

CLSN

RCV

TRMT

FROMHOST

MICROPROCESSOR

ADDR BUS

DATA BUS

COPROCESSORADDR BUS

COPROCESSORDATA BUS

10BASE2

COAX

ETHERNETSERIAL

INTERFACE82596DXETHERNET

COPROCESSOR(U408)

ETHERNETSERIAL

INTERFACE(U1308)

TRANSCEIVER(U1311)

HOSTINTERFACE

(U404 - U406)

ISOLATIONTRANSFORMER

(T100)

SHUTDOWNCIRCUITRY

(U3)

DC/DCCONVERTER

(U1310)5 VDC

-9 VDC

23

16

20 MHZTIMINGCIRCUIT(Y1300)

XMT CLK(10 MHZ)

A1-A13

A1-A13



2-53

REMOTE STATION

28V

P0_OUT SHUTDOWNCIRCUITRY

SHUTDOWN(TO POWERSUPPLY)

SHUTDOWN CIRCUITRY

1-Dec-06 68P80801E35-E

Figure 2-12 Enhanced Base Radio Controller Functional Block Diagram (Sheet 1 of 2)

BASERADIO

POWER EXCITER PA CTL RX1 RX2 R3

P0 OUT

LEDCONTROLLINESHOSTLATCH

12

FRONT PANEL LEDS

SYNTHESIZERIC / CIRCUITRY

5MHZ_1PPSBASE RADIOINPUT

HIGHSTABILITYVCXO

PHASEDETECTION/FILTERING/CONTROL

STEARINGLINE

DISCONNECT/CONNECTCONTROL

GATING

SPIBUS

16.8 MHZ

STATION REFERENCE CIRCUITRY

5MHZ1PPS

SUPPLY


1-Dec-06

CONTROL BUSTOSTATION MODULES

P0_OUT/P1_OUT

ANSMITIGITALGNALOCESSOR

X DSP)

SINGLE ENDTO DIFFERENTIAL

SERIAL DATA ANDCLOCK TO EXCITER

ECEIVEIGITALGNALOCESSOR

X DSP 1)

TISIC

A[0:5]

D[0, 8:23]D[0, 23]

SERIAL CONTROL DATATO RECEIVER 1

2.1 MHz

NETWORKEDSCI

FRONT PANELRESET

TO EXCITER

5MHZ1PPS

AND RECEIVERS

SERIAL CONTROL DATATO RECEIVER 2SERIAL CONTROL DATATO RECEIVER 3

BUFFER/SPLITTER

TRANSMITSERIALDATA BUS 3

AGC

4

AGC TOALL RECEIVERS


2-54 68P80801E35-E

Figure 2-13 Enhanced Base Radio Controller Functional Block Diagram (Sheet 2 of 2)

HOSTMICRO-

ETHERNETSERIAL

INTERFACETRANS-

CD

RCV RX

TRMT TX

CLSN

10BASE2COAX

ETHERNETSERIALINTERFACE

CEIVERISOLATION

TRANSFORMER

PROCESSOR

SCC1

8

SDRAM4M x 16

SDRAM4M x 16

SDRAM4M x 16

SDRAM4M x 16

GPLA0, A[8,9,17,18,20:29],RAS,CAS,WE

CS2

CS3

D[0:31]

D[0:15]

D[16:31]

D[0:15]

D[16:31]

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

D[0:31]

D[0:7]

A[10:31]

MA[21:0]

DSP_D[31:24]

A[0:7]

DSP_A[31:24]

MD[31:0]

EIA-232BUSRECEIVERS/DRIVERS

2STATUS PORT(9 PIN D CONNECTORON BRC FRONT PANEL)

2

BUFFER3 3

SPI BUS TO/FROM STATION MODULES

FLASH1M x 16

FLASH1M x 16

FLASH1M x 16

FLASH1M x 16

CS0CS1

MD[0:15]

MD[16:31]

MD[0:15]

MD[16:31]

16

16

16

16

16 16

16

16

MA[2:21]MA[2:21]

EEPROM32k x 8

MD[24:31]

MA[0:14]

CS4

P1_OUTLATCH

P0_OUTLATCH

MD[0:32]

MD[24:31]

P0_INBUFFER

MD[16,17,20-24,28-31]

STATUS BUSFROM

STATION MODULES

P0_IN

8

32

8

TRDSIPR(T

DIFFERENTIALTO SINGLE ENDRX1 SERIAL DATA

RDSIPR(R

1 PPS TIMING, CONTROL/ SLOT TIMING/RESET

16.8MHZ

SPIBUS

DIGITAL SIGNAL PROCESSING CIRCUITRY

DIFFERENTIALTO SINGLE END


50 MHZCLOCK

DRAM MEMORY

ETHERNET INTERFACE

NON-VOLATILE MEMORY EXPANDED STATUS INPUTAND OUTPUT CONTROL CIRCUITRY

EXTENDED HOSTBUS BUFFERS

40

RX2 SERIAL DATA

RX3 SERIAL DATA

HOST ADDRESS BUS

HOST DATA BUS

HOST BUFFERED DATA BUSHOST BUFFERED ADDRESS BUS

HOST-DSP BUFFERED DATA BUS

HOST-DSP BUFFERED ADDRESS BUS

SERIAL MANAGEMENT CONTROLLER (SMC2)

SERIAL PERIPHERAL INTERFACE

DATA CLOCK 2

DATA CLOCK 1

DATA CLOCK 3



2-55

SPIBUS

PHASEDETECTION/FILTERING

HIGHSTABILITYVCXO

48 MHZ

Z

REMOTE STATION

3.3V

P0_OUT SHUTDOWNCIRCUITRY

SHUTDOWN(TO POWERSUPPLY)

SHUTDOWN CIRCUITRY


STEARINGLINE

IT REFERENCE CIRCUITRY

1-Dec-06 68P80801E35-E

Figure 2-14 800 and 900 MHz QUAD Channel Base Radio Controller Functional Block Diagram (Sheet 1 of 2)

16.8MH

POWERSUPPLY

EXCITER/CONTROL

PA REF RX1 RX2 RX3 RX4 TX1 TX2 TX3 TX4

P0 OUT

LEDCONTROLLINESHOSTLATCH

12

FRONT PANEL LEDS


5MHZ_1PPSBASE RADIOINPUT

HIGHSTABILITYVCXO

PHASEDETECTION/FILTERING/CONTROL

STEARINGLINE

DISCONNECT/CONNECTCONTROL

GATING

SPIBUS

16.8 MHZ

STATION REFERENCE CIRCUITRY

TRANSM

5MHZ1PPS


1-Dec-06

CONTROL BUSTOSTATION MODULES

P0_OUT/P1_OUT

TRANSMITDIGITALSIGNALPROCESSOR(TX DSP)

SINGLE ENDTO DIFFERENTIAL

TRANSMITCLOCK ANDFRAME SYNCHCIRCUITRY

I/Q DATASERIAL DATATO EXCITER

RECEIVEDIGITALSIGNALPROCESSOR(RX DSP 1)

ECEIVEIGITALIGNALROCESSOR

RX DSP 2)

TISICA[0:5]

D[0, 8:23]

PARALLELTO SERIALCIRCUITRYD[16:23]

D[16:23]

D[0, 23]

SPI BUS TORECEIVER 1 & 2

SPI BUS TORECEIVER 3 & 4

2.4 MHz

1 PPS TIMING, CONTROL/ SLOT TIMING/RESET

NETWORKED

SCI

16.8MHZ

48 MHZ

SPIBUS

EXCITERSPICONTROL

DSP SPI

SPI BUSTO EXCITER


FRONT PANELRESET

TO EXCITER

5MHZ1PPS


2-56 68P80801E35-E

Figure 2-15 800 and 900 MHz QUAD Channel Base Radio Controller Functional Block Diagram (Sheet 2 of 2)

HOSTMICRO-

ETHERNETSERIAL

INTERFACETRANS-

CD

RCV RX

TRMT TX

CLSN

10BASE2COAX


CEIVERISOLATION

TRANSFORMER

PROCESSOR

SCC1

8

SDRAM4M x 16

SDRAM4M x 16

SDRAM4M x 16

SDRAM4M x 16

GPLA0, A[8,9,17,18,20:29],RAS,CAS,WE

CS2

CS3

D[0:31]

D[0:15]

D[16:31]

D[0:15]

D[16:31]

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

D[0:31]

D[0:7]

A[10:31]

MA[21:0]

DSP_D[31:24]

A[0:7]

DSP_A[31:24]

MD[31:0]

EIA-232BUSRECEIVERS/DRIVERS

2 STATUS PORT(9 PIN D CONNECTORON BRC FRONT PANEL)

2

BUFFER3 3

SPI BUS TO/FROM STATION MODULES

FLASH1M x 16

FLASH1M x 16

FLASH1M x 16

FLASH1M x 16

CS0CS1

MD[0:15]

MD[16:31]

MD[0:15]

MD[16:31]

16

16

16

16

16 16

16

16

MA[2:21]MA[2:21]

EEPROM32k x 8

MD[24:31]

MA[0:14]

CS4

P1_OUTLATCH

P0_OUTLATCH

MD[0:32]

MD[24:31]

P0_INBUFFER

MD[16,17,20-24,28-31]

STATUS BUSFROM

STATION MODULES

P0_IN

8

32

8

DIFFERENTIALTO SINGLE ENDRX1 SERIAL DATA

RDSP(

SPIBUS





50 MHZCLOCK

DRAM MEMORY

ETHERNET INTERFACE

NON-VOLATILE MEMORY EXPANDED STATUS INPUTAND OUTPUT CONTROL CIRCUITRY

EXTENDED HOSTBUS BUFFERS

40

RX2 SERIAL DATA

RX3 SERIAL DATA

RX4 SERIAL DATA

HOST ADDRESS BUS

HOST DATA BUS

HOST BUFFERED DATA BUSHOST BUFFERED ADDRESS BUS

HOST-DSP BUFFERED DATA BUS

HOST-DSP BUFFERED ADDRESS BUS



Chapter 3

Base Radio TransceiverIn This Chapter Topic See Page

Overview ...................................................................................... 3-2

QUAD+2 Channel Base Radio Transceiver ................................. 3-3


1-Dec-06 68P80801E35-E 3-1

Base Radio Transceiver Volume 2

Overview

Overview 3

This chapter provides information on the QUAD+2 Base Radio Transceiver (XCVR).


Base Radio Transceiver (XCVR) Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU contains the XCVR kit and required packaging. Table 3-1provides a cross reference between XCVR FRU numbers and kit numbers.


DescriptionFRU

NumberKit

Number

QUAD+2 Channel Base Radio Transceiver DLN6654 PCUF1001


3-2 68P80801E35-E 1-Dec-06

Volume 2 Base Radio Transceiver

QUAD+2 Channel Base Radio Transceiver

QUAD+2 Channel Base Radio Transceiver 3


The transceiver (XCVR) module provides the control, exciter and receiver functions for the Base Radio.

The XCVR generates the station reference which typically needs to be locked on the external 5 MHz reference from the site controller.

The XCVR SPI bus allows communication with its receiver and exciter circuitry, as well as the power supply and power amplifier modules.

The XCVR circuit board contains two major sections: XCVR Control: Performs the control management, digital signal

processing, and transmit and receive data formatting for the Base Radio. XCVR RF: Contains DC power conversion/regulation and performs

receiver and exciter functions.

Figure 3-1shows a top view of the Transceiver.

Figure 3-1 800/900 MHz QUAD+2 Channel Transceiver (Front View)


1-Dec-06 68P80801E35-E 3-3



Transceiver Control Section

The main operating software for the base radio is loaded in the XCVR’s control section. As the main manager for the base radio, the XCVR control provides operational control over the other station modules. It handles three types of information flow, in the following ways: Serves as a gateway between the network and RF functionality, by

distributing the RF payload to and from the network Supports operational and diagnostic functions with digital control data (for

example: site information, channel assignments, and identification numbers for call processing)

Ensures the flow of other network management configuration information

Figure 3-2 shows the information flow through the transceiver Control and RF sections.

Figure 3-2 800/900 MHz QUAD+2 Transceiver Information Flow

Transceiver RF Section

In addition to DC power conversion/regulation, the XCVR RF section provides circuitry for the following receiver and exciter functions.

Exciter

The exciter on the XCVR RF section provides the transmitter functions for the base radio. The exciter circuitry generates a low-level, modulated RF signal that passes to the power amplifier. It supports various modulation types as well as 1 to 6 transmit channels, through software programming.

The exciter also provides a controlled output power level to the power amplifier.

Ethernet viaSite Controller

Base Radio (XCVR)

ADC

DACP

DSPPA

RFDS

ControlRF

Host


3-4 68P80801E35-E 1-Dec-06



Receiver

The QUAD+2 receiver provides multiple receiver inputs for one to three diversity branches with multiple channels of up to six channels within each branch. The receiver is tuned to pass frequencies anywhere between 806 MHz and 901 MHz. The receiver is best suited for: Low density RF environments Stations with external multicouplers Stations with requirements for multi-frequency operation beyond 14 MHz

Controls and Indicators

The transceiver external interfaces include 2 external ports, a switch and LEDs. The ports and switch are described here. The LED states are listed in the reference section of the documentation. Figure 3-3 shows the port, switch and LED locations when the access door is opened. Figure 3-4 shows the Rear View connectors.

Figure 3-3 800/900 MHz QUAD+2 QUAD+2 Transceiver (with access door opened)

Ports

LEDs

Alarm LED

Reset Switch

Status LED


1-Dec-06 68P80801E35-E 3-5



Figure 3-4 800/900 MHz QUAD+2 Transceiver Backplane (Rear View)

Transceiver Ports - Front

Two ports are accessible via a dropdown door to the left of the fans. An asynchronous port and a synchronous port.

Transceiver Ports - Rear

The transceiver interconnects to the backplane using a 120–pin HVDML digital connector and 8–pack RF connector, as shown in Figure 3-4. These connections handle multiple signals including power, power supply communi-cations, power amplifier communications, 10Base2 Ethernet, fan interface and peripheral interface. The digital connection receives alarm data and the site controllers’ TDM signals, which are used to pass reference and control data to the station.

Transceiver Switch

There is one multifunction switch on the front of the transceiver module, accessible via the dropdown door to the left of the fans.

RF and Ethernet Digital

Table 3-2 Transceiver Connections

XCVR Port / Type

Connects to this Device/Port Description

RJ-45 10/100BaseT port Ethernet port for future use.

Service port, DB-9

Service PC, RS-232 port

Serial service port for configuration.


3-6 68P80801E35-E 1-Dec-06



Table 3-3 lists the Transceiver Front Switch Functions.

Transceiver LEDs

Table 3-4 and Table 3-5 lists the Transceiver LEDs.

Table 3-3 XCVR Front Switch Functions

User Action Result

Press switch for greater than 3 seconds Transceiver Control Module Reset

Table 3-4 QUAD+2 Channel Base Radio Status and Alarm LED Indications

Condition Status LED Alarm LED

No Power Off Off

Lamp Test Green Red

Failure Off Red

Impaired Green Red (blinking)

Booting Up Green (blinking) Off

Online Green Off

Table 3-5 QUAD+2 Channel Base Radio Transceiver LED Indications

Label LED State Description

1

Green Proper Base Radio operation with no alarm conditions and channel 1 is keyed

Green (Blinking) Channel 1 is not keyed

Off Channel 1 is not in operation or the Base Radio is out of service or power is removed

2





1-Dec-06 68P80801E35-E 3-7



Transceiver Band States

Table 3-6 lists the Transceiver Band States

3




4




5(See Note)




6(See Note)




Note Five and six carrier operation is only supported in Test Application mode and requires licensing agreement with Motorola for activation in Call Processing mode.

Table 3-5 QUAD+2 Channel Base Radio Transceiver LED Indications (continued)

Label LED State Description

Table 3-6 QUAD+2 Channel Base Radio Band State

Label LED State BR Band

7

Solid Red Install Band Failure

Solid Green 800 MHz

Solid Amber 900 MHz


3-8 68P80801E35-E 1-Dec-06



Theory of Operation - Controller Section

Table 3-7 briefly describes the BRC circuitry. Figure 3-5 shows the Controller with the cover removed. Figure 3-8 shows the Controller’s functional block diagram.

Table 3-7 Control Section Circuitry

Circuit Description

Host Microprocessor Contains integrated circuits that comprise the central controller of the BRC and station

Non-Volatile Memory

Consists of: • FLASH containing the station operating

software• Codeplug data

Volatile Memory Contains SDRAM to store station software used to execute commands.


RS-232 Interface Provides the BRC with an RS-232 serial interface

Digital Signal Processor Performs high-speed modulation/demodulation of compressed audio and signaling data

2QIC

Contains integrated circuits that provide:• Highly stable, reclocked transmit signals and

peripheral transmit control logic• Receive SPI capability for receive control,

metering ADC and signal path attenuators• Receive DSP functions including baseband

mixing and digital filtering for multiple branches with multiple channels with interleaved serialization of output

• Synthesizer for station reference and related control

• Site Reference timing decode and related Base Radio timing signals generation

• SPI interface to ADC devices for metering



Serial Peripheral Interface (SPI)

Provides serial control and metering capability with the exciter, receiver, power amplifier, and power supply.


1-Dec-06 68P80801E35-E 3-9



Figure 3-5 Controller Section (with housing removed)

Host Microprocessor

The host microprocessor is the main controller for the BR. The processor operates at a 266-MHz core clock speed. The processor controls Base Radio operation according to station software in memory. Station software resides in FLASH memory. For normal operation, the system transfers this software to volatile S-DRAM memory.Note At BR power-up and normal conditions, the Status and Alarm LEDs

transition through the Conditions stated in Table 3-4 as follows: Power Off, Failure, Lamp Test, Booting Up and Online states as indicated in Table 3-4. Any other sequence of Conditions indicates an impairment or failure.




3-10 68P80801E35-E 1-Dec-06




MPC8250 Host Processor

The MPC8250 microprocessor incorporates 16k bytes of instruction cache and 16k bytes of data cache that significantly enhance processor performance.

The microprocessor has a 32-line data bus. The processor uses this bus to access non-volatile memory and SDRAM memory. Via memory mapping, the processor also uses this bus to control other BRC circuitry.

The microprocessor uses its Chip Select capability to decode addresses and assert an output signal. The chip-select signals select non-volatile memory, SDRAM memory, and DSP.

The microprocessor has a Local Bus that is used to interface to the DSP.


other Base Radio devices and modules for control and metering of radio functions.

Provides RS-232 serial user interface Provides condition signals necessary to access SDRAM, FLASH, and

Compact Flash Accepts interrupt signals from BRC circuits (such as DSP and 2QIC). Organizes the interrupts, based on hardware-defined priority ranking. The Host supports several internal interrupts from its Communications


The Host supports 10/100 Mbps BaseT and 10Base2 Ethernet/IEEE 802.3 Provides a 32-line data bus transfers data to and from BRC SDRAM and

other BRC circuitry. Provides a Local Bus for communications with the DSP


1-Dec-06 68P80801E35-E 3-11



Non-Volatile Memory

Base Radio software resides in a minimum of 32M x 16 bits of Compact FLASH memory and 16M x 16 bits of additional board FLASH. The Host Microprocessor addresses the Compact FLASH memory with 4 of the host address bus’ 32 lines in conjunction with the data lines. The host accesses FLASH data over the 16-line host data bus. A host-operated chip-select line provides control signals for these transactions.

FLASH memory contains the operating system and application code. The system stores application code in Compact FLASH for fast recovery from reset conditions. Application code transfers from network or site controllers may occur in a background mode. Background mode transfers allow the station to remain operational during new code upgrades.

The data that determines the station personality (codeplug) resides in the 16M x 16 bit FLASH. The microprocessor addresses the FASH with 24 of the host address bus’ 32 lines. The host accesses FLASH data with 16 of the data bus’ 32 lines. A host-operated chip-select line provides control signals for these transactions.


Volatile Memory



Ethernet Interface


The LAN coprocessor supports all IEEE 802.3 Medium Access Control, including the following:


3-12 68P80801E35-E 1-Dec-06



framing preamble generation stripping source address generation destination address checking








(Jabber Timer)


The BRC includes one Digital Signal Processor for receive and transmit processing. This DSP and related circuitry process compressed station transmit and receive audio and data. The related circuitry includes the QUAD+2 Integrated Circuit (2QIC). The DSP only accepts input and output signals in digitized form.


1-Dec-06 68P80801E35-E 3-13



The DSP inputs are digitized receiver signals. The DSP outputs are digitized voice audio and data (modulation signals). These signals pass from the DSP to the Exciter section of the QUAD+2. DSP communicates with the Micropro-cessor via a 32-bit, host data bus on the host processor side. Interrupts drive communication between the DSP and the host.

The DSP operate from an external 49 MHz clock, provided by the CPLD and phase locked to the 16.8 MHz local station reference clock. The DSP internal core operating clock signal is 394MHz, produced by an internal Phase-Locked Loop (PLL).

The DSP accepts receive digitized signals from the 2QIC through the Time-Division Multiplexing (TDM) interface ports. The QUAD+2 uses 3 of these ports. All 3 ports use the same clock and framesync signals to input data. Each port handles digital data for 1 of the 3 branches. Each port handles digitized data for 6 channels, 2 status words, and 2 power detect words.

The QUAD+2 accesses its DSP program and signal-processing algorithms in 1440 kB of internal memory. The DSP communicates with the host bus over an 32-bit interface.

The DSP communicates with the 2QIC to provide serial communications to the receiver paths for receiver control over a Serial Peripheral Interface (SPI) link. The 2QIC provides a parallel-to-serial conversion circuit that accepts parallel data from the DSP and serial data to the receive circuitry.

The DSP sends up to six carriers of digitized signal to the 2QIC along with embedded control signals. Two framed and synchronized data streams are output. One data stream is I-data, and the other is the Q-data stream. The control bits are appended at the end of the data streams. The 2QIC extracts and applies the control signals. The 2QIC synchronizes the 2QIC I and Q output frames with system timing signals that exist in the 2QIC. The synchro-nized outputs are sent to a Digital to Analog Converter (DAC) in the exciter section that converts the digital signals to analog.

2QICplus

The 2QIC controls internal DSP operations. This circuit provides the following functions:

The 2QICplus is a DSP programmable FPGA that provides the circuit integration needed to condition, route and control receive and transmit data between the RF circuitry and the DSP, and provide consolidated monitoring and control for QUAD+2 transceiver. Following are the major functions of the 2QICplus For initialization and control, the 2QICplus interfaces with the DSP through

address and data buses. Provides six Independent Abacus III receiver data and control interfaces

with fault detection and handling


3-14 68P80801E35-E 1-Dec-06



Programmable General-Purpose Input/Output pins for monitor and control of the transceiver

Provides clocks required for the transceiver Phase detector for the 16.8MHz Synthesizer and PLL with PLL steering

line gate control Inputs a site reference signal, demodulates a 1PPS timing marker from this

signal and outputs the 1PPS signal for network timing alignment. 15 ms and 7.5 ms timing signals generation. (These signals are synchronize

to the 1 PPS time mark. The system decodes the time mark from the site reference. Then the system routes the reference to the DSP.)

Programmable Interrupt Controller for metering and status. Provides serial transmit data translation and transmit control and

synchronization to the network timing Complex Mixer capability to translate each of the six receive channels to

DC Polyphase 256 FIR filter with decimation by 10 for enhancing channel

selectivity Signal Energy detector for signal strength indication used for system signal

path attenuator control Provides output serializers to Time Division Multiplex information for six

channels two status values and two Energy Detection values for each branch


The Station Reference Circuitry is a phase-locked loop (PLL). This PLL consists of a high-stability, Voltage-Controlled, Crystal Oscillator (VCXO) and a PLL residing in the 2QICplus device. GPS output from the iSC connects to the 5 MHz/1 PPS BNC connector on the BR backplane. Wiring at this connector routes signals to QUAD+2 station reference circuitry.

The PLL compares the 5 MHz reference frequency to the 16.8 MHz VCXO output. Then the PLL generates a DC correction voltage. The PLL applies this correction voltage to the VCO through an analog gate. The analog gate closes when three conditions coexist: (1) The 5 MHz tests stable. (2) The 2QICplus PLL is programmed. (3) The PLL oscillator and reference signal output align-ments occur.

A loss of the 5 MHz/1PPS signal causes the control voltage enable switch to open. This permits the PLL to free run, which allows the BR to retain a clock for control purposes.



1-Dec-06 68P80801E35-E 3-15



The correction voltage from the PLL continuously adjusts the VXCO frequency. The VXCO outputs a 16.8 MHz clock signal. The circuit applies this clock signal to the receiver, transmitter, CPLD 49 MHz Digital Phase Lock circuitry and the 2QICplus.


Reset, Clock Generation, GPIO

The transceiver contains a reset and clock Combinational Programable Logic Device (CPLD). This circuitry provides reset and detection control, General Purpose Input and Output (GPIO), monitor interrupt registers with combined output indicator, and clock control and generation for the Base Radio. The reset functions include Power-on-Reset, front panel reset and internal resets of the transceiver and the output controls the Host, DSP, 2QIC and other BR circuitry. Clock control includes buffering of the Host processor clock and DSP clock generation that includes a PLL that is programable.

The GPIO provides control for the front panel LEDs and reset switch input, fan control output and failure detection input, and transmit power control input.

The interrupt feature includes two output signals that respond to GPIO inputs and the front panel reset. Masking of the interrupts is available.

Theory of Operation - Exciter and Receiver Section

The Exciter and the Receiver provide the transmitter functions of the QUAD+2 Channel 800/900 MHz Base Radio. The Exciter module consists of a printed circuit board, a slide in housing, and associated hardware. The BRC shares the printed circuit board and housing.

The Exciter connects to the Base Radio backplane through a 120-pin connector and one blindmate RF connector. Controller and exciter circuitry also interconnect on the Exciter/Controller module.

An LED identifies the Exciter’s operational condition, as described in the manual’s Controller section. The Base Radio section of the manual provides specifications for transmitter circuitry. This information includes data on the Exciter and Receiver.


3-16 68P80801E35-E 1-Dec-06



RF- Exciter Board Table 3-8 describes the basic circuitry of the Exciter. Figure 3-6 shows the Exciter with the housing removed. Figure 3-9 show the Exciter’s functional block diagram.

Table 3-8 Exciter Board Circuitry

Circuit Description

JAVELIN IC

• Up-converts baseband data to the transmit frequency

• Down-converts the PA feedback signal to baseband

• Uses a baseband Cartesian feedback loop system, necessary to obtain linearity from the transmitter and avoid splattering power into adjacent channels

• Performs training functions for proper linearization of the transmitter

Memory & A/D ConverterServes as the main interface between the synthesizer, JAVELIN IC, A/D, and EEPROM on the Exciter, and the BRC via the SPI bus

Frequency Synthesizer Circuitry

• Consists of a phase-locked loop and VCO• Provides an LO signal to the JAVELIN IC for

the up-conversion to the radio frequency signal and down-conversion of the feedback signal from the PA

800/900 MHz VCO Provides an LO signal to the JAVELIN IC, for up-conversion to the transmit frequency

Regulator Circuitry Provides a regulated voltage to various ICs and RF devices located on the Exciter

Linear RF amplifier Stages Amplifies the RF signal from the Exciter IC to an appropriate level for input to the PA


1-Dec-06 68P80801E35-E 3-17



Figure 3-6 Exciter Board (with housing removed)

Memory Circuitry

The memory circuitry is an EEPROM on the Controller portion of the Exciter/Controller module. The Controller performs memory read and write opera-tions over the parallel bus. The memory device stores the following data... kit number revision number module specific scaling and correction factors serial number free form information (scratch pad)

A/D Converter Circuitry

Analog signals from various areas throughout the Exciter board enter the A/D converter (A/DC). The A/DC converts these analog signals to digital form. Upon request of the Host Processor, A/DC output signals enter the Host Processor via SPI lines. The Controller periodically monitors all signals.

Some of the monitored signals include amplifier bias and synthesizer signals.


3-18 68P80801E35-E 1-Dec-06



JAVELIN IC Circuitry

The JAVELIN IC up converts the baseband I and Q signals from the D/A converter and low pass filters to the radio frequency signals.

The JAVELIN IC inputs the I and Q signals to a summing junction which adds the baseband transmitter feedback signal and feeds it to a low pass filter.

The output of the low pass filter feeds the baseband input to the transmit mixer. The other input to the transmit mixer is the output of the transmit VCO. This VCO operates at the radio frequency. The RF output of the transmit mixer is fed to the transmit RF amplifier chain.

A feedback signal from a coupler in the output of the PA is fed back into the JAVELIN IC and is down converted to baseband with a mixer that has the transmit VCO as it’s LO input. The feedback output of this mixer is used to linearize the PA signal to reduce power in the adjacent channels. The baseband feedback can be switched off to the summing junction during the PA training algorithm.

Synthesizer Circuitry

The synthesizer circuit consists of the Phase-Locked Loop (PLL) IC and associated circuitry. This circuit’s controls the Transmit VCO signal. An internal phase detector generates a logic pulse. This pulse is proportional to the phase or frequency difference between the reference frequency and the counted down VCO signal.

The charge pump circuit generates a correction signal. The correction signal moves up or down in response to phase detector output pulses. The correction signal passes through the low-pass loop filter. The signal then enters the Transmit Voltage Controlled Oscillator (VCO) circuit.

Transmit Voltage Controlled Oscillator (VCO)

For proper operation, the VCO requires a very low-noise, DC supply voltage. An ultra low-pass filter prepares the necessary low-noise voltage and drives the oscillator.

A portion of the oscillator output signal enters the synthesizer circuitry. The circuitry uses this feedback signal to generate correction pulses.

The Transmit VCO output mixes with the baseband I and Q signals in the JAVELIN IC. The JAVELIN IC uses this LO signal to up-convert to the programmed transmit frequency. The JAVELIN IC also uses the LO signal to down-convert the PA feedback signal.


1-Dec-06 68P80801E35-E 3-19



Regulator Circuitry

The voltage regulators generate three regulated voltages: +12 Vdc, +5 Vdc and +3.3 Vdc. The regulators obtain input voltages from the +29 Vdc backplane voltages. The regulated voltages power various ICs and RF devices in the Exciter.

Linear RF Amplifier Stages

The linear RF amplifiers boost the RF signal from the Low Noise IC. The RF Amplifier generates an appropriate signal level to drive the PA.

RF- Receiver Board Table 3-9 lists the Receiver circuitry. Figure 3-7 shows the Receiver Board with the housing removed. Figure 3-10 shows the Receiver’s functional block diagram.

Frequency Synthesizer and VCO Circuitry

The synthesizer and VCO circuitry generate the RF signal used to produce the 1st LO injection signal for the first mixer in all the Receiver front end circuits. Functional operation of these circuits involves a Phase-Locked Loop (PLL) and VCO.

Table 3-9 Receiver Circuitry

Circuit Description


Consists of a phase-locked loop and VCO. It generates the 1st LO injection signal for all six receivers.

Receiver Front-End Circuitry

Provides filtering, amplification, and the 1st down conversion of the receive RF signal. This block includes digital step attenuators at the 1st IF.

Custom Receiver IC Circuitry

Consists of a custom IC to perform the 2nd down conversion, filtering, amplification, and A/D conversion of the receive signal. This block outputs the receive signal as differential data to the FPGA and DSP.

Address Decode, A/D Converter, & Memory Circuitry

Performs address decoding for board and chip-select signals. Converts analog status signals to digital format for use by the BRC. A memory device holds module-specific information.

Local Power Supply Regulation

Accepts +29 VDC input from the backplane interconnect board. Also generates +12 VDC, a +5 VDC, and +3.3 VDC signals for the receiver.


3-20 68P80801E35-E 1-Dec-06



The PLL IC receives frequency selection data from the BRC module micro-processor. Once programmed, the PLL IC compares a counted down 16.8 MHz to 2.1 MHz, 2.4 MHz, or 2.25 MHz reference signal with a feedback sample of the VCO output from its feedback buffer.

The PLL ICC generates correction pulses, depending on whether the feedback signal is higher or lower in frequency than the 2.1 MHz, 2.4 MHz, or 2.25 MHz reference. The width of these pulses depends on the amount of difference between the 2.1 MHz, 2.4 MHz, or 2.25 MHz reference and the VCO feedback.

Figure 3-7 Receiver Board (with housing removed)

The up/down pulses enter a charge pump circuit. The charge pump outputs a DC voltage proportional to the pulse widths. After low-pass filtering, this DC voltage enters the VCO circuit as the control voltage. The control voltage measures between +1 VDC and +9 VDC.

The DC control voltage from the synthesizer enters the VCO. The VCO generates the RF signal that the circuit uses to produce the 1st LO injection signal. The VCO responds to the DC control voltage by generating the appro-priate RF signal. This signal passes through a buffer to the 1st LO injection amplifier. A sample of this signal returns to the PLL IC through a buffer to close the VCO feedback loop.


1-Dec-06 68P80801E35-E 3-21



Receiver Front End Circuitry

The station receive RF signal enters the Receiver through the RF-type connector on the back of the Receiver board. The circuit low-pass filters and amplifies this signal. The amplified output passes through an image filter before entering the 1st mixer. The signal mixes with the 1st LO injection signal to produce a 73.425 MHz +/- 75kHz 1st IF signal.

The 1st IF signal passes through a three-pole, bandpass filter and enters a buffer amplifier. The buffer amplifier output signal again undergoes three-pole, bandpass filtering. The resultant signal then passes through a digital attenuator. The BRC determines the amount of attenuation. The resulting signal then enters the RF input of the custom Receiver IC.


The custom Receiver IC provides additional amplification, filtering, and a second down-conversion. The IC converts the 2nd IF signal to a digital signal. The digital signal exits the receiver IC via differential driver circuitry, and passes to the 2QIC FPGA and Transceiver DSP. This data signal contains I and Q information, AGC information, and other data transfer information. The QUAD+2 uses this information to facilitate processing of the receive signal.

The remainder of the custom Receiver IC circuitry consists of timing and tank circuits. These circuits support the internal oscillator, 2nd LO synthesizer, and 2nd IF circuitry.

A SPI bus provides data communications between the custom Receiver IC and the 2QIC FPGA. The programming information from the FPGA controls the following receiver functions... control various current and gain settings establish the data bus clock rate program the 2nd LO perform other control functions

Decode Circuitry

Select/Enable lines from the Host Processor enable devices to RX A/D, synth for control or data communication purposes.

Memory Circuitry

The memory is shared with the Host Processor Non-Volatile Memory (NVM). Information stored in this memory device includes... the kit number revision number


3-22 68P80801E35-E 1-Dec-06



module specific scaling and correction factors free form module information (scratch pad)


Analog signals from various strategic operating points throughout the Receiver board pass through the A/D converter. These analog signals become a digital signal. Upon request of the Host Processor, this signal travels to the Host Processor via the SPI lines.

Voltage Regulator Circuitry

The voltage regulator circuitry consists of a +12 VDC, +5 VDC, and +3.3 VDC regulators. The +12 VDC, +5 VDC, and +3.3 VDC regulators accept the +29 VDC input from the backplane interconnect board. These regulators produce operating voltages for the Receiver circuitry.

The Hotswap circuit is included in the Power Supply section of the board. The +12 VDC regulator feeds a number of low dropout regulators. The LDO circuits provide finely regulated, low noise DC sources for VCOs and other sensitive receiver circuits.

QUAD+2 Channel Receiver Diversity Uses and Cautions

The QUAD+2 Channel BR Receiver board can be used in one, two, or three-branch diversity systems. The diversity parameter determines the number of active receivers. To view the diversity parameter, use the MMI command. (See software commands.) Each repeater’s configuration can be changed in the field to match the number of receivers connected to antennas. To change the diversity parameter, use the command (see software commands). For the iDEN system to work optimally, the diversity parameter must match the number of receivers connected to antennas.

CAUTIONImproperly setting the diversity parameter will cause serious system degradation.

Modifying Base Radios from Three Branch to Two Branch Diversity

When modifying a three-branch Base Radio to a two-branch Base Radio, observing all precautionary statements in the previous paragraph is important.

To modify a three-branch Base Radio to a two-branch Base Radio:

1. Disconnect the RF cable from the RX3 connector on the Base Radio.


1-Dec-06 68P80801E35-E 3-23



2. Connect an SMA male load (Motorola part number 5882106P03) to the RX3 connector on the Base Radio.

The SMA male load is required to limit the amount of radiated emissions.

3. Verify that the diversity parameter is set properly, according to the Diversity Uses and Caution paragraph above.

Modifying Base Radios from Two Branch to Three Branch Diversity

1. Remove the SMA male load from the RX3 connector of the Base Radio that you wish to convert from two-branch diversity to three-branch diversity.

2. Connect the Receive Antenna #3 RF cable to the RX3 connector on the Base Radio.

3. Verify that the diversity parameter is set properly, according to the Diversity Uses and Cautions paragraph.


3-24 68P80801E35-E 1-Dec-06



3-25

TX SERIAL DATATO EXCITER

RX1A SERIAL DATA

25.6MHz

L PROCESSING UITRY

TO EXCITER

RX21B SERIAL DATARX2A SERIAL DATARX2B SERIAL DATARX2A SERIAL DATARX2B SERIAL DATA

RX1A SPI BUSRX1B SPI BUSRX2A SPI BUSRX2B SPI BUSRX2A SPI BUSRX2B SPI BUS

RX AGC BUS

RX SYNCB

TDM3

TDM[0:2]

60x

RX CLK, FS, DATA[0;2]

TX DSP_CLK&FS

TX_DSP_Data[0:1]

RCVR

Intf.

Station RefPLL

16.8MHzOSC MUX

Chrg PmpTO

Tx Intf.

Phase_Det_d,u

16o8_FreeRun

CK_FS, CK_HS, IRQ1*,IRQ2*

Ext_Ref_In

Sel_1PPS ClockGen

GPIO Power Control_0,1,2,3

16.8MHZ

Reset Signals

2QIC

VCOCIRCUITRY

(5MHz_1PPS)

BNCBACKPLANE

16.8MHZTO EXCITER

16.8MHZTO RECEIVER

1-Dec-06 68P80801E35-E

Figure 3-8 QUAD+2 Control Section Functional Block Diagram

HOSTMICRO-

ETHERNETSERIAL

INTERFACETRANS-

CD

RCV RX

TRMT TX

CLSN

10BASE2COAX


CEIVERISOLATION

TRANSFORMER

PROCESSOR

SCC1

8

SDRAM32M x 16

SDRAM32M x 16

DA10,SEL[1:2],DDQM[1:3],

CS3

D[0:15] D16:31]

EIA-232BUSRECEIVERS/DRIVERS &

3 STATUS PORT(9 PIN D CONNECTORON BRC FRONT PANEL)

2

BUFFER &15

6

BOOT

16M x 16

COMPACT

32M x 16

CS1CS0

MD[0:15]

MD[0:15]

MA[21, 28:30]MA[7:30]

SPI BUSTO EXCITER

DIGITAL SIGNACIRC

66 MHZCLOCK

SDRAM MEMORY

ETHERNET INTERFACE

NON-VOLATILE MEMORY

HOST 60X ADDRESS BUS



FLASHFLASH

HOST 60X DATA BUS

MODULE

A[17,18,20:29],RAS,CAS,WE

LEDS & SW1

CPLDReset

HI Bus

MII

GPIO, LEDsRaw_1PPS

Power Control_0,1,2,3IRQ

UART

49.0 MHz

Clk_66MHz

16.8MHZ

External Trigger In

External Trigger Out

10/100BaseT

Local Bus

10/100 Base TETHERNET &

FRONT

FRONT PANEL

Reset Signals

Reset Signals

Reset Signals

PANEL

FRONT PANELRJ-45

6

78

CONTROL5 SPI BUS

TO RECEIVER9 SPI BUS TO BACKPLANE

POWER SUPPLY & POWER AMPLIFIER

CONTROLADC

4

CONTROL2

CONTROL

Hlt_1PPS*

DB9

INDICATORS& SWITCH

METERING


1-Dec-06

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3-26 68P80801E35-E

Figure 3-9 QUAD+2 Exciter Functional Block Diagram

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1-Dec-06 68P80801E35-E

Figure 3-10 QUAD+2 Receiver Board Functional Block Diagram

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3-28 68P80801E35-E

N O T E S . . .

Chapter 4

Base Radio Exciter


Overview ...................................................................................... 4-2

800 Legacy MHz Exciter – TLN3337 ............................................ 4-3

Low Noise 800 MHz Exciter ......................................................... 4-8




1-Dec-06 68P80801E35-E 4-1

Base Radio Exciter Volume 2

Overview

Overview 4

This chapter provides technical information for the Exciter (EX).


Exciter Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU contains the Exciter kit and required packaging. Table 4-1 provides a cross reference between Exciter FRU numbers and kit numbers.


DescriptionFRU

NumberKit

Number

Single Channel Exciter (800 MHz) TLN3337 CLF1490

QUAD Channel 900 MHz Exciter/Base Radio Controller)

CLN1497 CLF6452

QUAD Channel 800 MHz Exciter/Base Radio Controller

CLN1497 CLF1560

LNODCT (Low Noise Offset Direct Conversion Transmit) Exciter (800 MHz)

TLN3337 CLF1789


4-2 68P80801E35-E 1-Dec-06

Volume 2 Base Radio Exciter

800 Legacy MHz Exciter – TLN3337

800 Legacy MHz Exciter – TLN3337 4

800 MHz Exciter Overview

The Exciter, in conjunction with the Power Amplifier (PA), provides the trans-mitter functions for the Base Radio. The Exciter module consists of a printed circuit board, a slide in housing, and associated hardware.

The Exciter interconnects to the Base Radio backplane using a 96-pin DIN connector and two blindmate RF connectors. Two Torx screws on the front of the Exciter hold it in the chassis.

There are no controls or indicators on the Exciter. Specifications of the trans-mitter circuitry, including the Exciter and PAs, are provided in the Base Radio section of the manual.

Figures 4-1 shows the Exciter with the cover removed.

Figure 4-1 800 MHz Exciter (with cover removed)


1-Dec-06 68P80801E35-E 4-3



800 MHz Exciter Theory of Operation

Table 4-2 lists and describes the basic circuitry of the Exciter. Figure 4-5 shows the functional block diagram of the Exciter.

Table 4-2 Exciter Circuitry

Circuit Description

Tranlin IC

Performs the following functions:up-converts the baseband data to the first IFdown-converts the IF feedback signal to basebanduses a baseband Cartesian feedback loop system, necessary to obtain linearity from the transmitter and avoid splattering power into adjacent channelsperforms training functions for proper linearization of the transmitter

Exciter IC

Interfaces with Tranlin IC to perform:up-conversion from first IF to the transmit operating frequencydown-conversion to IF of PA output feedback signal for input to Tranlin IC

Address Decode, Memory, & A/D Converter

Serves as the main interface between the synthesizer, Tranlin IC, A/D, and EEPROM on the Exciter and the BRC via the SPI bus


Consists of a phase-locked loop and VCO to provide a LO signal to the Exciter IC for the second up-conversion and for the first down-conversion of the feedback signal from the PA

970 MHz VCO (800 MHz BR)

Provides a LO signal to the Exciter IC for the second up-conversion to the transmit frequency


Provides a LO signal to Tranlin IC for the first up-conversion and for the second down-conversion of the feedback signal. The synthesizer and divide by 2 circuitry within the Tranlin IC set the first IF to 118.5 MHz

Regulator CircuitryProvides a regulated voltage to various ICs and RF devices located on the Exciter

Linear RF amplifier StagesAmplifies the RF signal from the Exciter IC to an appropriate level for input to the PA

Automatic Gain Control (AGC)

provides automatic gain control of the transmitter (Exciter and Power Amplifier modules) to maintain a level forward gain of the RF amplifier stages.


4-4 68P80801E35-E 1-Dec-06



Address Decode Circuitry

The address decode circuitry enables the BRC to use the address bus to control Exciter circuitry. The BRC can select a specific device on the Exciter via the SPI bus for control or data communication purposes.

If the board select circuitry decodes address lines A2 through A5 as the Exciter address, it enables the chip select circuitry. The chip select circuitry then decodes address lines A0 and A1 to generate the chip select signals for the EEPROM, A/D converter, Tranlin IC, and PLL IC. Once selected, the BRC uses the SPI bus to send and receive data to and from the device.

Memory Circuitry

The memory circuitry consists of an EEPROM located on the Exciter. The BRC performs all memory read and write operations via the SPI bus. Infor-mation stored in this memory device includes the kit number, revision number, module specific scaling and correction factors, and free form infor-mation (scratch pad).


Analog signals from various areas throughout the Exciter board are fed to the A/D converter. These analog signals are converted to a digital signal and are output to the BRC via the SPI lines upon request of the BRC. All signals are periodically monitored and controlled by the BRC.

Some of the signals monitored include the regulated voltages, the external wattmeter (optional), the PLL circuit, and other internal signals.

Tranlin IC Circuitry

The Tranlin IC is a main interface between the Exciter and BRC. Digitized signals (baseband data) are sent via the DSP data bus from the Digital Signal Processors (DSP) of the BRC to the Exciter. These data signals are clocked via the DSP clock signal provided by the Receiver.

The differential data clock signal also serves as a 4.8 MHz reference signal to the internal synthesizer circuit of the Tranlin IC. The Tranlin compares the reference signal with the output of the 237 MHz Voltage Controlled Oscillator (VCO). If the VCO output is out of phase or differs in frequency, correction pulses are sent to the Oscillator and the VCO output is adjusted.

The Tranlin IC up-converts the baseband data received from the BRC to the first IF of 118.5 MHz. It also down-converts an IF feedback signal from the Exciter IC to baseband data for summing.


1-Dec-06 68P80801E35-E 4-5



The Serial Peripheral Interface (SPI) bus is used to communicate with the Tranlin IC. The SPI bus serves as a general purpose bi-directional serial link between the BRC and other modules of the Base Radio, including the Exciter. The SPI bus is used to send control and operational data signals to and from the various circuits of the Exciter.

Exciter IC Circuitry

The Exciter IC interfaces directly with the Tranlin IC to perform up-conversion from the first IF to the programmed transmit operating frequency. The first IF signal is passed through a band-pass filter before it reaches the Exciter IC.

The Exciter IC also down-converts the RF feedback signal from the PA to its IF signal. The IF signal is then input to the Tranlin IC for conversion to baseband data that computes the Cartesian feedback.


The synthesizer circuitry consists of the Phase-Locked Loop (PLL) IC and associated circuitry. The output of this circuit is combined with the 970 MHz VCO to supply a Local Oscillator (LO) signal to the Exciter IC for the second up-conversion of the programmed transmit frequency. This signal is also used for the first down-conversion of the feedback signal from the PA.

An internal phase detector generates a logic pulse in proportion to the difference in phase or frequency between the reference frequency and loop pulse signal.

If the reference frequency is faster than the VCO feedback frequency, an up signal is output from the PLL IC. If the reference frequency is slower than the VCO feedback frequency, a down signal is output from the PLL IC. These pulses are used as correction signals and are fed to a charge pump circuit.

The charge pump circuit consists of five transistors and its associated biasing components. This circuit generates the correction signal and causes it to move up or down in response to the phase detector output pulses. The correction signal is passed through the low-pass loop filter to the 970 MHz Voltage Controlled Oscillator (VCO) circuit.

970 MHz Voltage Controlled Oscillator (VCO)

The 970 MHz VCO generates the second injection frequency for the Exciter IC.

The VCO requires a very low-noise DC supply voltage of +10 VDC for proper operation. The oscillator is driven by a Super Filter that contains an ultra low-pass filter. The Super Filter obtains the required low-noise output voltage for the oscillator.


4-6 68P80801E35-E 1-Dec-06



The output of the oscillator is tapped and sent to the VCO Feedback Filter. This feedback signal is supplied to the Synthesizer circuitry for the generation of correction pulses.

The untapped output of the 970 MHz VCO is sent to the second LO injection circuitry.


The 237 MHz VCO provides a LO signal to Tranlin IC for the first up-conversion and for the second down-conversion of the feedback signal. The synthesizer and divide by 2 circuitry within the Tranlin IC set the first IF to 118.5 MHz.

Regulator Circuity

This circuit generates three regulated voltages of +5 VDC, +10 VDC, and +11.8 VDC. All voltages are obtained from the +14.2 VDC backplane voltage. These voltages are used to power various ICs and RF devices of the Exciter.


This circuitry is used to amplify the RF signal from the Exciter IC to an appropriate level for input to the PA.


1-Dec-06 68P80801E35-E 4-7


Low Noise 800 MHz Exciter

Low Noise 800 MHz Exciter 4

LNODCT (Low Noise Offset Direct Conversion Transmit) 800 MHz Exciter Overview

The Low Noise Exciter and the Power Amplifier (PA) provide the transmitter functions of the Generation 2 Base Radio. The Low Noise Exciter module consists of a printed circuit board, a slide in housing, and associated hardware.

The Low Noise Exciter connects to the Base Radio backplane through a 96-pin DIN connector and two blindmate RF connectors. Two Torx screws on the front of the Exciter secure it to the chassis.

There are no controls or indicators on the Exciter. Specifications of the trans-mitter circuitry, including the Exciter and PAs, are provided in the Base Radio section of the manual.

Figure 4-2 shows the Exciter with the cover removed.

Figure 4-2 Low Noise 800 MHz Exciter (with cover removed)


4-8 68P80801E35-E 1-Dec-06



Low Noise Exciter Theory of Operation

Table 4-3 describes the basic circuitry of the Low Noise Exciter. Figure 4-6 show the Low Noise Exciter’s functional block diagram.

Memory Circuitry

The memory circuitry is loaded on an EEPROM on the Exciter. The EBRC performs memory read and write operations via the SPI bus. Information stored in this memory device includes the kit number, revision number, module-specific scaling, and correction factors, operations, parameters, and free-form information (scratch pad) kit number


Circuit Description

Low Noise IC

Up-converts baseband data to the transmit frequencyDown-converts the PA feedback signal to basebandUses a baseband Cartesian feedback loop system, necessary to obtain linearity from the transmitter and avoid splattering power into adjacent channelsPerforms training functions for proper linearization of the transmitter

Memory & A/D ConverterServes as the main interface between the synthesizer, Tranlin IC, A/D, and EEPROM on the Exciter, and the BRC via the SPI bus


Consists of a phase-locked loop and VCOProvides a LO signal to the Low Noise IC for the second up-conversion and first down-conversion of the feedback signal from the PA


Provides a LO signal to the Low Noise IC, for up-conversion to the transmit frequency

90.3 MHz VCO (800 MHz BR)

Provides a LO signal to Low Noise IC, for the up-conversion and for the down-conversion of the feedback signal. The mixed output becomes the LO signal for Transmit signal up- and down- conversion




1-Dec-06 68P80801E35-E 4-9




Analog signals from various areas throughout the Exciter board enter the A/D converter (A/DC). The A/DC converts these analog signals to digital form. Upon request of the BRC, A/DC output signals enter the BRC via SPI lines. The Controller periodically monitors all signals.


LNODCT IC Circuitry

The LNODCT IC (Low Noise Offset Direct Conversion Transmit IC) is a main interface between the Exciter and BRC. The BRC’s Digital Signal Processor (DSP) sends digitized signals (baseband data) to the Exciter over the DSP data bus.

The differential data clock signal serves as a 2.4 MHz reference signal to the LNODCT IC’s internal synthesizer. The LNODCT compares the reference signal with the outputs of Voltage Controlled Oscillators (VCOs). The LNODCT might sense that a VCO’s output is out of phase or off-frequency. If so, then the LNODCT sends correction pulses to the VCO. The pulses adjust VCO output, thereby matching phase and frequency with the reference.

The LNODCT IC up-converts baseband data from the EBRC to the transmit frequency. The LNODCT IC also down-converts the Transmit signal from the Power Amplifier to baseband data for cartesian feedback linearization.

The EBRC uses the Serial Peripheral Interface (SPI) bus to communicate with the LNODCT IC. The SPI bus serves as a general purpose, bi-directional, serial link between the EBRC and other Base Radio modules, including the Exciter. The SPI carries control and operational data signals to and from Exciter circuits.


The synthesizer circuit consists of the Phase-Locked Loop (PLL) IC and associated circuitry. This circuit’s controls the 970 MHz VCO signal. An internal phase detector generates a logic pulse. This pulse is proportional to the phase or frequency difference between the reference frequency and loop pulse signal.

The charge pump circuit generates a correction signal. The correction signal moves up or down in response to phase detector output pulses. The correction signal passes through the low-pass loop filter. The signal then enters the 970 MHz Voltage Controlled Oscillator (VCO) circuit.


4-10 68P80801E35-E 1-Dec-06






The 970 MHz VCO output mixes with the 90.3 MHz VCO output. The result is a Local Oscillator [LO) signal for the LNODCT IC. The LNODCT uses this LO signal to up-convert the programmed transmit frequency. The LNODCT also uses the LO signal to down-convert the PA feedback signal.

90.3 MHz Voltage Controlled Oscillator (VCO)

The synthesizer within the LNODCT IC sets the 90.3 MHz signal. The 90.3 MHz VCO provides a LO signal to the LNODCT IC. The LNODCT uses this signal in up-converting and down-converting the feedback signal.

Regulator Circuitry

The voltage regulators generate three regulated voltages: +3 Vdc, +5 Vdc and +11.7 Vdc. The regulators obtain input voltages from the +3.3 Vdc and +14.2 Vdc backplane voltages. The regulated voltages power various ICs and RF devices in the Exciter.


The linear RF amplifiers boost the RF signal from the LNODCT IC. The RF Amplifier generates an appropriate signal level to drive the PA.


1-Dec-06 68P80801E35-E 4-11


QUAD Channel 900 MHz Exciter

QUAD Channel 900 MHz Exciter 4

QUAD Channel 900 MHz Exciter Overview

The Exciter and the Power Amplifier (PA) provide the transmitter functions of the QUAD Channel 900 MHz Base Radio. The Exciter module consists of a printed circuit board, a slide in housing, and associated hardware. The BRC shares the printed circuit board and housing.

The Exciter connects to the Base Radio backplane through a 168-pin connector and two blindmate RF connectors. Controller and exciter circuitry also interconnect on the Exciter/Controller module. Two Torx screws on the front of the Exciter secure it to the chassis.

An LED identifies the Exciter’s operational condition, as described in the manual’s Controller section. The Base Radio section of the manual provides specifications for transmitter circuitry. This information includes data on the Exciter and PAs.


Figure 4-3 900 MHz QUAD Channel Exciter (with cover removed)


4-12 68P80801E35-E 1-Dec-06



900 MHz QUAD Channel Exciter Theory of Operation

Table 4-4 describes the basic circuitry of the Exciter. Figure 4-7 show the QUAD Carrier Exciter’s functional block diagram.

Table 4-4 900 MHz Exciter Circuitry

Circuit Description

LNODCT IC




Consists of a phase-locked loop and VCOProvides a LO signal to the LNODCT IC for the second up-conversion and first down-conversion of the feedback signal from the PA


Provides a LO signal to the LNODCT IC, for up-conversion to the transmit frequency


Provides a LO signal to LNODCT IC, for the up-conversion and for the down-conversion of the feedback signal. The mixed output becomes the LO signal for Transmit signal up- and down- conversion




1-Dec-06 68P80801E35-E 4-13



Memory Circuitry





Low Noise Offset Direct Conversion Transmit (LNODCT) IC Circuitry

The Low Noise IC is a main interface between the Exciter and BRC. The BRC’s Digital Signal Processor (DSP) sends digitized signals (baseband data) to the Exciter over the DSP data bus.

The differential data clock signal serves as a 2.4 MHz reference signal to the Low Noise IC’s internal synthesizer. The Low Noise IC compares the reference signal with the outputs of Voltage Controlled Oscillators (VCOs). The Low Noise IC might sense that a VCO’s output is out of phase or off-frequency. If so, then the Low Noise IC sends correction pulses to the VCO. The pulses adjust VCO output, thereby matching phase and frequency with the reference.

The Low Noise IC up-converts baseband data from the BRC to the transmit frequency. The Low Noise IC also down-converts the Transmit signal from the Power Amplifier to baseband data for cartesian feedback linearization.

The BRC uses the Serial Peripheral Interface (SPI) bus to communicate with the Low Noise IC. The SPI bus serves as a general purpose, bi-directional, serial link between the BRC and other Base Radio modules, including the Exciter. The SPI carries control and operational data signals to and from Exciter circuits.


4-14 68P80801E35-E 1-Dec-06









The 1025MHz VCO output mixes with the 90.3 MHz VCO output. The result is a Local Oscillator [LO) signal for the Low Noise IC. The LNODCT uses this LO signal to up-convert the programmed transmit frequency. The Low Noise IC also uses the LO signal to down-convert the PA feedback signal.


The synthesizer within the Low Noise IC sets the 90.3 MHz signal. The 90.3 MHz VCO provides a LO signal to the LNODCT IC. The Low Noise IC uses this signal in up-converting and down-converting the feedback signal.

Regulator Circuitry





1-Dec-06 68P80801E35-E 4-15



QUAD Channel 800 MHz Exciter 4

QUAD Channel 800 MHz Exciter Overview

The Exciter and the Power Amplifier (PA) provide the transmitter functions of the QUAD Channel Base Radio. The Exciter module consists of a printed circuit board, a slide in housing, and associated hardware. The BRC shares the printed circuit board and housing.

The Exciter connects to the Base Radio backplane through a 168-pin connector and two blindmate RF connectors. Controller and exciter circuitry also interconnect on the Exciter/Controller module. Two Torx screws on the front of the Exciter secure it to the chassis.

An LED identifies the Exciter’s operational condition, as described in the manual’s Controller section. The Base Radio section of the manual provides specifications for transmitter circuitry. This information includes data on the Exciter and PAs.


Figure 4-4 800 MHz QUAD Channel Exciter (with cover removed)


4-16 68P80801E35-E 1-Dec-06



QUAD Channel 800 MHz Exciter Theory of Operation

Table 4-5 describes the basic circuitry of the Exciter. Figure 4-7 show the QUAD Carrier Exciter’s functional block diagram.


Circuit Description

LNODCT IC




Consists of a phase-locked loop and VCOProvides a LO signal to the LNODCT IC for the second up-conversion and first down-conversion of the feedback signal from the PA


Provides a LO signal to the LNODCT IC, for up-conversion to the transmit frequency


Provides a LO signal to LNODCT IC, for the up-conversion and for the down-conversion of the feedback signal. The mixed output becomes the LO signal for Transmit signal up- and down- conversion




1-Dec-06 68P80801E35-E 4-17



Memory Circuitry





Low Noise Offset Direct Conversion Transmit (LNODCT) IC Circuitry

The Low Noise IC is a main interface between the Exciter and BRC. The BRC’s Digital Signal Processor (DSP) sends digitized signals (baseband data) to the Exciter over the DSP data bus.

The differential data clock signal serves as a 2.4 MHz reference signal to the Low Noise IC’s internal synthesizer. The Low Noise IC compares the reference signal with the outputs of Voltage Controlled Oscillators (VCOs). The Low Noise IC might sense that a VCO’s output is out of phase or off-frequency. If so, then the Low Noise IC sends correction pulses to the VCO. The pulses adjust VCO output, thereby matching phase and frequency with the reference.

The Low Noise IC up-converts baseband data from the BRC to the transmit frequency. The Low Noise IC also down-converts the Transmit signal from the Power Amplifier to baseband data for cartesian feedback linearization.

The BRC uses the Serial Peripheral Interface (SPI) bus to communicate with the Low Noise IC. The SPI bus serves as a general purpose, bi-directional, serial link between the BRC and other Base Radio modules, including the Exciter. The SPI carries control and operational data signals to and from Exciter circuits.


4-18 68P80801E35-E 1-Dec-06









The 970 MHz VCO output mixes with the 90.3 MHz VCO output. The result is a Local Oscillator [LO) signal for the Low Noise IC. The LNODCT uses this LO signal to up-convert the programmed transmit frequency. The Low Noise IC also uses the LO signal to down-convert the PA feedback signal.


The synthesizer within the Low Noise IC sets the 90.3 MHz signal. The 90.3 MHz VCO provides a LO signal to the LNODCT IC. The Low Noise IC uses this signal in up-converting and down-converting the feedback signal.

Regulator Circuitry





1-Dec-06 68P80801E35-E 4-19



N O T E S . . .


4-20 68P80801E35-E 1-Dec-06



4-21

970 MHZVCO CIRCUITRY

SYNTHESIZERCIRCUITRY

SUPERFILTER

+10 V

CONTROL VOLTAGE(+2.5 TO +7.5 VDC)

OSCILLATOR

CHARGEPUMP

2.1 MHZ

VCO FEEDBACK

CHIPSELECT

SPI BUS (CLOCK & DATA)FROM BACKPLANE

PHASELOCKED

LOOPICRIN

FIN

LOW-PASSLOOP

FILTERBUFFER

VCOFEEDBACK

FILTER

BUFFERAMP

BPF

0 VRCE

.8 VRCE

ALOGSOURCE

EBTS283101597JNM

1-Dec-06 68P80801E35-E

Figure 4-5 Legacy Exciter Functional Block Diagram

DIFFERENTIAL

DATA & CLOCKFROM

BRC MODULE

ADDRESS BUSFROM CONTROL

MODULE

SPI BUSTO/FROM CONTROL

MODULE

ADDRESS DECODE, MEMORY, & A/DCONVERTER CIRCUITRY

EXCITER IC CIRCUITRY

LINEAR RF AMPLIFIERCIRCUITRY

2ND LOINJECTIONCIRCUITRY

MEMORY

A/DCONVERTER

CHIP SELECTDECODE

CIRCUITRY

BOARD SELECTDECODE

CIRCUITRY

VARIOUSSIGNALS

TO MONITOR

CHIPSELECT

237 MHZVCO

CIRCUITRY

OSCILLATOR

BUFFERAMP

TRANLIN IC CIRCUITRY

EXCITER IC

BPFTISIC DATA & CLOCK

1ST LOINJECTIONCIRCUITRY

RF OUTPUTTO PA MODULE

TRANLIN IC

IFOUT

IFIN

RF FEEDBACKFROM PA MODULE

REGULATORCIRCUITRY

+11.8 VREGULATOR

+14.2 VFROM

BACKPLANE

+1SOU

+11SOU

AN+5 V

+5 VREGULATOR

+10 VREGULATOR

(U3702)


1-Dec-06



DCFILTER

+10 V

CONTROL VOLTAGEOSCILLATOR

CHARGEPUMP

2.4 MHZ

VCO FEEDBACK

CHIPSELECT


PHASELOCKED

LOOPICRIN

FIN

LOW-PASSLOOP

FILTERBUFFER

VCOFEEDBACK

BUFFERAMP

BPF

VRCE

.7 VRCE

5 VRCE

EBTS283LN080601JNM


4-22 68P80801E35-E

Figure 4-6 Low Noise Exciter Functional Block Diagram

DIFFERENTIAL

DATA & CLOCKFROM

BRC MODULE


MODULE


MODULE




LOINJECTIONCIRCUITRY

MEMORY

A/DCONVERTER

VARIOUSSIGNALS

TO MONITOR

90.3VCO

CIRCUITRY

OSCILLATOR

BUFFERAMP

LNODCT IC CIRCUITRY

LNODCT IC


DAC

I

Q


REGULATORCIRCUITRY

+11.7 VREGULATOR

+14.2 VFROM

BACKPLANE

+3SOU

+11SOU

+SOU

+5 VREGULATOR

+3 VREGULATOR

(U3702)

NOTE: Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.

+5.0 V FROM BACKPLANE

PLD



4-23



DCFILTER

+10 V

CONTROL VOLTAGEOSCILLATOR

CHARGEPUMP

2.4 MHZ

VCO FEEDBACK

CHIPSELECT


PHASELOCKED

LOOPICRIN

FIN

LOW-PASSLOOP

FILTERBUFFER

VCOFEEDBACK

BUFFERAMP

BPF

3 VRCE

.7 VRCE

5 VRCE

EBTS283Q080601JNM

1-Dec-06 68P80801E35-E

Figure 4-7 800 and 900 MHz Exciter Board Functional Block Diagram

DIFFERENTIAL

DATA & CLOCKFROM

BRC MODULE


MODULE


MODULE




LOINJECTIONCIRCUITRY

MEMORY

A/DCONVERTER

VARIOUSSIGNALS

TO MONITOR

90.3VCO

CIRCUITRY

OSCILLATOR

BUFFERAMP

LNODCT IC CIRCUITRY

LNODCT IC

TX DATA & CLOCK


DAC

I

Q


REGULATORCIRCUITRY

+11.7 VREGULATOR

+14.2 VFROM

BACKPLANE

+SOU

+11SOU

+SOU

+5 VREGULATOR

+3 VREGULATOR

(U3702)

NOTE: Where two frequencies are given, frequency without parentheses applies to 800 MHz BR only and frequency with parentheses applies to 900 MHz BR only.

+3.3 V


1-Dec-06


4-24 68P80801E35-E

N O T E S . . .

Chapter 5

Power Amplifier


Overview ...................................................................................... 5-2

Power Amplifier Overview ............................................................ 5-3

PA Theory of Operation ............................................................... 5-7


1-Dec-06 68P80801E35-E 5-1

Power Amplifier Volume 2

Overview

Overview 5

This section provides technical information for the Power Amplifier (PA).


Power Amplifier (PA) Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU contains the PA kit and required packaging. Table 5-1 provides a cross reference between PA FRU numbers and kit numbers.


DescriptionFRU

NumberKit

Number

40 W- 800 MHz Single Channel Base Radio PA TLF2020 CLF1772

70 W- 800 MHz Single Channel Base Radio PA TLN3335 CLF1771

52 W- 900 MHz QUAD Channel Base Radio PA DLN1202 CTF1082

52 W- 800 MHz QUAD Channel Base Radio PA CLF1499 CLF1400

QUAD+2 Channel Base Radio PA DLN6655 CLF1835


5-2 68P80801E35-E 1-Dec-06

Volume 2 Power Amplifier

Power Amplifier Overview

Power Amplifier Overview 5

Note The power outputs discussed on this section for the 800 MHz QUAD and 900 MHz QUAD Power Amplifiers are referenced to the single carrier mode, operating at 52 W average power output from the Power Amplifier’s output connector.

General Specifications of the transmitter circuitry, including the Exciter and PAs, are provided in Base Radio Overview section. Figure 5-1 shows the 40W, 800 MHz PA. Figure 5-2 shows the 70W, 800 MHz PA. Figure 5-3 shows the 800 MHz QUAD PA (the 900 MHz QUAD PA is similar in appearance). Figure 5-4 shows the QUAD+2 PA.

40W-800 MHz, 70W-800 MHz, 800 MHz QUAD and 900 MHz QUAD

The Power Amplifier (PA), with the Exciter, provides the transmitter functions for the Base Radio. The PA accepts the low-level modulated RF signal from the Exciter. The PA then amplifies the signal for transmission and distributes the signal through the RF output connector.

The 800 MHz Base Radio can be equipped with either 40 Watt PA, TLF2020 (version CLF1771) or 70 Watt PA, TLN3335 (version CLF1772). The 40W PA module consists of five hybrid modules, four pc boards, and a module heatsink/housing assembly. The 70W PA module consists of eight hybrid modules, four pc boards, and a module heatsink/housing assembly.

The PA connects to the chassis backplane through a 96-pin DIN connector and three blindmate RF connectors. Two Torx screws located on the front of the PA hold it in the chassis.

QUAD+2

The QUAD+2 Power Amplifier is a hot-swap capable, forced convection cooled RF power amplifier. It accepts a low-level modulated RF signal from the transceiver module, and amplifies it for transmission via the site transmit antenna.


1-Dec-06 68P80801E35-E 5-3



Figure 5-1 40W - 800 MHz PA – TLF2020 (cover removed)

NOTE: 70W PA shown. 40W PA is similar.


5-4 68P80801E35-E 1-Dec-06



Figure 5-2 70W - 800 MHz PA – TLN3335 (cover removed)

NOTE: 70W PA shown. 40W PA is similar.


1-Dec-06 68P80801E35-E 5-5



Figure 5-3 800/900 MHz QUAD PA

Figure 5-4 QUAD+2 PA


5-6 68P80801E35-E 1-Dec-06


PA Theory of Operation

PA Theory of Operation 5

Table 5-2 describes the basic functions of the PA circuitry. Figures 5-5 and 5-6 show the functional block diagrams of 40W, 800 MHz and 70W, 800 MHz PA, respectively. Figures 5-7 shows a functional block diagram of 800 QUAD MHz. Figures 5-8 shows a functional block diagram of 900 MHz QUAD PA. Figures 5-9 shows a functional block diagram of QUAD+2 PA.

Table 5-2 Power Amplifier Circuitry

Circuit Description

DC/Metering Board

Serves as the main interface between the PA and the backplane board

Accepts RF input from the Exciter via a blindmate RF connector

Routes the RF input via a 50 Ω stripline to the Linear Driver Module RF amplifier

Routes the RF feedback from the RF Combiner/Peripheral Module to the Exciter via a blindmate RF connector

Provides digital alarm and metering information of the PA to the BRC via the SPI bus

Routes DC power to the fans and PA

Contains the thermistor that senses the PA temperature (800 MHz QUAD and 900 MHz QUAD)

Contains a Linear Driver Module and Linear Final Module Bias Enable Circuit (900 MHz QUAD)

Contains a Voltage Variable Attenuator Circuit (900 MHz QUAD)

Linear Driver Module(LDM)

Contains two Class AB stages with the final stage in a parallel configuration (70W-800 MHz, 40W-800 MHz, 800 MHz QUAD)

Contains three cascaded Class AB stages with the first two stages configured as distributed amplifiers and the final stage in parallel configuration (900 MHz QUAD)

Amplifies the low level RF signal ~11mW average power from the Exciter via the DC/Metering Board (70W-800 MHz, 800 MHz QUAD*, 900 MHz QUAD*)

Amplifies the low-level RF signal ~8 mW average power from the Exciter via the DC/Metering Board (40W- 800 MHz)

Provides an output of:~8 W (70W, 800MHz) average power

~4 W (40W, 800 MHz) average power

~6 W (800 MHz QUAD* and 900 MHz QUAD*) average power

Interconnect Board Provides RF interconnection from the LDM to the RF Splitter board

Provides DC supply filtering


1-Dec-06 68P80801E35-E 5-7



RF Splitter/DC board

Interfaces with the DC/Metering Board to route DC power to the LFMs

Interfaces with the DC/Metering Board to route PA Bias Enable to the six Linear Final Modules (900 MHz Quad)

Contains splitter circuits that split the RF output signal of the LDM to the three Linear Final Modules (40W- 800 MHz)

Contains splitter circuits that split the RF output signal of the LDM to the six Linear Final Modules (70W- 800 MHz, 800 MHz QUAD and 900 MHz QUAD)

Linear Final Module (LFM)

Each module contains two Class AB amplifiers in parallel. Each module amplifies one of three RF signals (~ 84 W average power) from the LDM (via the Splitter/DC board). Three LFMs provide a sum RF output of approximately 48 W average power, before losses. (40W, 800MHz)

Each module contains two Class AB amplifiers in parallel. Each module amplifies one of six RF signals (~ 8 W average power) from the LDM (via the Splitter/DC board). Six LFMs provide a sum RF output of approximately 97 W average power, before losses. (70W, 800MHz)

Each module contains two Class AB amplifiers in parallel. Each module amplifies one of six RF signals (~6W average power) from the LDM (via the splitter/DC Board). Six LFMs provide a sum RF output of approximately 73W average power , before losses. (800 MHZ QUAD* and 900 MHz QUAD*)

RF Interconnect Board(40W- 800 MHz PA only)

Contains three transmission lines that interconnect the LFMs to the RF Combiner/Peripheral Module

Combiner Board(70W-800 MHz,800 MHz QUAD, and900 MHz QUAD only)

Contains three separate Quadrature combiner circuits that respectively combine the six RF outputs from the LFMs into three signals. These three signals, in turn, are applied to the RF Combiner/Peripheral Module.

Table 5-2 Power Amplifier Circuitry (continued)

Circuit Description


5-8 68P80801E35-E 1-Dec-06



RF Combiner/Peripheral Module

Contains a combiner circuit that combines the three RF signals from the RF Interconnect Board (40W- 800 MHz PA) or the Combiner Board (70W-800 MHz PA). It then routes the combined RF signal through a single stage circulator and a Low Pass Filter. The final output signal is routed to the blindmate RF connector (40W-800 MHz and 70W-800 MHz PAs).

Contains a combiner circuit that combines the three RF signals from the Combiner Board. It then routes the combined RF signal through a dual stage circulator and a Low Pass Filter. The final output signal is routed to the blindmate RF output connector. (800 MHz QUAD and 900 MHz QUAD PAs)

Contains an RF coupler that provides an RF feedback signal to the Exciter via a blindmate RF connector on the DC/Metering Board. Also contains a forward and reverse power detector for alarm and power monitoring purposes.

Contains the thermistor that senses PA temperature and feeds the signal back to the DC/Metering Board for processing (40W-800 MHz, 70W-800 MHz)

Fan Assembly Consists of three fans used to keep the PA within predetermined

operating temperatures

DC Core Board(QUAD+2 only)

Provides Non-volatile memory (NVM) to store unique power amplifier calibration information

Provides Gain and FB power control

Provides Diagnostic sensors

Provides Digital interface to the rest of the base radio

Provides Cooling measures control

Provides Status LEDs

Driver Board(QUAD+2 only)

Amplifies the output RF signal from the transceiver module (via the core board) to an intermediate power level

Provides first two stages of RF amplification

Final Board(QUAD+2 only)

Amplifies the output RF signal from the driver board (via the distribution board).

Provides last two stages of RF amplification

Isolator Board(QUAD+2 only)

Provides proper RF loading to the final module

Low Pass Filter Board(QUAD+2 only)

Reduces harmonic power levels conducted through the PA RF output connector to acceptable levels


Circuit Description


1-Dec-06 68P80801E35-E 5-9



DC/Metering Board Non-QUAD PA

The DC/Metering Board provides the interface between the PA and the Base Radio backplane. The preamplified/modulated RF signal is input directly from the Exciter via the Base Radio backplane.

The RF input signal is applied to the input of the Linear Driver Module (LDM). The RF feedback signal is fed back to the Exciter, where it is monitored for errors.

The primary function of the DC/Metering Boards is to monitor proper operation of the PA. This information is forwarded to the Base Radio Controller (BRC) via the SPI bus. The alarms diagnostic points monitored by the BRC on the PA include the following: Forward power Reflected power PA temperature sense Fan Sensor

QUAD PA Only

The DC/Metering Board in the QUAD Radio serves the same function as it does in other radios. However, its circuitry is modified for compatibility with the QUAD Station. As a result, its logic circuitry is operated at 3.3 VDC.

In addition to the functions listed for non-QUAD versions above, the following meter points are ported to the SPI bus: A and B Currents

Thermistor (for PA temperature sensing circuit on the DC/Metering Board)

Voltage Variable Attenuator Circuit (900 MHz QUAD version)

PA Bias Enable Circuitry (900 MHz QUAD version)

Null Board(QUAD+2 only)

Provides +28Vdc to the Distribution Board

Distribution Board(QUAD+2 only)

Provides all signal routing from the Core and Null Boards to that of the Final and Low Pass Filter boards

Note * The power outputs described in this section for the 800 QUAD and 900 QUAD PAs are references to the single carrier mode operating at 52W average power out from the PA output connector.


Circuit Description


5-10 68P80801E35-E 1-Dec-06



Linear Driver Module 40W-800 MHz, 70W-800 MHZ and 800 MHZ QUAD PAs

The Linear Driver Module (LDM) amplifies the low-level RF signal from the Exciter. The LDM consists of a two-stage cascaded Class AB amplifier, with the final stage in a parallel configuration.

See Table 5-2 for the approximate input and output levels of the various LDMs. The LDM output is fed to the RF Splitter/DC Distribution Board via an Interconnect Board.

900 QUAD PA

The Linear Driver Module (LDM) amplifies the low-level RF signal from the Exciter. The LDM consists of a three stage, cascaded, Class AB amplifier, with the final stage in a parallel configuration.

See Table 5-2 for the approximate input and output power of the 900 MHz QUAD LDM.

The LDM Output is fed to the RF Splitter/DC Distribution Board via the Interconnect Board.

Interconnect Board The output of the LDM is applied to the Interconnect Board, which provides an RF connection to the RF Splitter/DC Distribution Board. As a separate function, area on the Interconnect Board serves as a convenient mounting location for electrolytic capacitors used for filtering the +28 VDC supply.

RF Splitter/DC Distribution Board

The RF Splitter portion of this board accepts the amplified signal from the LDM (via the Interconnect Board). The primary function of this circuit is to split the RF signal into drive signals for the LFMs.

In the 40W-800 MHz PA, this circuit splits the drive signal into three separate paths to be applied to the three LFMs, where the signals will be amplified further. In the 70W-800 MHz, 800 MHz QUAD and 900 MHZ QUAD PAs, this circuit splits the drive signal into six separate paths to be applied to the six LFMs, where the signals will be amplified further.

The DC Distribution portion of this board interfaces directly with the DC/Metering Board to route DC power to the LFMs and provide PA Bias Enable (900 MHz QUAD only)


1-Dec-06 68P80801E35-E 5-11



Linear Final Modules The RF Splitter output signals are applied directly into the LFMs for final amplification. Each LFM contains a coupler that splits the LFM input signal and feeds the parallel Class AB amplifiers that amplify the RF signals.

In the 40W PA, the amplified signals are then combined on the LFM and sent directly to the RF Interconnect Board. In the 70W PA, the amplified signals are then combined on the LFM and sent directly to the Combiner Board.

See Table 5-2 for the approximate total summed output powers of the various LFMs, before output losses.

RF Interconnect Board

40W- 800 MHz PA Only

The RF Interconnect Board consists of transmission line paths which route the three output signals from the LFMs to the three inputs of the RF Combiner/Peripheral Module.

Combiner Board The Combiner Board combines pairs of signals into single signals, thereby combining the six signals from the LDMs into three signals. The resulting three signals are applied to the RF Combiner/Peripheral Module.

RF Combiner/Peripheral Module

40- 800 MHz, 70W- 800 MHz PAs

This module consists of two portions: an RF combiner and a peripheral module. The RF Combiner portion of the module combines the three RF signals from the RF Interconnect Board (40W- 800 MHz PA) or the Combiner Board (70W- 800 MHz PA) into a single signal using a Wilkinson coupler arrangement.

Following the combiner circuit, the single combined RF signal is then passed through a directional coupler which derives a signal sample of the LFM RF power output. Via the coupler, a sample of the RF output signal is fed to the Exciter, via the DC/Metering Board, as a feedback signal. Following the coupler, the power output signal is passed through a single stage circulator, which protects the PA in the event of high reflected power.

The peripheral portion of the module provides a power monitor circuit that monitors the forward and reflected power of the output signal. This circuit furnishes the A/D converter on the DC/Metering Board with input signals representative of the forward and reflected power levels.


5-12 68P80801E35-E 1-Dec-06



For forward power, a signal representative of the measured value is sent to the BRC via the SPI bus. The BRC determines if this level is within tolerance of the programmed forward power level. If the level is not within parameters, the BRC will issue a warning to the site controller which, in turn, will shut down the Exciter if required.

Reflected power is monitored in the same manner. The BRC uses the reflected power to calculate the voltage standing wave ratio (VSWR). If the VSWR is determined to be excessive, the forward power is rolled back. If it is extremely excessive, the BRC issues a shut-down command to the Exciter.

A thermistor is located on the RF Combiner/Peripheral module to monitor the operating temperature of the PA. The thermistor signal indicating excessive temperature is applied to the A/D converter and then sent to the BRC. The BRC issues a cut-back command to the Exciter module if the monitored temperature is greater than 185° F (85° C).

800 MHz QUAD and 900 MHz QUAD

This module consists of two parts: an RF combiner and a Peripheral module. The RF combiner combines three RF signals from the Combiner Board into a single signal using a Wilkinson coupler arrangement. Following the combiner circuit, the single combined RF signal is then passed through a directional coupler, which derives a signal sample of the LFM RF power output. Via the coupler, a sample of the RF output signal is fed to the Exciter, via the DC/Metering Board, as a feedback signal. Following the coupler, the power output signal is passed through a dual stage circulator, which protects the PA in the event of high reflected power.

The Peripheral module provides a power monitor circuit that monitors the forward and reflected power of the output signal. This circuit furnishes the A/D converter on the DC/Metering Board with input signals, representative of the forward and reflected power levels.

For forward power, a signal representative of the measured value is sent to the BRC via the SPI bus. The BRC determines if this level is within tolerance of the programmed forward power level. If the level is not within tolerance, the BRC will issue a warning to the site controller, which, in turn, will shut down the Exciter, if required.

Reflected power is monitored in the same manner. The BRC uses the reflected power to calculate the voltage standing wave ratio (VSWR). If the VSWR is calculated as excessive, forward power is rolled back. If the VSWR calcu-lation is exceedingly out of tolerance, the BRC issues a shut-down command to the Exciter.

The Thermistor that monitors the operating temperature of the 800 MHZ QUAD and 900 MHz QUAD PAs is located on the DC/Metering Board


1-Dec-06 68P80801E35-E 5-13



Fan Module The PA contains a fan assembly to maintain normal operating temperature through the use of a cool air intake. The fan assembly consists of three individual fans in which airflow is directed across the PA heatsink.

The current draw of the fans is monitored by the DC/Metering Board. A voltage representative of the current draw is monitored by the BRC. The BRC flags the iSC if an alarm is triggered. The PA LED on the front panel of the BRC also lights, however the PA does not shut down due to a fan failure alone.

DC Core Board (QUAD+2)

The Core Board communicates with the other base radio modules as well as internal PA modules. It utilizes non-volatile memory (NVM) via an EEPROM to store unique PA calibration information.

Driver Board (QUAD+2)

The Driver Amplifier Board provides the first two stages of RF amplification within the PA. It accepts the output RF signal from the transceiver module (via the core board) and amplifies it to an intermediate power level. The Driver Amplifier Board also provides: Gain compensation over temperature.

On-board DC regulation.

Transmitter standby functionality

Final Board (QUAD+2)

The Final Amplifier Board provides the last two stages of RF amplification, including the second RF gain stage (parallel stage). QUAD+2 utilizes two Final Amplifier Boards.: RF power splitting (4–way)

RF power combining (4–way)

Diagnostics

Transmitter standby functionality

Isolator Board (QUAD+2)

The Isolator provides proper RF loading to the final module output regardless of the load presented to the output of the PA itself. The Isolator contains a load resistor to dissipate any reflected power caused by load mismatches at the output of the PA.


5-14 68P80801E35-E 1-Dec-06



Low Pass Filter (LPF) Board (QUAD+2)

The LPF Board reduces harmonic power levels conducted through the PA RF output connector to acceptable levels. The LPF Board has forward and feedback RF power detectors to monitor forward and reflected output power from the PA, in reference to its output connector. It has a single stage isolator that provides > 20dB isolation with < 0.35dB insertion loss. It also provides a low pass filter with < 0.54dB of in-band insertion loss.

Null Board (QUAD+2)

The Null Board provides the +28Vdc supply routing from the Core board to the Distribution board (which routes it to the Final board). It also provides the necessary bulk capacitance that is warranted by the Final board.

Distribution Board (QUAD+2)

The Distribution Board provides for all signal routing from the Core and the Null boards to the Final and LPF boards: RF signal from the driver module is split and provided as the input to each

of the two final modules.

RF output from both of the final modules is combined to a single path and provided as the input to the isolator.

RF power is coupled off the combined port and fed back to the XCVR

DC Power routing from the NULL board to the Final board

Forward and reverse DC signaling from the LPF board


1-Dec-06 68P80801E35-E 5-15



N O T E S . . .


5-16 68P80801E35-E 1-Dec-06



5-17

EBTS611121701JNM

RFINTERCONNECT

BOARD

LINEAR FINALMODULES

ARD

STAGE 3CLASS AB

1-Dec-06 68P80801E35-E

Figure 5-5 40W - 800 MHz PA Functional Block Diagram

DCFILTER

ADDRESS BUSFROM BRC

SPI BUSTO/FROM BRC

ADDRESS DECODE, MEMORY,& A/D CONVERTER CIRCUITRY

MEMORY

BOARD SELECTDECODE

CIRCUITRY

CHIPSELECT

CHIP SELECTDECODE

CIRCUITRY

CH

IPS

ELE

CT

RF INPUT

RF OUTTO ANTENNA

RF FEEDBACKTO EXCITER

MODULE

CLK/DATA

A/DCONVERTER

LINEAR DRIVER MODULE

CLASS AB STAGE 2CLASS AB

INTERCONNECTBOARD

+28 VDC

PA TEMP SENSE

RF COMBINER/PERIPHERAL MODULE

LOW-PASSFILTER

REF PWR

FWD PWR

FAN SENSE

TEMPERATURESENSOR

CIRCULATOR

50O

HM

LOA

D

50O

HM

LOA

D50

OH

MLO

AD

FAN ASSEMBLY

RF SPLITTER/DC DISTRIBUTION BO

50O

HM

LOA

D50

OH

MLO

AD

STAGE1


1-Dec-06

COMBINER BOARD

LINEAR FINALMODULES

50

OH

MLO

AD

EBTS417121701JNM

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

TRIBUTION BOARD

STAGE 3CLASS AB


5-18 68P80801E35-E

Figure 5-6 70W - 800 MHz PA Functional Block Diagram


ADDRESS BUSFROM BRC

SPI BUSTO/FROM BRC


MEMORY

A/DCONVERTER

BOARD SELECTDECODE

CIRCUITRY

PA TEMP SENSE

CHIPSELECT

CHIP SELECTDECODE

CIRCUITRY

CH

IPS

EL

EC

T


LOW-PASSFILTER

RF INPUT

RF OUTTO ANTENNA


MODULE

REF PWR

FWD PWR

FAN SENSE

FAN ASSEMBLY

TEMPERATURESENSOR

CLK/DATA

CIRCULATOR

50

OH

MLO

AD

STAGE1


RF SPLITTER/DC DIS

INTERCONNECTBOARD 5

0O

HM

LO

AD

50

OH

MLO

AD

DCFILTER

+28 VDC

50

OH

MLO

AD

50

OH

MLO

AD



5-19

COMBINER BOARD

LINEAR FINALMODULES

50

OH

ML

OA

D

EBTS417_800121701JNM

50

OH

ML

OA

D

50

OH

ML

OA

D

50

OH

ML

OA

D

50

OH

ML

OA

D

50

OH

ML

OA

D

STRIBUTION BOARD

STAGE 3CLASS AB

1-Dec-06 68P80801E35-E

Figure 5-7 800 MHz QUAD Power Amplifier Functional Block Diagram


ADDRESS BUSFROM BRC

SPI BUSTO/FROM BRC


MEMORY

A/DCONVERTER

BOARD SELECTDECODE

CIRCUITRY

PA TEMP SENSE

CHIPSELECT

CHIP SELECTDECODE

CIRCUITRY

CH

IPS

EL

EC

T


LOW-PASSFILTER

RF INPUT

RF OUTTO ANTENNA


MODULE

REF PWR

FWD PWR

FAN SENSE

FAN ASSEMBLY

TEMPERATURESENSOR

CLK/DATA

CIRCULATOR

50

OH

ML

OA

D

STAGE1


RF SPLITTER/DC DI

INTERCONNECTBOARD

DCFILTER

+28 VDC

CIRCULATOR

50

OH

ML

OA

D

50

OH

ML

OA

D5

0O

HM

LO

AD

50

OH

ML

OA

D5

0O

HM

LO

AD


1-Dec-06

COMBINER BOARD

LINEAR FINALMODULES

50

OH

MLO

AD

EBTS417_900121701JNM

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

RF SPLITTER/DC TRIBUTION BOARD

STAGE 3CLASS AB

50

OH

MLO

AD

50

OH

MLO

AD

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E

PA_E


5-20 68P80801E35-E

Figure 5-8 900 MHz QUAD Power Amplifier Functional Block Diagram


ADDRESS BUSFROM BRC

SPI BUSTO/FROM BRC


MEMORY

A/DCONVERTER

BOARD SELECTDECODE

CIRCUITRY

PA TEMP SENSE

CHIPSELECT

CHIP SELECTDECODE

CIRCUITRY

CH

IPS

EL

EC

T


LOW-PASSFILTER

RF INPUT

RF OUTTO ANTENNA


MODULE

REF PWR

FWD PWR

FAN SENSE

FAN ASSEMBLY

TEMPERATURESENSOR

CLK/DATA

CIRCULATOR

50

OH

MLO

AD

STAGE 2CLASS AB

DIS

INTERCONNECTBOARD

DCFILTER

+28 VDC

CIRCULATOR

50

OH

MLO

AD

50

OH

MLO

AD

50

OH

MLO

AD

EEPOT

STAGE 2CLASS AB

DISTRIBUTED

STAGE 1CLASS AB

DISTRIBUTED

C_E

INC

V_D

VVA

PA_ENABLE (PA_E)

PA_E

PA_E



5-21

SPLITTER

SPLITTER

SPLITTER

BLACKBEAR

BLACKBEAR

COMBINER

BLACKBEAR

BLACKBEAR

COMBINER

21-29 VDC COMBINER

5 VDC

FINAL BOARD

RWARD ANDVERSE DC

1-Dec-06 68P80801E35-E

Figure 5-9 QUAD+2 Power Amplifier Functional Block Diagram

SPLITTER

SPLITTER

SPLITTER

BLACKBEAR

BLACKBEAR

COMBINER

BLACKBEAR

BLACKBEAR

COMBINER

21-29 VDC

FWD VVA

FEEDBACKVVA

ICEBERGIC

SPLITTER

COMBINER

COMBINER

FEEDBACKCOUPLER

ISOLATOR

LOW PASSFILTER

DETECTORS

OUTPUT BOARD

FINAL BOARD

CORE BOARD

DRIVER BOARD DISTRIBUTION BOARD

NULL BOARD

RF FEEDBACK

RF IN

28 VDC

28 VDC

28 VDC

ADC

FORE


1-Dec-06


5-22 68P80801E35-E

N O T E S . . .

Chapter 6

Power Supply


Overview ...................................................................................... 6-2

Single Channel DC Power Supply Overview ................................ 6-3

DC Power Supply for QUAD Channel Base Radios ..................... 6-6

DC Power Supply for QUAD+2 Channel Base Radios ................ 6-9


1-Dec-06 68P80801E35-E 6-1

Power Supply Volume 2

Overview

Overview 6

This section provides technical information for the DC Power Supply (PS).


DC Power Supply Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU contains the Power Supply kit and required packaging. Table 6-1 provides a cross reference between DC Power Supply FRU numbers and kit numbers.


DescriptionFRU

NumberKit

Number

Single Channel DC Power Supply TLN3338 CPN1027

QUAD Channel DC Power Supply CLN1498 CLN1461

QUAD+2 Channel DC Power Supply DLN6656 MCPN1082


6-2 68P80801E35-E 1-Dec-06

Volume 2 Power Supply

Single Channel DC Power Supply Overview

Single Channel DC Power Supply Overview 6

The DC Power Supply provides DC operating voltages to the Base Radio FRUs. It accepts input voltages from 41VDC to 60VDC. The voltage source may be either positive or negative ground.

On initial start up, the supply requires nominal 43 VDC. If the voltage drops below 41 VDC, the DC Power Supply reverts to a quiescent mode and does not supply output power.

The DC Power Supply is designed for sites with an available source of DC voltage. Output voltages supplied from the DC Power Supply are 28.6 VDC, 14.2 VDC and 5.1 VDC with reference to output ground. The supply is rated for 575 Watts continuous output at up to 113° F (45° C) inlet air. At 140° F (60° C), the 28.6 VDC output lowers to 80% of maximum.

The DC Power Supply consists of the Power Supply and front panel hardware. The DC Power Supply connects to the chassis backplane using an edgecard style connector. The DC power supply is secured in the chassis with two Torx screws located on the front panel.

Figure 6-1 shows the DC Power Supply with the cover removed.

Figure 6-1 Single Channel DC Power Supply


1-Dec-06 68P80801E35-E 6-3



Single Channel DC Power Supply Controls and Indicators

Table 6-2 summarizes the LED indicators on the DC Power Supply during normal operation. The ON/OFF switch, located behind the front panel, turns the DC power supply on and off.

Single Channel DC Power Supply Performance Specifications

Table 6-3 lists the specifications for the DC Power Supply.

Table 6-2 DC Power Supply Indicators

LED Condition Indications

Green

Solid (on)Power Supply is on and operating under normal conditions with no alarms

OffPower Supply is turned off or required power is not available

Red

Solid (on)Power Supply fault or load fault on any output, or input voltage is out of range

OffPower Supply is under normal operation with no alarms

Table 6-3 DC Power Supply Specifications

Description Value or Range

Operating Temperature0° to +40° C (no derating)+41° to +60° C (derating)

Input Voltage 41 to 60 VDC

Input Polarity Positive (+) ground system

Start-up Voltage 43 VDC (minimum)

Input Current 15.6 A (maximum) @ 41 VDC

Steady State Output Voltages28.6 VDC +5%14.2 VDC +5%5.1 VDC +5%

Total Output Power Rating575 W (no derating)485 W (derating)


6-4 68P80801E35-E 1-Dec-06



Single Channel DC Power Supply Theory of Operation

Table 6-4 briefly describes the basic DC Power Supply circuitry. Figure 6-4 shows the functional block diagrams for the DC Power Supply.

Output Ripple

All outputs 150mV p-p (measured with 20 MHz BW oscilloscope at 25°C)High Frequency individual harmonic voltage limits (10kHz to 100MHz) are:

28.6 VDC 1.5 mV p-p

14.2 VDC 3.0 mV p-p

5.1 VDC 5.0 mV p-p

Short Circuit Current 0.5 A average (maximum)

Table 6-3 DC Power Supply Specifications (continued)


Table 6-4 DC Power Supply Circuitry

Circuit Description

Input Circuit

Routes input current from the DC power input cable through the high current printed circuit edge connector, EMI filter, panel mounted combination circuit breaker, and on/off switch

Start-up Inverter Circuitry

Provides VDC for power supply circuitry during initial power-up

Main Inverter CircuitryConsists of a switching-type power supply to generate the +28.6 VDC supply voltage

Temperature Protection

The Power Supply contains a built-in cooling fan that runs whenever the supply is powered on. The supply shuts down if temperature exceeds a preset threshold

+14.2 VDC Secondary Converter Circuitry

Consists of a switching-type power supply to generate the +14.2 VDC supply voltage

+5 VDC Secondary Converter Circuitry


Clock Generator Circuitry

Generates the 267 kHz and 133 kHz clock signals used by the pulse width modulators in the four inverter circuits


Serves as the main interface between A/D on the Power Supply and the BRC via the SPI bus


1-Dec-06 68P80801E35-E 6-5


DC Power Supply for QUAD Channel Base Radios

DC Power Supply for QUAD Channel Base Radios 6

QUAD Channel DC Power Supply Overview

The QUAD Channel DC Power Supply provides DC operating voltages to QUAD Channel Base Radio FRUs. The power supply accepts input voltage sources from 41VDC to 60VDC. Input sources may be either positively or negatively grounded.

On initial startup, the supply requires a nominal 43 VDC. If the voltage drops below 41 VDC, the QUAD Channel DC Power Supply enters quiescent mode. In quiescent mode, the power supply emits no power.

The QUAD Channel DC Power Supply is designed for sites with an available DC voltage source. Output voltages from the DC Power Supply are 28.6 VDC, 14.2 VDC and 3.3 VDC, with reference to output ground. The supply is rated for 575 Watts of continuous output, with up to 113° F (45° C) inlet air. At 140° F (60° C), the 28.6 VDC output reduces to 80% of maximum.

The QUAD Channel DC Power Supply consists of the Power Supply and front panel hardware. The QUAD Channel DC Power Supply connects to the chassis backplane through an edgecard connector. Two Torx screws on the front panel secure the QUAD Channel DC power supply to the chassis.

Figure 6-2 shows the QUAD Channel Power Supply with the cover removed.

Figure 6-2 Quad Carrier Power Supply


6-6 68P80801E35-E 1-Dec-06



QUAD Channel DC Power Supply Controls and Indicators

Table 6-5 summarizes LED indications on the QUAD Channel DC Power Supply during normal operation. The ON/OFF switch behind the front panel turns DC power supply on and off.

QUAD Channel DC Power Supply Performance Specifications

Table 6-6 lists the specifications for the QUAD Channel DC Power Supply.

Table 6-5 DC Power Supply Indicators


Green

Solid (on)Power Supply is on, and operating under normal conditions with no alarms


Red


OffPower Supply is operating normally, with no alarms



Operating Temperature0° to +40° C (no derating)+41° to +60° C (derating)



Startup Voltage 43 VDC (minimum)


Steady State Output Voltages28.6 VDC +5%14.2 VDC +5%3.3 VDC +5%

Total Output Power Rating575 W (no derating)485 W (derating)


1-Dec-06 68P80801E35-E 6-7



QUAD Channel DC Power Supply Theory of Operation

Table 6-7 briefly describes the basic DC Power Supply circuitry. Figure 6-6 shows the functional block diagrams for the DC Power Supply.

Output Ripple

All outputs 150mV p-p (measured with 20 MHz BW oscilloscope at 25°C)High Frequency individual harmonic voltage limits (10kHz to 100MHz) are:

28.6 VDC 1.5 mV p-p

14.2 VDC 3.0 mV p-p

3.3 VDC 5.0 mV p-p

Short Circuit Current 0.5 A average (maximum)



Table 6-7 DC Power Supply Circuitry

Circuit Description

Input Circuit

Routes input current from the DC power input cable through the high current printed circuit edge connector, EMI filter, panel mounted combination circuit breaker, and on/off switch

Startup Inverter Circuitry

Provides VDC for power supply circuitry during initial power-up

Main Inverter CircuitryConsists of a switching-type power supply to generate the +28.6 VDC supply voltage

Temperature Protection

The Power Supply contains a built-in cooling fan that runs whenever the supply is powered on. The supply shuts down if the temperature exceeds a preset threshold





Clock Generator Circuitry

Generates the 267 kHz and 133 kHz clock signals used by the pulse width modulators in the four inverter circuits


Serves as the main interface between A/D on the Power Supply and the BRC via the SPI bus


6-8 68P80801E35-E 1-Dec-06


DC Power Supply for QUAD+2 Channel Base Radios

DC Power Supply for QUAD+2 Channel Base Radios 6

QUAD+2 Channel Power Supply Overview

The QUAD+2 Channel DC Power Supply provides DC operating voltages to QUAD+2 Channel Base Radio. The power supply accepts input voltage sources from 43 VDC to 60 VDC. Input sources may be either positively or negatively grounded. The power supply generates two DC output voltages of 29 VDC with reference to output ground.

Figure 6-3 shows the QUAD+2 Channel Power Supply.

Figure 6-3 Quad+2 Power Supply (Front and Rear Views)

FRONT REAR


1-Dec-06 68P80801E35-E 6-9



QUAD+2 Channel Power Supply Controls and Indicators

Table 6-8 summarizes LED indications on the QUAD+2 Channel Power Supply during normal operation. Table 6-9 summarizes the Power Supply and Battery Charger states of the QUAD+2 Channel Power Supply during normal operation.

QUAD+2 Channel Power Supply Performance Specifications

Table 6-10 lists the specifications for the QUAD+2 Channel Power Supply.

Table 6-8 Power Supply Indicators


Green

Solid (on)Power Supply is on, and operating under normal conditions with no alarms


Red


Blinking Power Supply is impaired

OffPower Supply is operating normally, with no alarms

Table 6-9 Power Supply ON/OFF Switch

Switch Position Power Supply State

On Main DC converter runs to create the MAIN and AUX DC

outputs

Off Main DC converter is turned OFF and the MAIN and AUX

DC outputs become 0.0VDC

PFC section continues to run in an idle mode



Operating Temperature 0° to 60° C (no derating)


Input Start-up Voltage 46 VDC (minimum)



6-10 68P80801E35-E 1-Dec-06



QUAD+2 Channel Power Supply Theory of Operation

Table 6-11 briefly describes the basic Power Supply circuitry. Figure 6-8 shows the functional block diagrams for the Power Supply.


Main DC Output Voltage 28.94 VDC +3%

Main DC Output VDC Ripple 250 mVp-p



Table 6-11 Power Supply Circuitry

Circuit Description

DC Vcc

DC Vcc is developed on the CPN6112 board by U303, a fully integrated switching converter. The 48VDC bulk cap C320 serve as the energy source for DC Vcc. When the voltage across C320 is more than 24VDC, U303 is enabled and begins operating.

DC Input Reverse Polarity Protection

DC input reverse polarity protection is implemented by components on the CPN6112 board. If the DC input is connected in the incorrect polarity, the output transistor of DS300 will be turned ON, pulling the gates of transistors Q301/Q303 to the same value as the DC input, preventing the transistors from turning ON. Also, the output transistor of U100 is turned ON, which prevents the AC converter section from starting up until the reversed polarity condition is corrected.

DC Input Undervoltage Lockout

The DC Input Undervoltage Lockout (UVLO) function is implemented by using the EN pin (pin 1) of control IC U301 on the CPN6112 board. The resistor divider comprised of R307 and R308 reduce the DC input voltage at the EN pin of U301. When DC input rises above 44V, the voltage at pin 1 is above the enable threshold (going HIGH) voltage level, enabling the IC which turns ON the blocking FET Q301. When DC bus voltage drops below 42V, the voltage at pin 1 drops below the enable threshold (going LOW) and Q301 is turned OFF.The UVLO can be overridden by controlling the ON state of Q305. If Q305 is turned ON, Q307 is turned OFF and DC Vcc is fed directly to the EN pin via D300, keeping U301 enabled regardless of the magnitude of DC input voltage.


1-Dec-06 68P80801E35-E 6-11



DC Input Overvoltage Lockout

The DC Input Overvoltage Lockout (OVLO) function is implemented by TL431 U304 on the CPN6112 board. Voltage divider consisting of R336, R337 and R360 divide down the DC input voltage to the reference pin of U304. When DC input voltage exceeds 62.4V, the voltage at the reference input of U304 exceeds 2.5V and triggers U304. Q306 is then turned ON which applies DC Vcc to the gate of Q308, turning it ON. This pulls the EN pin of U301 to GROUND, disabling U301 and turning OFF the DC input blocking FET Q301. Feedback resistor R342 introduces approximately 100mV hysteresis between the set and reset points of U304, preventing oscillations when the DC voltage exceeds the setpoint.

DC Output Overvoltage

DC output overvoltage protection is implemented by U600 on the CPN6112 board. Resistor divider R600 and R601 divide the 28V down to the reference pin of TL431 U600. When 28V exceeds 31.4V, U600 is triggered, turning ON Q600 which then turns ON Q601, pulling the shutdown signal line to ground. Feedback resistor R604 provides a small amount of hysteresis so that the shutdown signal does not oscillate when the DC voltage is close to the setpoint value.

DC Output Overcurrent

The principal method for output overcurrent protection is a primary-side current sense. This feature is implemented by TL431 IC U1201 (when the supply is operating from a DC source). Both are located on the CPN6112 board.When the combined output current (the sum of the main and aux DC output current) exceeds 25A, the voltage at the reference pin of U1201 exceeds 2.5V and the TL431 is triggered. No hysteresis is incorporated into this setpoint because the shutdown of the supply immediately reduces the output current to zero (continuous operation with values approximately equal to the setpoint is not possible).

Power Supply Enable

The power supply includes a feature historically referred to as a “pin 1 enable” due to the use of pin 1 in legacy designs. Small signal pin D4 must be connected to chassis ground in order to permit the power supply to operate. If D4 is not grounded, the supply will operate in hiccup mode until D4 is terminated to ground.

Table 6-11 Power Supply Circuitry (continued)

Circuit Description


6-12 68P80801E35-E 1-Dec-06



Power Supply Remote Shutdown

The power supply can be remotely shut down by writing 0xFFC to U7300 (DAC 1) channel “OUTE”. This causes pin 6 of U7300 to go HIGH, turning ON Q100 and initiating a shutdown timer cycle. Simultaneously, the PRESET pin of U7300 is pulled LOW by transistor Q7300, causing all DAC output channels to be reset to zeros (all DAC channels are set to zeros as part of the initialization routine). This ensures that a single reset timer cycle occurs and the power supply and platform software will restart/reboot normally.

Power Supply Fan Speed Control

The power supply includes a two-speed cooling fan. When power is first applied, the fan defaults to low speed. If core software determines that the higher fan speed is needed, 0xCE4 is written to U7300 (DAC1) channel “OUTC”. This applies 3.3V to the control lead of the fan and causes the fan to operate at high speed. When the channel output is set to zero (by writing 0x000), the fan resumes low speed.

Power Factor Correction Circuit Remote Shutdown

To incorporate features such as battery capacity testing, remote shutdown of the PFC section is implemented through U505 (DAC2) channel “OUTD” and Q506 on the CPN6111 board. When 0xFFC is written to OUTD, Q506 is turned ON which turns ON the transistor of DS202. Transistor Q102 is turned OFF, which turns OFF Q113 and removes Vcc from the PFC IC U101. When OUTD of U505 is returned to LOW (either by writing 0x000 to OUTD, by cycling the front panel ON/OFF switch, or removing/ restoring AC input power) the PFC is again enabled.

Battery Charger Control

The Battery Charger control circuit creates a DC output voltage used to maintain the state of charge on the DC input source (normally a battery backup). Software turns ON and OFF the battery charger as needed, and sets the output voltage as required for the battery type selected.


Circuit Description


1-Dec-06 68P80801E35-E 6-13



Battery Charger Output Overvoltage Shutdown

Overvoltage shutdown of the battery charger occurs when voltage in excess of 60V is sensed. This is accomplished by TL431 U402 on the CPN6111 board. Resistor divider R418 and the parallel combination of R419 and R437 provide a scaled value of the output voltage to the reference pin of U402. When output voltage exceeds 60V, U402 is triggered, DS402 is turned OFF and the battery charger control IC is disabled by Q303/Q302.


Circuit Description


6-14 68P80801E35-E 1-Dec-06



6-15

+5.1 V INVERTER CIRCUITRY

FILTERCIRCUITRY

URRENTCT

REF

REF

SURGE CURRENTDELAY

REF

OVERVOLTAGEDETECT

FET

CROWBARCIRCUIT

A

2425

3031

+5.1 V DCTO

STATIONMODULES

VIABACKPLANE

P/OBACKPLANECONNECTOR

+5.1 V


FILTERCIRCUITRY

CURRENTCT

REF

REF

SURGE CURRENTDELAY

REF

OVERVOLTAGEDETECT

FET

CROWBARCIRCUIT

A

1617

2223

+14.2V DCTO

STATIONMODULES

VIABACKPLANE


+14.2V+14.2V

34

1415

+28.6 VDCTO

STATIONMODULES

VIABACKPLANE


REF

REF

CURRENTDETECT A

+28.6 V OVERVOLTAGEDETECT

+28 V BULK TODIAGNOSTICS

CIRCUITRY

OVERCURRENTDETECT

+28.6 VDC

B

LATIONORMER

MOD FAIL

FILTERINGCIRCUITRY

EBTS323011497JNM

1-Dec-06 68P80801E35-E

Figure 6-4 DC Power Supply Functional Block Diagram (Sheet 1 of 2)

FETDRIVER

POWER FETSWITCH

VCC

VCC

+ 5V OVERCDETE

+ 28V BULK

PULSEWIDTH

MODULATOR÷ 2

CLOCK GENERATOR CIRCUITRY

STARTUP INVERTER CIRCUITRY

BULK DETECTTO


PULSEWIDTH

MODULATOR

VCC

VCCSTARTUP ISOLATION

TRANSFORMER

FETDRIVER

POWER FETSWITCH

VCC

VCC

+ 14.2V OVERDETE

PULSEWIDTH

MODULATOR

PULSEWIDTH

MODULATOR

FRONT PANELON / OFFSWITCH

EXTERNALDC INPUT41-60 VDC

FILTERCIRCUITRY

INPUT FILTER BOARD

MAIN INVERTER CIRCUITRY


267 KHZ

TRANSISTORSWITCH

MAIN ISOTRANSF

TRANSISTORDRIVERS

SOFTSTARTCIRCUITRY

SHUTDOWNA

+12V STARTUP BIAS

+12V STARTUP BIAS

VCC

VCC

133 KHZ

267 KHZ

133 KHZ

133 KHZ

133 KHZ

133 KHZ

133 KHZ

267 KHZ

133 KHZ267 KHZ

133 KHZ

POWER FETSWITCHES

+28 V BULK


1-Dec-06

A/DCONVERTER

SPI BUS

AG

G

REF

REF

INPUT GOOD(GREEN)

MODULEFAIL

(RED)

3

SPI BUSTO/FROM

STATION CONTROLMODULE

ENABLE

EBTS324012097JNM


6-16 68P80801E35-E

Figure 6-5 DC Power Supply Functional Block Diagram (Sheet 2 of 2)

COOLINGFAN

THERMISTORMOUNTED ON

HEATSINK

REF

REF

REF

MOD FAIL

INPUT FAIL

HEATSINK DI

+5.1 V

+14.2V DIAG

+5.1 V DIAG

+28.6 V DIA

HEATSINK STATUSDETECT

HI-TEMPDETECT

BULK DETECTFROM STARTUP

INVERTERCIRCUITRY

FROMDETECT

CIRCUITRY

A

B

ADDRESS DECODE CIRCUITRY

ADDRESSDECODE

CIRCUITRY

FROMSTATION

CONTROLBOARD

9

P/O ADDRESS BUS ENABLE

DIAGNOSTICS CIRCUITRY

T°

J300

REF



6-17


FILTERCIRCUITRY

URRENTCT

REF

REF

SURGE CURRENTDELAY

REF

OVERVOLTAGEDETECT

FET

CROWBARCIRCUIT

A

2425

3031

+5.1 V DCTO

STATIONMODULES

VIABACKPLANE


+5.1 V


FILTERCIRCUITRY

CURRENTCT

REF

REF

SURGE CURRENTDELAY

REF

OVERVOLTAGEDETECT

FET

CROWBARCIRCUIT

A

1617

2223

+14.2V DCTO

STATIONMODULES

VIABACKPLANE


+14.2V+14.2V

34

1415

+28.6 VDCTO

STATIONMODULES

VIABACKPLANE


REF

REF

CURRENTDETECT A

+28.6 V OVERVOLTAGEDETECT

+28 V BULK TODIAGNOSTICS

CIRCUITRY

OVERCURRENTDETECT

+28.6 VDC

B

LATIONORMER

MOD FAIL

FILTERINGCIRCUITRY

EBTS323011497JNM

1-Dec-06 68P80801E35-E

Figure 6-6 QUAD DC Power Supply Functional Block Diagram (Sheet 1 of 2)

FETDRIVER

POWER FETSWITCH

VCC

VCC

+ 5V OVERCDETE

+ 28V BULK

PULSEWIDTH

MODULATOR÷ 2

CLOCK GENERATOR CIRCUITRY

STARTUP INVERTER CIRCUITRY

BULK DETECTTO


PULSEWIDTH

MODULATOR

VCC

VCCSTARTUP ISOLATION

TRANSFORMER

FETDRIVER

POWER FETSWITCH

VCC

VCC

+ 14.2V OVERDETE

PULSEWIDTH

MODULATOR

PULSEWIDTH

MODULATOR

FRONT PANELON / OFFSWITCH

EXTERNALDC INPUT41-60 VDC

FILTERCIRCUITRY

INPUT FILTER BOARD

MAIN INVERTER CIRCUITRY


267 KHZ

TRANSISTORSWITCH

MAIN ISOTRANSF

TRANSISTORDRIVERS

SOFTSTARTCIRCUITRY

SHUTDOWNA

+12V STARTUP BIAS

+12V STARTUP BIAS

VCC

VCC

133 KHZ

267 KHZ

133 KHZ

133 KHZ

133 KHZ

133 KHZ

133 KHZ

267 KHZ

133 KHZ267 KHZ

133 KHZ

POWER FETSWITCHES

+28 V BULK


1-Dec-06

A/DCONVERTER

SPI BUS

L

AIL

NK DIAG

.1 V

DIAG

DIAG

V DIAG

REF

REF

INPUT GOOD(GREEN)

MODULEFAIL

(RED)

3

SPI BUSTO/FROM

STATION CONTROLMODULE

ENABLE

EBTS324012097JNM


6-18 68P80801E35-E

Figure 6-7 QUAD DC Power Supply Functional Block Diagram (Sheet 2 of 2)

COOLINGFAN

THERMISTORMOUNTED ON

HEATSINK

REF

REF

REF

MOD FAI

INPUT F

HEATSI

+5

+14.2V

+5.1 V

+28.6

HEATSINK STATUSDETECT

HI-TEMPDETECT

BULK DETECTFROM STARTUP

INVERTERCIRCUITRY

FROMDETECT

CIRCUITRY

A

B

ADDRESS DECODE CIRCUITRY

ADDRESSDECODE

CIRCUITRY

FROMSTATION

CONTROLBOARD

9

P/O ADDRESS BUS ENABLE

DIAGNOSTICS CIRCUITRY

T°

J300

REF



6-19

circuitry is not supported in standard product configurations.

DC OUT is not supported in standard product configurations.

1-Dec-06 68P80801E35-E

Figure 6-8 QUAD+2 DC Power Supply Functional Block Diagram

NOTE: AC

AUX


1-Dec-06


6-20 68P80801E35-E

N O T E S . . .

Chapter 7

Receiver


Overview ...................................................................................... 7-2

800 MHz 3X Receiver – CLN1283 ............................................... 7-3

800 MHz QUAD Receiver - CLN1283900 MHz QUAD Receiver - DLN1201 ........................................ 7-10


1-Dec-06 68P80801E35-E 7-1

Receiver Volume 2

Overview

Overview 7

This section provides technical information for the Receiver (RX).


Receiver (RX) Field Replaceable Units (FRUs) are available for the iDEN EBTS. The FRU contains the RX kit and required packaging. Table 7-1 provides a cross reference between RX FRU numbers and kit numbers.


DescriptionFRU

NumberKit

Number

3 branch Receiver for 800 MHz Single Channel BR

CLN1283 CLF1470

3 branch Receiver for 900 MHz Single Channel BR

CLN1356 CLF1480

3 Branch Receiver for 900 MHz QUAD Channel BR

DLN1201 CLF6453

3 branch Receiver for 800 MHz QUAD Channel BR

CLN1496 CLF1550


7-2 68P80801E35-E 1-Dec-06

Volume 2 Receiver

800 MHz 3X Receiver – CLN1283

800 MHz 3X Receiver – CLN1283 7

800 MHz 3X Receiver Overview

The 3X Receiver provides the receiver functions for the Base Radio. It consists of a receiver board, a slide-in housing, and associated hardware. The 3X Receiver incorporates one to three diversity branches on a single module. Figure 7-1 shows a top view of the Receiver with the cover removed.

Figure 7-1 3X Receiver (with cover removed)

800 MHz 3X Receiver Definition and Identification

The 3X receiver kit contains three receivers on a single board. This allows a single module to provide three-branch diversity BR functionality. To identify 3X receiver boards in the EBTS, use the MMI command get_rx1_kit_no. This command can be used on all receiver models, and reports the kit number from the receiver’s EEPROM. The 3X receiver can also be identified by visual inspection of the front panel. Because the 3X receiver can only be inserted into the middle receiver slot, the front panel of a 3X receiver reads: INSERT ONLY IN SLOT RX2 WITH BACKPLANE 0183625X 3X RECEIVER.


1-Dec-06 68P80801E35-E 7-3

Receiver Volume 2


The two remaining receiver slots are covered with blank panels. A summary of the Receiver FRUs available for the Base Radio is provided in the chart below.

800 MHz 3X Receiver Replacement Compatibility

The 3X Receiver board (CRF6010 or CRF6030) can only be used in receive slot 2 (middle receiver slot) with backplane 0183625X _ _. The backplane connector is different than the TRF6560 version of the receiver board. This is why there is a need for a new backplane. The receiver will function only when it is installed in slot 2. The TRF6560 receiver will not make electrical connection in any slot of the new backplane. Compatibility between the new and old receiver boards is summarized in Tables 7-3 and 7-4 for 800 MHz Base Radios, respectively.

Table 7-2 Receiver FRUs

Receiver FRUs Chassis FRUs

3X Receiver:800 MHz CLN1283

With 3x Receiver Backplane:

800 MHzCLN1282

Single Receiver:800 MHz TLN3336

With Single Receiver Backplane:

800 MHz TLN3333

Table 7-3 800 MHz Base Radio Receiver Board/BR Backplane Compatibility

CRF6010 3X Receiver TRF6560 Receiver

New backplane 0183265X--

Compatible Not compatible

Old backplane 0182416W--

Not compatible Compatible

Table 7-4 900 MHz Base Radio Receiver Board/BR Backplane Compatibility

CRF6030A 3X Receiver

New backplane 0183265X--

Compatible

Old backplane 0182416W--

Not compatible


7-4 68P80801E35-E 1-Dec-06

Volume 2 Receiver


800 MHz 3X Receiver Diversity Configuration

There is a new software parameter used for diversity purposes with the CLN1283 and CLN1356 3X Receivers. The parameter is the rx_fru_config parameter. The diversity issues to consider are described in the following paragraph. This parameter can be accessed through the MMI commands using the Motorola password. ROMs prior to version R06.06.17 do not support the rx_fru_config parameter. The ROM version in a base repeater can be checked using the MMI command ver. If a repeater contains the CRF6010 or CRF6030 receiver, the BRC board must be populated with a compatible version of ROM. Table 7-5 lists the ROM compatibilities.

Note When replacing FRUs, ensure that the ROM version on the BRC installed in the base radio is compatible with the ROM version on the Receiver.

If downloaded code is used, then the downloaded code can be used to change the needed parameter (the rx_fru_config parameter).

800 MHz 3X Receiver Diversity Uses and Cautions

The 3X receiver board can be used in one, two, or three branch diversity systems. The number of active receivers is determined by the rx_fru_config parameter stored on the Base Radio Control (BRC) board. The rx_fru_config parameter is only valid, and must be set properly for, systems utilizing the CRF6010 or CRF6030 3X Receiver board. The rx_fru_config parameter is ignored by Base Radios that have ROM older than version R06.06.17 installed on the Base Radio Controller board.

To view the rx_fru_config parameter, use the MMI command get rx_fru_config. The configuration of each repeater can be changed in the field to match the number of receivers connected to antennas. To change the rx_fru_config parameter, use the command set rx_fru_config yyy, where yyy is the active receiver (yyy is 1 for one branch, 12 for two branch, and 123 for three branch diversity. For the iDEN system to work optimally, the rx_fru_config parameter must match the number of receivers connected to antennas.

Table 7-5 Receiver ROM Compatibility

CRF6010/CRF6030 TRF6560

ROM version R06.03.40 Not compatible Compatible



ROM versions newer than R06.06.17

Compatible Compatible


1-Dec-06 68P80801E35-E 7-5

Receiver Volume 2


CAUTIONThere will be significant system degradation if the rx_fru_config parameter is not properly set in systems with the CLN1283 or CLN1356 3X receiver kit.


Note This procedure is applicable only to Base Radios equipped with the CRF6010 or CRF6030 3X Receiver Board.

When modifying a three branch Base Radio to a two branch Base Radio, it is important to observe all precautionary statements in the previous paragraph.

To modify a three branch Base Radio to a two branch Base Radio:


2. Connect an SMA male load (Motorola part number 5882106P03) to the RX3 connector on the Base Radio.The SMA male load is required to limit the amount of radiated emissions.

3. Verify that the rx_fru_config parameter is set properly as described in the Diversity Uses and Caution paragraph above.


1. Remove the SMA male load from the RX3 connector of the Base Radio you wish to convert from two branch diversity to three branch diversity.


3. Verify that the rx_fru_config parameter is set properly as described in the Diversity Uses and Cautions paragraph.


7-6 68P80801E35-E 1-Dec-06

Volume 2 Receiver


800 MHz 3X Receiver Theory of Operation

The Receiver performs highly selective bandpass filtering and dual down conversion of the station receive RF signal. A custom Receiver IC outputs the baseband information in a differential data format and sends it to the BRC.

Table 7-6 lists the Receiver circuitry and Figure 7-3 shows a functional block diagram for the Receiver.



The PLL IC receives frequency selection data from the BRC module micro-processor via the SPI bus. Once programmed, the PLL IC compares a 2.1 MHz reference signal from the BRC with a feedback sample of the VCO output from its feedback buffer.

Correction pulses are generated by the PLL IC, depending on whether the feedback signal is higher or lower in frequency than the 2.1 MHz reference. The width of these pulses is dependent on the amount of difference between the 2.1 MHz reference and the VCO feedback.

Table 7-6 Receiver Circuitry

Circuit Description


Consists of a phase-locked loop and VCO. It generates the 1st LO injection signal for all three receivers.


Provides filtering, amplification, and the 1st down conversion of the receive RF signal. Digital step attenuators at the 1st IF are included in this block.


Consists of a custom IC to perform the 2nd down conversion, filtering, amplification, and conversion of the receive signal. This block outputs the receive signal as differential data to the BRC.


Performs address decoding for board and chip select signal, converts analog status signals to digital format for use by the BRC. A memory device holds module specific information.


Accepts +14.2 VDC input from the backplane interconnect board and generates two +10 VDC, a +11.5 VDC, and two +5 VDC signals for the receiver.


1-Dec-06 68P80801E35-E 7-7

Receiver Volume 2


The up/down pulses are fed to a charge pump circuit that outputs a DC voltage proportional to the pulse widths. This DC voltage is low-pass filtered and fed to the VCO circuit as the control voltage. The control voltage is between +2.5 VDC and +7.5 VDC.

The DC control voltage from the synthesizer is fed to the VCO, which generates the RF signal used to produce the 1st LO injection signal. The VCO responds to the DC control voltage by generating the appropriate RF signal. This signal is fed through a buffer to the 1st LO injection amplifier. A sample of this signal is returned to the PLL IC through a buffer to close the VCO feedback loop.


The station receive RF signal enters the Receiver through the RF-type connector located on the back of the Receiver board. This signal is low-pass filtered and amplified. The amplified output is image filtered before being input to the 1st mixer. The signal mixes with the 1st LO injection signal to produce a 73.35 MHz 1st IF signal.

The 1st IF signal is sent through a 4-pole bandpass filter and fed to a buffer amplifier. The buffer amplifier output signal is 4-pole bandpass filtered again and the resultant signal is then passed through a digital attenuator. This atten-uation is determined by the BRC. The resulting signal is then fed to the RF input of the custom receive IC.


The custom Receiver IC provides additional amplification, filtering, and a second down-conversion. The 2nd IF signal is converted to a digital signal and is output via differential driver circuitry to the BRC. This data signal contains the necessary I and Q information, AGC information, and other data transfer information required by the BRC to process the receive signal.

The remainder of the custom Receiver IC circuitry consists of timing and tank circuits to support the internal oscillator, 2nd LO synthesizer circuitry, and 2nd IF circuitry.

A serial bus provides data communications between the custom Receiver IC and the DSP Glue ASIC (DGA) located on the BRC. This bus enables the DGA to control various current and gain settings, establish the data bus clock rate, program the 2nd LO, and perform other control functions.


The address decode circuitry enables the BRC to use the SPI bus to select a specific device on a specific Receiver for control or data communication purposes.


7-8 68P80801E35-E 1-Dec-06

Volume 2 Receiver


If the board select circuitry decodes address lines A2 through A5 as the Receiver address, it enables the chip select circuitry. The chip select circuitry then decodes address lines A0 and A1 to generate the chip select signals for the EEPROM, A/D converter, and PLL IC.

Memory Circuitry

The memory circuitry consists of three EEPROMs located on the Receiver. The BRC performs all memory read and write operations via the SPI bus. Information stored in this memory device includes the kit number, revision number, module specific scaling and correction factors, and free form module information (scratch pad).


Analog signals from various strategic operating points throughout the Receiver board are fed to the A/D converter. These analog signals are converted to a digital signal and are output to the BRC via the SPI lines upon request of the BRC.


The voltage regulator circuitry consists of two +10 VDC, a +10.8 VDC, and two +5 VDC regulators. The two +10 VDC and the +10.8 VDC regulators accept the +14.2 VDC input from the backplane interconnect board and generate the operating voltages for the Receiver circuitry.

The +10 VDC regulators each feed a +5 VDC regulator, one of which outputs Analog +5 VDC, and the other Digital +5 VDC operating voltages for use by the custom Receiver IC.

A +5.1 VDC operating voltage is also available from the backplane inter-connect board to supply +5.1 VDC to the remainder of the Receiver circuitry.


1-Dec-06 68P80801E35-E 7-9

Receiver Volume 2

800 MHz QUAD Receiver - CLN1283 900 MHz QUAD Receiver - DLN1201

800 MHz QUAD Receiver - CLN1283900 MHz QUAD Receiver - DLN1201 7

QUAD Channel Receiver Overview

The QUAD Channel BR Receiver provides receiver functions for the QUAD Channel Base Radio. The QUAD Channel BR Receiver consists of a receiver board, a slide-in housing, and associated hardware. A single module of the QUAD receiver incorporates one to three diversity branches. Figure 7-2 shows a top view of the Receiver with the housing removed.

Figure 7-2 QUAD Receiver (with housing removed)


7-10 68P80801E35-E 1-Dec-06

Volume 2 Receiver

800 MHz QUAD Receiver - CLN1283 900 MHz QUAD

QUAD Channel Receiver Diversity Uses and Cautions

The QUAD Channel BR Receiver board can be used in one, two, or three-branch diversity systems. The diversity parameter determines the number of active receivers. To view the diversity parameter, use the MMI command. (See software commands.) Each repeater’s configuration can be changed in the field to match the number of receivers connected to antennas. To change the diversity parameter, use the command (see software commands). For the iDEN system to work optimally, the diversity parameter must match the number of receivers connected to antennas.

CAUTIONImproperly setting the diversity parameter will cause serious system degradation.


When modifying a three-branch Base Radio to a two-branch Base Radio, observing all precautionary statements in the previous paragraph is important.

To modify a three-branch Base Radio to a two-branch Base Radio:


2. Connect an SMA male load (Motorola part number 5882106P03) to the RX3 connector on the Base Radio.

3. The SMA male load is required to limit the amount of radiated emissions.

4. Verify that the diversity parameter is set properly, according to the Diversity Uses and Caution paragraph above.


1. Remove the SMA male load from the RX3 connector of the Base Radio that you wish to convert from two-branch diversity to three-branch diversity.


3. Verify that the diversity parameter is set properly, according to the Diversity Uses and Cautions paragraph.


1-Dec-06 68P80801E35-E 7-11

Receiver Volume 2


QUAD Channel Receiver Theory of Operation

The Receiver performs highly selective bandpass filtering and dual down conversion of the station receive RF signal. A custom Receiver IC outputs the baseband information in a differential data format and sends it to the BRC.

Table 7-7 lists the Receiver circuitry. Figure 7-4 shows a functional block diagram for the Receiver.



The PLL IC receives frequency selection data from the BRC module micro-processor via the SPI bus. Once programmed, the PLL IC compares a 2.1 MHz reference signal from the BRC with a feedback sample of the VCO output from its feedback buffer.

The PLL ICC generates correction pulses, depending on whether the feedback signal is higher or lower in frequency than the 2.1 MHz reference. The width of these pulses depends on the amount of difference between the 2.1 MHz reference and the VCO feedback.

Table 7-7 QUAD Receiver Circuitry

Circuit Description


Consists of a phase-locked loop and VCO. It generates the 1st LO injection signal for all three receivers.


Provides filtering, amplification, and the 1st down conversion of the receive RF signal. This block includes digital step attenuators at the 1st IF.


Consists of a custom IC to perform the 2nd down conversion, filtering, amplification, and conversion of the receive signal. This block outputs the receive signal as differential data to the BRC.


Performs address decoding for board and chip-select signals. Converts analog status signals to digital format for use by the BRC. A memory device holds module-specific information.


Accepts +14.2 VDC input from the backplane interconnect board. Also generates two +10 VDC, a +11.5 VDC, and two +5 VDC signals for the receiver.


7-12 68P80801E35-E 1-Dec-06

Volume 2 Receiver

800 MHz QUAD Receiver - CLN1283 900 MHz QUAD

The up/down pulses enter a charge pump circuit. The charge pump outputs a DC voltage proportional to the pulse widths. After low-pass filtering, this DC voltage enters the VCO circuit as the control voltage. The control voltage measures between +2.5 VDC and +7.5 VDC.

The DC control voltage from the synthesizer enters the VCO. The VCO generates the RF signal that the circuit uses to produce the 1st LO injection signal. The VCO responds to the DC control voltage by generating the appro-priate RF signal. This signal passes through a buffer to the 1st LO injection amplifier. A sample of this signal returns to the PLL IC through a buffer to close the VCO feedback loop.


The station receive RF signal enters the Receiver through the RF-type connector on the back of the Receiver board. The circuit low-pass filters and amplifies this signal. The amplified output passes through an image filter before entering the 1st mixer. The signal mixes with the 1st LO injection signal to produce a 73.35 MHz 1st IF signal.

The 1st IF signal passes through a four-pole, bandpass filter and enters a buffer amplifier. The buffer amplifier output signal again undergoes four-pole, bandpass filtering. The resultant signal then passes through a digital attenuator. The BRC determines the amount of attenuation. The resulting signal then enters the RF input of the custom Receiver IC.


The custom Receiver IC provides additional amplification, filtering, and a second down-conversion. The IC converts the 2nd IF signal to a digital signal. The digital signal exits the receiver IC via differential driver circuitry, and passes to the BRC. This data signal contains I and Q information, AGC infor-mation, and other data transfer information. The BRC uses this information to facilitate processing of the receive signal.

The remainder of the custom Receiver IC circuitry consists of timing and tank circuits. These circuits support the internal oscillator, 2nd LO synthesizer, and 2nd IF circuitry.

A serial bus provides data communications between the custom Receiver IC and the DSP Glue ASIC (DGA). These circuits are on the BRC. The serial bus enables the DGA to perform several control functions... control various current and gain settings establish the data bus clock rate program the 2nd LO perform other control functions


1-Dec-06 68P80801E35-E 7-13

Receiver Volume 2



Address decode circuitry enables the BRC to use the SPI bus to select a specific device on a specific Receiver for control or data communication purposes.

If board-select circuitry decodes address lines A2 through A5 as the Receiver address, it enables the chip select circuitry. The chip select circuitry then decodes address lines A0 and A1. The decoding process generates the chip select signals for the EEPROM, A/D converter, and PLL IC.

Memory Circuitry

The memory circuitry consists of three EEPROMs located on the Receiver. The BRC performs memory read and write operations via the SPI bus. Infor-mation stored in this memory device includes... the kit number revision number module specific scaling and correction factors free form module information (scratch pad)


Analog signals from various strategic operating points throughout the Receiver board pass through the A/D converter. These analog signals become a digital signal. Upon request of the BRC, this signal travels to the BRC via the SPI lines.


The voltage regulator circuitry consists of two +10 VDC, a +10.8 VDC, and two +5 VDC regulators. The two +10 VDC and the +10.8 VDC regulators accept the +14.2 VDC input from the backplane interconnect board. These regulators produce operating voltages for the Receiver circuitry.

The +10 VDC regulators each feed a +5 VDC regulator. One of these regulators outputs Analog +5 VDC. The other regulator outputs Digital +5 VDC operating voltages for use by the custom Receiver IC.

The backplane interconnect board also produces a +5.1 VDC operating voltage. This voltage powers the remainder of the Receiver circuitry.


7-14 68P80801E35-E 1-Dec-06

Volume 2 Receiver


7-15

DIFFERENTIALDATA

TO CONTROLMODULE

SERIAL BUSTO/FROM CONTROL

MODULE

AGCFROM CONTROL

MODULE

2ND LOVCO

14.4 MHZTIMING

CIRCUITRY

450 KHZFILTER

CIRCUITRY

DRIVERCIRCUITRY

CUSTOM RECEIVERIC CIRCUITRY(ABACUS #1 )

DIGITALATTENUATOR

CIRCUITRY

73.35 MHZ1ST IF

CUSTOMRECEIVER

IC

ITAL5 VURCE

10 VURCE

LOG VRCE

VCOEDBACK

2.1 MHZ REF

4-POLEBANDPASS

FILTER

EBTS293120597JNM

JECTIONPLIFIER

ABACUS #2

ABACUS #3

3 WAYSPLITTER

(NOTE)

1-Dec-06 68P80801E35-E

Figure 7-3 3X Receiver Functional Block Diagram

RECEIVER #3 FRONT END CIRCUITRY


RECEIVE RFFROM RX ANTENNA

(MULTICOUPLER)

SMA-TYPECONNECTOR

2.1 MHZ REFFROM CONTROL

MODULE


MODULE


MODULE


CHIP SELECTDECODE CIRCUITRY

RECEIVER SELECTDECODE CIRCUITRY

MEMORY #1


CHARGEPUMP

PHASELOCKED

LOOPIC

+10 VREGULATOR

REGULATORYCIRCUITRY

VCOCIRCUITRY

+10 V

LO-PASSFILTER

HI-PASSFILTER

PREAMPLIFIERCIRCUITRY


VCOFEEDBACK

BUFFER

BUFFER

SUPERFILTER

OSCILLATOR

BUFFERAMP

LO-PASSLOOP

FILTER

CONTROLVOLTAGE

(+2.5 TO +7.5 VDC)

VCO FEEDBACK

2.1 MHZ REFERENCE

CHIPSELECT

CHIPSELECT

SECOND+10 V

SOURCE

+14.2 VFROM

BACKPLANE

+10 VREGULATOR

+5 VREGULATOR

+5 VREGULATOR

DIG+

SO

+SO

ANA+5

SOU

CHIPSELECT

FIN

RIN

FE

SPI BUS (CLOCK & DATA)

VARIOUSSIGNALS

TO MONITOR

4-POLEBANDPASS

FILTER

1STMIXER

VCO

MEMORY #2

MEMORY #3

#3 A/DCONVERTER

#2 A/DCONVERTER

#1 A/DCONVERTER

+10 VREGULATOR

INAM

TO RECEIVER #2 MIXER


NOTE: 14.4 MHz TIMING CIRCUITRY AND 2ND LO VCO PRESENT ONLY ON ABACUS #2. FUNCTIONS ARE SHARED FOR ALL THREE ABACUS SECTIONS.

Receiver Volume 2

1-Dec-06

DIFFERENTIALDATA

TO CONTROLMODULE

SERIAL BUSTO/FROM ARMIC

AGCFROM ARMIC

2ND LOVCO

14.4 MHZTIMING

CIRCUITRY

450 KHZFILTER

CIRCUITRY

DRIVERCIRCUITRY

CUSTOM RECEIVERIC CIRCUITRY(ABACUS #1 )

DIGITALATTENUATOR

CIRCUITRY

73.35 MHZ1ST IF

CUSTOMRECEIVER

IC

2.1 MHZ REF

4-POLEBANDPASS

FILTER

EBTS293Q011801JNM

R

ABACUS #2

ABACUS #3

AYITTER

(NOTE)

ARMIC

SPI BUSFROMCONTROLMODULE

SPI BUSTOCONTROLMODULE

16.8 MHzREF FROMCONTROLMODULE

HOST SPIBUS FROMCONTROLMODULE


7-16 68P80801E35-E

Figure 7-4 800 and 900 MHz QUAD Receiver Functional Block Diagram



RECEIVE RFOM RX ANTENNA

(MULTICOUPLER)

SMA-TYPECONNECTOR

2.1 MHZ REFFROM CONTROL

MODULE


MODULE


MODULE


CHIP SELECTDECODE CIRCUITRY

RECEIVER SELECTDECODE CIRCUITRY

MEMORY #1


CHARGEPUMP

PHASELOCKED

LOOPIC

+10 VREGULATOR

REGULATORYCIRCUITRY

VCOCIRCUITRY

+10 V

LO-PASSFILTER

HI-PASSFILTER

PREAMPLIFIERCIRCUITRY


VCOFEEDBACK

BUFFER

BUFFER

SUPERFILTER

OSCILLATOR

BUFFERAMP

LO-PASSLOOP

FILTER

CONTROLVOLTAGE

(+2.5 TO +7.5 VDC)

VCO FEEDBACK

2.1 MHZ REFERENCE

CHIPSELECT

CHIPSELECT

SECOND+10 V

SOURCE

+14.2 VFROM

BACKPLANE

+10 VREGULATOR

+5 VREGULATOR

+5 VREGULATOR

DIGITAL+5 V

SOURCE

+10 VSOURCE

ANALOG+5 V

SOURCE

CHIPSELECT

FIN

RIN

VCOFEEDBACK

SPI BUS (CLOCK & DATA)

VARIOUSSIGNALS

TO MONITOR

4-POLEBANDPASS

FILTER

1STMIXER

VCO

#2 A/DCONVERTER

#1 A/DCONVERTER

+10 VREGULATOR

INJECTIONAMPLIFIE



3 WSPL

NOTE: 14.4 MHz TIMING CIRCUITRY AND 2ND LO VCO PRESENT ONLY ON ABACUS #2. FUNCTIONS ARE SHARED FOR ALL THREE ABACUS SECTIONS.

FROM RX #EXPANSION

OUTPUT

FROM RX #EXPANSION

OUTPUT

BRANCHEXPANSION

OUTPUT

DISTRIBUTED MULTICOUPLER*

* MULTICOUPLER BYPASSED ON CH4 RX

Chapter 8

Fan Assembly


Overview ...................................................................................... 8-2


1-Dec-06 68P80801E35-E 8-1

Fan Assembly Volume 2

Overview

Overview 8

The fan assembly provides continuous forced air cooling for the QUAD+2 Base Radio power amplifier and transceiver modules. The fan assembly houses two 119 mm axial fans which deliver a total of approximately 160 cubic feet per minute of airflow. Nominal fan speed is 4100 revolutions per minute. Each fan has a built in speed sensor which will turn on the red Fan Alarm LED if fan speed for either fan falls 30% below rated speed.

The fan assembly connects to the base radio backplane via a 4–pin port on the front of the base radio chassis. Figure 8-1 shows the fan assembly.Note The power supply module has its own fan which provides independent

airflow.

Figure 8-1 Fan Assembly

Fan Assembly Indicator

The fan assembly has one “Fan Alarm” LED visible from the lower right corner of its front panel. The Alarm is red during Lamp Test (for a second or less), and remains red if there is a fan failure. A fan failure alarm occurs if the built in speed sensor detects that either fan is operating 30% below rated speed. A red Fan Alarm indicates that the fan module needs to be replaced.


The Fan Assembly Field Replaceable Unit (FRU) is available for the iDEN QUAD+2 Base Radio. The FRU contains the Fan Assembly kit and required packaging. Table 8-1 provides a cross reference between Fan Assembly FRU number and kit number.


DescriptionFRU

Number Kit Number

QUAD+2 Fan Assembly DLN6657 0180706H35


8-2 68P80801E35-E 1-Dec-06

Chapter 9

TroubleshootingIn This Chapter Topic See Page

Overview ...................................................................................... 9-2

Troubleshooting Preliminaries ...................................................... 9-3

Legacy Single Channel Base Radio FRU Replacement Procedures .................................................... 9-6

Legacy Single Channel BR Station Verification Procedures ........ 9-9

Legacy Single Channel Base Radio Backplane ......................... 9-22

Generation 2 Single Channel Base Radio FRU Replacement Procedures .................................................. 9-42

Generation 2 Single Channel BR Station Verification Procedures .............................................................. 9-45

Generation 2/EBRC Single Channel Base Radio Backplane ..... 9-66

QUAD Channel Base Radio/Base Radio FRU Replacement Procedures .................................................. 9-82

QUAD Base Radio Station Verification Procedures ................... 9-86

QUAD Channel BR Backplane ................................................. 9-117

QUAD Base Radio Signals ....................................................... 9-132

QUAD+2 Channel Base Radio/Base Radio FRU Replacement Procedures ................................................ 9-136

QUAD+2 Base Radio Station Verification Procedures ............. 9-142

QUAD+2 Channel BR Backplane ............................................. 9-178

QUAD+2 Base Radio Signals .................................................. 9-190


22-Mar-06 6880801E35-E 9-1

Troubleshooting Volume 2

Overview

Overview

This chapter is a guide for isolating Base Radio failures to the FRU level. There are three sections- one each for Legacy Single Channel Base Radios, Generation 2 Single Channel Base Radios, QUAD Channel Base Radios and QUAD+2 Channel Base Radios. Each section contains procedures for: Troubleshooting Verification/Station Operation

The maintenance philosophy for any Base Radio is to repair by replacing defective FRUs with new FRUs. This method limits down-time.

Two troubleshooting procedures are included. Each procedure is designed to quickly identify faulty FRUs.

Ship defective FRUs to a Motorola repair depot for repair.Note Any product damage resulting from improperly packaged equipment

will not be covered under the standard Motorola warranty agreement.


9-2 6880801E35-E 22-Mar-06

Volume 2 Troubleshooting

Troubleshooting Preliminaries


Recommended Test Equipment

Table 9-1 lists recommended test equipment necessary for performing Base Radio troubleshooting/verification procedures.

Troubleshooting Procedures

Many of the troubleshooting and station operation procedures require Man-Machine Interface (MMI) commands. These commands are used to commu-nicate station level commands to the Base Radio via the RS-232 communica-tions port located on the front of the BRC.

Table 9-1 Recommended Test Equipment

Equipment Model/Type Manufacturer Description

Service Computer † 80286 or betterIBM, IBM compatible, or

MacintoshLocal service computer with a Serial Port

Application Code n/a MotorolaCompressed application code for Gen 3 SC and BRC

Communication Software

ProComm PlusHyperTerminal

SymantecWindows 95/98/2000/XP

Host communication

RS-232 Cable n/a Locally ProcuredStraight through connecting cable with DB9 connector for BRC port

RF Attenuator,250W, 10dB

01-80301E7258-45-33

MotorolaAeroflex / Weinschel

Used to attenuate receive signals for testing

RF Power Meter††HP438AE4418

Hewlett-PackardAgilent

Used to perform relative calibration and linearity checks of signal source

Low-Power Sensor Head

HP8481DE9301

Hewlett-PackardAgilent

Used in conjunction with Power Meter

Rubidium Frequency Standard

RubiSource SymmetricomUsed as a frequency standard for receive test

iDEN Test Set R2660 MotorolaUsed for checking receive operation

Note † Either a DOS-based computer or Macintosh computer may be used for the service computer. Contact your iDEN System Manager for additional information.

†† Do not substitute analog power meter (such as HP435A). Analog power meter averaging time is not long enough to accurately read pulsed iDEN signal.


22-Mar-06 6880801E35-E 9-3



Routine Checkout

Procedure One is a quick, non-intrusive test performed during a routine site visit. Use this procedure to verify proper station operation without taking the station out of service. Figure 9-1 shows the Procedure One Troubleshooting Flowchart.

Figure 9-1 Procedure One Troubleshooting Flowchart

PROCEDURE 1ROUTINE

SITE VISIT

OBSERVE LEDINDICATORS

Module Suspectedof Being Faulty?

No

No

DONE

CHECK CURRENTALARM STATUS

Use MMI commandget alarms

to check alarm status


YesGo to Troubleshooting

Procedure 2 Flow Chart

YesGo to Troubleshooting

Procedure 2 Flow Chart

Refer toControls and Indicators

for LED Definitions

EBTS021071895JNM


9-4 6880801E35-E 22-Mar-06



Reported/Suspected Problem

Use Procedure Two to troubleshoot reported or suspected equipment malfunc-tions. Perform this procedure with equipment in service (non-intrusive) and with equipment taken temporarily out of service (intrusive).

Figure 9-2 shows the Procedure Two Troubleshooting Flowchart.

Figure 9-2 Procedure Two Troubleshooting Flowchart

PROCEDURE 2PROBLEM

REPORTED OR SUSPECTED

DONEClear Problem Report

OBSERVE LEDINDICATORS


YesGo to Module Replacement

Procedures Section

No

CHECK CURRENTALARM STATUS

Use MMI commandget alarms

to check alarm status


Go to Module ReplacementProcedures Section

PERFORMVERIFICATION TESTSUse MMI commands to

perform tests as specified instation verification procedure.


Go to Module ReplacementProcedures Section

Yes

No

Yes

No

Refer toControls and Indicators

for LED Definitions

EBTS022071895JNM


22-Mar-06 6880801E35-E 9-5


Legacy Single Channel Base Radio FRU Replacement Procedures


Replace suspected station modules with known non-defective modules to restore the station to proper operation. The following procedures provide FRU replacement instructions and post-replacement adjustments and/or verification instructions.

Legacy Single Channel Base Radio Replacement Procedure

Note The Legacy Base Radio removal and installation procedures are included for reference or buildout purposes. Field maintenance of Legacy Base Radios typically consists of replacement of FRUs within the Legacy Base Radio. Perform Legacy Base Radio FRU replacement in accordance with “Legacy Base Radio FRU Replacement Procedure” below.

Perform Legacy Base Radio (BR) replacement as described in the following paragraphs.

Removal

Remove BR from Equipment Cabinet as follows:

1. Remove power from the Base Radio by setting the Power Supply ON/OFF switch to the OFF position.

2. Tag and disconnect the cabling from the BR rear panel connectors.

3. Remove the four M6 TORX screws which secure the BR front panel to the Equipment Cabinet mounting rails.

! WARNING

br weight exceeds 60 lbs (27 kg). use two-person lift when removing or installing br from equipment cabinet. make certain BR is fully supported when br is free from mounting rails.

4. While supporting the BR, carefully remove the BR from the Equipment Cabinet by sliding the BR from the front of cabinet.

Installation

Install BR in Equipment Cabinet as follows:

1. If adding a BR, install side rails in the appropriate BR mounting position in the rack.


9-6 6880801E35-E 22-Mar-06


Legacy Single Channel Base Radio FRU Replace-

2. While supporting the BR, carefully lift and slide the BR in the Equipment Cabinet mounting position.

3. Secure the BR to the Equipment Cabinet mounting rails using four M6 TORX screws. Tighten the screws to 40 in-lb (4.5 Nm).

4. Connect the cabling to the BR rear panel connectors as tagged during the BR removal. If adding a BR, perform the required cabling in accordance with the Cabling Information subsection of the RFDS section applicable to the system.

5. Perform BR activation in accordance with the Legacy Single Channel BR Station Verification Procedures on page 9-9.

Anti-Static Precautions

CAUTIONThe Base Radio contains static-sensitive devices. when replacing Base Radio FRUs, always wear a grounded wrist strap and observe proper anti-static procedures to prevent electrostatic discharge damage to Base Radio modules.

Motorola publication 68P81106E84 provides complete static protection infor-mation. This publication is available through Motorola National Parts.

Observe the following additional precautions: Wear a wrist strap (Motorola Part No. 4280385A59 or equivalent) at all

times when servicing the Base Radio to minimize static build-up. A grounding clip is provided with each EBTS cabinet. If not available, use

another appropriate grounding point. DO NOT insert or remove modules with power applied to the Base Radio.

ALWAYS turn the power OFF using the Power Supply rocker switch on the front of the Power Supply module.

Keep spare modules in factory packaging for transporting. When shipping modules, always pack in original packaging.


22-Mar-06 6880801E35-E 9-7



Legacy BR FRU Replacement Procedure

Perform the following steps to replace any of the Legacy Base Radio FRUs:Note When servicing Legacy Base Radios (BRs) in situations where the

Control Board or the entire Legacy BR is replaced, the integrated Site Controller (iSC) will automatically reboot the serviced BR if the BR has been off-line for a period not less than the value contained in “Replacement BRC Accept Timer” (default is 3 minutes). If the BR is turned on prior to that time value, power the BR down and wait the minimum timer length before re-powering the BR.

1. Remove power from the Base Radio by setting the Power Supply rocker switch (located behind the front panel of the Power Supply) to the OFF (0) position.

2. Loosen the front panel fasteners. These are located on each side of the module being replaced.

3. Pull out the module.

4. Insert the non-defective replacement module by aligning the module side rails with the appropriate rail guides inside the Base Radio chassis.

5. Gently push the replacement module completely into the Base Radio chassis assembly using the module handle(s).

CAUTIONDO NOT slam or force the module into the chassis assembly. This will damage the connectors or backplane.

6. Secure the replacement module by tightening the front panel fasteners to the specified torque of 5 in-lbs.

7. Apply power to the Base Radio by setting the switch to the ON position.

8. Perform the Station Verification Procedure provided below.

Legacy Single Channel BR Power Amplifier (PA) Fan FRU Replacement

Perform the following steps to replace the Power Amplifier (PA) fans.

1. Remove the Power Amplifier from the Base Radio per FRU Replacement Procedure.

2. Disconnect fan power cable from PA housing.

3. Remove front panel from fan assembly.

4. Remove fan assembly from PA chassis. Note Reverse above procedure to install new fan kit.


9-8 6880801E35-E 22-Mar-06


Legacy Single Channel BR Station Verification Proce-

Legacy Single Channel BR Station Verification Procedures

Perform the Station Verification Procedures whenever you replace a FRU. The procedures verify transmit and receive operations. Each procedure also contains the equipment set-up.

Legacy Single Channel BR Replacement FRU Verification

All module specific information is programmed in the factory prior to shipment. Base Radio specific information (e.g., receive and transmit frequencies) is downloaded to the Base Radio from the network/site controller.

Replacement FRU alignment is not required for the Base Radio.

Legacy Single Channel BR Base Repeater FRU Hardware Revision Verification

Note The following procedure requires the Base Radio to be out of service. Unless the Base Radio is currently out of service, Motorola recommends performing this procedure during off-peak hours. This minimizes or eliminates disruption of service to system users.




The default factory set field password is motorola.Note The motorola password is a field password that is programmed during

manufacturing. The password will be changed by the Operations and Maintenance Center (OMC) as soon as the controller takes a download. The OMC default field password is Motorola.


f ie ld>dekeyf ie ld> test_modef ie ld>get brc_rev_nof ie ld>get rx1_rev_nof ie ld>get rx2_rev_nof ie ld>get rx3_rev_no (if BR is 3 branch)f ie ld>get pa_rev_nof ie ld>get ex_rev_no

f ie ld>


22-Mar-06 6880801E35-E 9-9




6. When all BRs have been checked, log out.

Legacy Single Channel BR Transmitter Verification

The transmitter verification procedure verifies the transmitter operation and the integrity of the transmit path. This verification procedure is recommended after replacing an Exciter, Power Amplifier, BRC, or Power Supply module.Note The following procedure requires the Base Radio to be out of service.

Unless the Base Radio is currently out of service, Motorola recommends performing this procedure during off-peak hours. This minimizes or eliminates disruption of service to system users.

Equipment Setup

To set up the equipment, use the following procedure:



3. Connect the other end of the RS-232 cable to the STATUS port located on the front panel of the BRC.

! CAUTION

Make sure power to BR is OFF before disconnecting transmitter RF connectors. Disconnecting transmitter RF connectors while the BR is keyed may result in RF burns from arcing.

4. Disconnect the existing cable from the connector labeled PA OUT. This connector is located on the backplane of the Base Radio.

5. Connect a test cable to the PA OUT connector.

6. Connect a 10 dB attenuator on the other end of the test cable.

7. From the attenuator, connect a cable to the RF IN/OUT connector on the R2660 Communications Analyzer.

8. Remove power from the R2660 and connect the Rubidium Frequency Standard 10MHZ OUTPUT to a 10 dB attenuator.


9-10 6880801E35-E 22-Mar-06



9. Connect the other end of the 10 dB attenuator to the 10MHZ REFERENCE OSCILLATOR IN/OUT connector on the R2660.

Note Refer to the equipment manual provided with the R2660 for further information regarding mode configuration of the unit (Motorola Part No. 68P80386B72).

10. Set the R2660 to the EXT REF mode.

11. Apply power to the R2660.

12. Set the R2660 to the SPECTRUM ANALYZER mode with the center frequency set to the transmit frequency of the Base Radio under test.

13. Perform the appropriate transmitter verification procedure below for the particular Power Amplifier used in the Base Radio.

Legacy Single Channel BR Transmitter Verification Procedure (40W, 800 MHz Power Amplifier – TLF2020)

This procedure provides commands and responses to verify proper operation of the transmit path for 800 MHz Base Radios using a 40 Watt Power Amplifier.

1. Apply power to the Base Radio by setting the switch to the 1 position. The following message displays on the service computer during power-up.

2. Enter the proper password. After entering the correct password, the field> prompt is displayed on the service computer. The default password is motorola

3. At the field> prompt, type: dekey This command verifies that there is no RF power being transmitted.

Base Radio

firmware revision RXX.XX.XX

Copyright © 1998Motorola, Inc. All rights reserved.

Unauthorized access prohibited

Enter login password:

field>dekeyXMIT OFF INITIATED


22-Mar-06 6880801E35-E 9-11



CAUTIONThe following command keys the transmitter. Make sure that transmission only occurs on licensed frequencies or into a RF load.

4. At the field> prompt, type: set tx_power 40

This command sets the transmitter output to 40 Watts.

After keying the Base Radio, verify the forward and reflected powers of the station along with the station VSWR with the parameters listed in Table 9-2.

5. At the field> prompt, type: get fwd_pwr

This command returns the current value of forward power from the RF Power Amplifier.

6. At the field> prompt, type: get ref_pwr

Table 9-2 Legacy BR 40W, 800 MHz PA Transmitter Parameters

Parameter Value or Range

Forward Power Greater than 38.0 Watts

Reflected Power Less than 4.0 Watts

VSWR Less than 2:1

f ield>set tx_power 40setting transmitter power to 40 watts

TXLIN ATTENUATION: 5.000000

TARGET POWER: 40.00 watts [46.02 dBm]

ACTUAL POWER: 37.77 watts [45.07 dBm]

POWER WINDOW: 38.20-> 41.89 watts [45.82 -> 46.22 dBm]TXLIN LEVEL REGISTER REDUCED 59 STEPS [-2.30 dB].

TXLIN LEVEL: 0x6f

completed successfully

field>get fwd_pwrFORWARD POWER is 39.13 watts [45.92 dBm]


9-12 6880801E35-E 22-Mar-06



This command returns the current value of reflected power from the RF Power Amplifier.

7. At the field> prompt, type: get vswr

This command calculates the current Voltage Standing Wave Ratio (VSWR) from the RF Power Amplifier.

8. At the field> prompt, type: get alarms

This command returns all active alarms of the Base Radio.

Note If the get alarms command displays alarms, refer to the System Troubleshooting section of this manual for corrective actions.

9. View the spectrum of the transmitted signal on the R2660 Communications Analyzer in the Spectrum Analyzer mode. Figure 9-3 shows a sample of the spectrum.

f ield> get ref_pwrREFLECTED POWER is 0.27 watts [24.28 dBm]

field>get vswrVSWR is 1.17:1

field> get alarmsNO ALARM CONDITIONS DETECTED


22-Mar-06 6880801E35-E 9-13



Figure 9-3 Transmitted Signal Spectrum (800 MHz Legacy BR)

10. At the field> prompt, type: dekey This command stops all transmitter activity.

EBTS071032394JNM

field> dekeyXMIT OFF INITIATED


9-14 6880801E35-E 22-Mar-06



Legacy Single Channel BR Transmitter Verification Procedure (70W, 800 MHz Power Amplifiers – CTF1040)

This procedure provides commands and responses to verify proper operation of the transmit path for 800 MHz Base Radios using a 70 Watt Power Amplifier.

1. Apply power to the Base Radio by setting the switch to the 1 position. The following message displays on the service computer during power-up.


3. At the field> prompt, type: dekey This command verifies that there is no RF power being transmitted.

CAUTIONThe following command keys the transmitter. Make sure that transmission only occurs on licensed frequencies or into an RF load.

4. At the field> prompt, type: set tx_power 70

Base Radio

firmware revision RXX.XX.XXCopyright © 1998

Motorola, Inc. All rights reserved.



field>dekeyXMIT OFF INITIATED


22-Mar-06 6880801E35-E 9-15



This command sets the transmitter output to 70 Watts.

After keying the Base Radio, verify the forward and reflected powers of the station along with the station VSWR with the parameters listed in Table 9-3.

5. At the field> prompt, type: get fwd_pwr

This command returns the current value of forward power from the RF Power Amplifier.

6. At the field> prompt, type: get ref_pwr

This command returns the current value of reflected power from the RF Power Amplifier.

7. At the field> prompt, type: get vswr

Table 9-3 Legacy BR 70W, 800 MHz PA Transmitter Parameters


Forward Power Greater than 66.5 Watts


VSWR Less than 2:1

f ield>set tx_power 70setting transmitter power to 70 watts

TXLIN ATTENUATION: 5.000000

TARGET POWER: 70.00 watts [48.45 dBm]

ACTUAL POWER: 56.70 watts [47.54 dBm]POWER WINDOW: 66.85 -> 73.30 watts [48.25 -> 48.65 dBm]

TXLIN LEVEL REGISTER REDUCED 85 STEPS [-3.32 dB].

TXLIN LEVEL: 0x55

completed successfully

field>get fwd_pwrFORWARD POWER is 68.55 watts [48.36 dBm]

field>get ref_pwrREFLECTED POWER is 2.10 watts [33.22 dBm]


9-16 6880801E35-E 22-Mar-06



This command calculates the current Voltage Standing Wave Ratio (VSWR) from the RF Power Amplifier.

8. At the field> prompt, type: get alarms


Note If the get alarms command displays alarms, refer to the System Troubleshooting section of this manual for corrective actions.


Figure 9-4 Transmitted Signal Spectrum (800 MHz Legacy BR)

f ield>get vswrVSWR is 1.42:1

field>get alarmsNO ALARM CONDITIONS DETECTED

EBTS071032394JNM


22-Mar-06 6880801E35-E 9-17



10. At the field> prompt, type: dekey This command stops all transmitter activity.

Legacy Single Channel BR Receiver Verification

The receiver verification procedure sends a known test signal to the Base Radio to verify the receive path. This verification procedure is recommended after replacing a Receiver, BRC, or Power Supply module.Note The following procedure requires the Base Radio to be out of service.


Equipment Setup

Set up the equipment for the receiver verification procedure as follows:




4. Disconnect the existing cable from the connector labeled RX1 (or the connector corresponding to the receiver under test).This connector is located on the backplane of the Base Radio.

5. Connect a test cable to the RX 1 connector.

6. Connect the other end of the test cable to the RF IN/OUT connector on the R2660 Communications Analyzer.




10. Apply power to the R2660.Note Refer to the equipment manual provided with the R2660 for further

information regarding mode configuration of the unit (Motorola Part No. 68P80386B72).

f ield>dekeyXMIT OFF INITIATED


9-18 6880801E35-E 22-Mar-06



11. Set the R2660 to the receive frequency of the Base Radio under test.All receivers within a single Base Radio have the same receive frequency.

12. Set the R2660 to generate the test signal at an output level of -80dBm.

Receiver Verification Procedure

This procedure provides commands and responses to verify proper operation of the Base Radio receive path. Perform the procedure on all three receivers in each Base Radio in the EBTS.

The Bit Error Rate (BER) measurement meets specifications at less than 0.01% (1.0e-02%) to pass the process.

Before you begin the verification procedure, put the Base Radio into the test mode of operation to take it out of service. Enable the desired receiver under test and disable the other receiver(s). In this case the receiver under test is receiver #1.

In the following procedures, enter the software commands as they appear after the prompt. These commands are in bold letters.

For example, field> get rx_freq

13. Restore power to the Base Radio by setting the Power Supply rocker switch to the ON (1) position.The following message displays on the service computer during power-up.


15. At the field> prompt, type: get rx_freq

This command displays the receive frequency for the current Base Radio. For 800/900/1500 MHz Base Radios, the message respectively appears as:

Base Radio

firmware revision RXX.XX.XXCopyright © 1998

Motorola, Inc. All rights reserved.




22-Mar-06 6880801E35-E 9-19



800 MHz BR:

16. Verify that the R2660 transmit frequency is set to the frequency determined in the previous step.

17. At the field> prompt, type: set rx_mode 1

This command is used to enable the antenna/receiver under test.

18. At the field> prompt, type: get rssi 1 1000

This commands returns the receive signal strength indication. To pass the BER floor test, the Bit Error Rate must be less than 0.01% (1.0e-02%) for the displayed results.

19. Verify that the RSSI dBm signal strength, for the receiver under test, is -80.0 dBm ± 1.0 dBm. Adjust the R2660 signal output level to get the appropriate RSSI dBm level. The BER floor% value is valid only if the RSSI signal strength is within the limits of -81.0 dBm to -79.0 dBm.

20. At the prompt, type: get alarms


Note If the get alarms command displays alarms, refer to the System Troubleshooting section for corrective actions.

f ield> get rx_freqThe RX FREQUENCY is: 806.00000

field>set rx_mode 1set RECEIVER 1 to ENABLED in RAMset RECEIVER 2 to DISABLED in RAM

set RECEIVER 3 to DISABLED in RAM

field>get rssi 1 1000Starting RSSI monitor for 1 repetit ions averaged each 1000 reports.

Line RSSI1 RSSI2RSSI3SGC C IBEROffset Sync Miss

dBm dBm dBm dB dBm dBm %Hz %

---- ------ ------ ------ ---- ----- - ------ --

field>get alarmsNO ALARM CONDITIONS DETECTED


9-20 6880801E35-E 22-Mar-06



21. At the field> prompt, type: get rx1_kit_no

As shown below respectively for 800 /900/1500 MHz Base Radios, this command returns the kit number of the receiver.800 MHz BR:

Note If the kit number is CRF6010 or CRF6030, continue to step 22., otherwise to Equipment Disconnection.

22. At the field> prompt, type: get rx_fru_config

This command lists the receivers active for diversity.

Note If the antenna configuration does not match the receiver configuration, use the set rx_fru_config MMI command to properly set the parameter.

Equipment Disconnection

Disconnect equipment after verifying the receiver as follows:


2. Disconnect the RS-232 cable from the connector on the service computer.

3. Disconnect the other end of the RS-232 cable from the RS-232 connector on the front panel of the BRC.

4. Disconnect the test cable from the RX 1 connector located on the backplane of the Base Radio.

5. Connect the standard equipment cable to the RX 1 connector.

6. Disconnect the cable to the R2660 Communications Analyzer.

7. Restore power to the Base Radio by setting the Power Supply rocker switch to the ON (1) position.This completes the Receiver Verification Procedure for the receiver under test.

Repeat the Receiver Verification Procedure for each receiver in every Base Radio in the EBTS.

f ield> get rx1_kit_noRECEIVER 1 KIT NUMBER IS CRF6010A

field> get rx_fru_configRECEIVER CONFIGURATION RX1 RX2 RX3


22-Mar-06 6880801E35-E 9-21


Legacy Single Channel Base Radio Backplane


Legacy Single Channel BR Backplane Connectors

All external equipment connections are made on the Base Radio backplane. Table 9-4 lists and describes each of the connectors on the backplane.

Table 9-4 Legacy Base Radio Backplane Connectors

Connector Description Type

RX 1 through RX 3

Provides the input path for the received signal to the Base Radio. Each receiver has an input for one of these signals.Connect these ports to a multicoupler distribution system and surge protection circuitry before connecting them to the receive antennas.

RF-type connector in Table 9-26

EX OUT/EX FBPA IN/PA FB

Connects the exciter and PAs together to form the transmitter for the Base Radio. These connections are usually made at the factoryThese four ports close the feedback loop between these two modules by connecting EX OUT to the PA IN and the EX FB to the PA FB

RF-type connectors in

Table 9-38 and Table 9-40

PA OUTTransmits the RF output of the Base Radio. Connect this port to a combiner or duplexer before connecting to the transmit antenna

RF-type connector in Table 9-40

ETHERNET A (or labeled ETHERNET on some production units)

Provides Ethernet connectivity to the Base Radio from the site controller. This Ethernet port connects directly to the BRC

BNC-type connector in Table 9-36

5MHZ/ 1 PPS-A (or labeled SPARE on some production units)

Serves as both the timing and frequency reference port for the Base RadioThis port is connected to the site timing/frequency reference.

BNC-type connector in Table 9-39

RS-232 This is a DTE RS-232 interface provided for future use and is not currently enabled

DB-9-type connectors in Table 9-329

ALARM

Provides the connection for external calibrated power monitors to the Base RadioThis connector also provides station DC voltages and programming lines (SPI) for monitoring/potential future expansion

DB-25-type connector


9-22 6880801E35-E 22-Mar-06



Figure 9-5 shows the locations of the Legacy Base Radio external connec-tions.

Figure 9-5 Legacy Base Radio Backplane Connectors

AC POWER Provides connection to AC power supply, if the Base Radio is equipped with an AC power supply

Line cord connector

DC POWERProvides DC power connection, if the Base Radio is equipped with a DC power supply or an AC power supply to support the battery revert feature

Card edge connector

GROUND

Connects the station to ground. A ground stud and a ground braid on the back of the Base Radio connect the station to a site ground, such as an appropriately grounded cabinetThis ground provides increased transient/surge protection for the station

Ground stud

Table 9-4 Legacy Base Radio Backplane Connectors (continued)

Connector Description Type

EX OUT

PA IN

EX

PA FB

DC POWER

AC POWER

RS 232ALARM5MHZ/1 PPS B

RX 1

RX 2

RX 3

5MHZ/1 PPS A

ETHERNET A

PA OUT

GROUND

EBTS327021997JNM

RE BLACK

This port must be terminated by 50Ω load when configured for2 Branch Diversity. Also, the rx_fru_config parameter must be set to R12.

*

*


22-Mar-06 6880801E35-E 9-23



Legacy Single Channel BR Backplane RF Connections

When Base Radios are shipped from the factory as FRUs, each connection on the back of a repeater has a designated color dot beside it as listed in Table 9-5. To find where a cable should be connected, match the label wrapped around the cable to the dot on the back of the repeater.

Legacy Single Channel BR Backplane Connector Pinouts

Table 9-6 lists the pin-outs for the 96-pin P1 connector of the Base Radio Controller board.

Table 9-5 Legacy BR RF Connector Code

Connectors Color Dot Code

TX Orange

RX 1 Red

RX 2 Green

RX 3 Yellow

Ethernet White

5 MHz/1 pps A or Spare Gray

Table 9-6 Legacy BR P1 Connector Pin-outs

Pin No. Row A Row B Row C

1 AGC3 14.2V AGC1

2 AGC4 14.2V AGC2

3 GND GND GND

4 RESET GND GND

5 BATT_STAT GND GND

6 CTS GND GND

7 RTS 5V 5V

8 5V 5V 5V

9 5V 5V 5V

10 SHUTDOWN 5V

11 RCLK 5V DATA1

12 ODC_1 5V DATA1*

13 TCLK GND DATA3

14 ODC_3 GND DATA3*


9-24 6880801E35-E 22-Mar-06



Table 9-7 lists the pin-outs for the 96-pin P1 connector for Receiver 1.

15 RXD GND DATA2

16 ODC_2 DATA2*

17 TXD

18 SSI SBI_1

19 SSI* SBI_3

20 BRG GND SBI_2

21 CLK

22 CLK* GND A4

23 GND A3

24 A5 GND A2

25 A0 GND A1

26 CD GND 5MHZ/SPARE

27 METER_STAT GND SPI_MISO

28 WP* GND SPI_CLK

29 GND GND SPI_MOSI

30 GND GND GD

31 1PPS_GPS GND 2.1MHZ_TX

32 GND GND 2.1MHZ_RX

Note * = Enabled low



1 AGC3 GND AGC1

2 AGC4 GND AGC2

3 GND GND GND

4 GND GND GND

5 14.2V 14.2V 14.2V

6 14.2V 14.2V 14.2V




22-Mar-06 6880801E35-E 9-25



7 GND GND GND

8 GND GND GND

9 5V 5V 5V

10 5V 5V 5V

11 GND GND GND

12 GND GND GND

13 DATA1* GND GND

14 DATA1 GND GND

15 ODC_1 GND GND

16 GND GND GND

17 GND GND GND

18 SBI_1 GND GND

19 GND GND GND

20 GND GND GND

21 A0_CS1

22 A1_CS2

23 A5

24 WP*

25 A4_RXSEL

26

27 SPI_MISO

28 SPI_MOSI

29 SPI_CLK

30 GND GND GND

31 GND GND GND



Table 9-7 Legacy BR P1 Connector Pin-outs (continued)



9-26 6880801E35-E 22-Mar-06






1 AGC3 GND AGC1

2 AGC4 GND AGC2

3 GND GND GND

4 GND GND GND

5 14.2V 14.2V 14.2V

6 14.2V 14.2V 14.2V

7 GND GND GND

8 GND GND GND

9 5V 5V 5V

10 5V 5V 5V

11 GND GND GND

12 GND GND GND

13 DATA2* GND GND

14 DATA2 GND GND

15 ODC_2 GND GND

16 GND GND GND

17 GND GND GND

18 SBI_2 GND GND

19 GND GND GND

20 GND GND GND

21 A0_CS1

22 A1_CS2

23 A5

24 WP*

25 A3_RXSEL

26

27 SPI_MISO

28 SPI_MOSI


22-Mar-06 6880801E35-E 9-27




29 SPI_CLK

30 GND GND GND

31 GND GND GND





1 AGC3 GND AGC1

2 AGC4 GND AGC2

3 GND GND GND

4 GND GND GND

5 14.2V 14.2V 14.2V

6 14.2V 14.2V 14.2V

7 GND GND GND

8 GND GND GND

9 5V 5V 5V

10 5V 5V 5V

11 GND GND GND

12 GND GND GND

13 DATA3* GND GND

14 DATA3 GND GND

15 ODC_3 GND GND

16 GND GND GND

17 GND GND GND

18 SBI_3 GND GND

19 GND GND GND

20 GND GND GND




9-28 6880801E35-E 22-Mar-06



Table 9-10 lists the pin-outs for the 48-pin P2 connector of the 3X Receiver.

21 A0_CS1

22 A1_CS2

23 A5

24 WP*

25 A2_RXSEL

26

27 SPI_MISO

28 SPI_MOSI

29 SPI_CLK

30 GND GND GND

31 GND GND GND




Pin No. Row A Row B Row C Row D

1 GND AGC4 AGC3 GND

2 GND AGC2 AGC1 A0

3 GND RX1_DATA RX1_DATA A1

4 GND RX1_SBI RX1_ODC A2


6 5V RX2_SBI RX2_ODC A4


8 GND RX3_SBI RX3_ODC WP*

9 14.2V SCLK MOSI MISO

10 14.2V GND GND GND




22-Mar-06 6880801E35-E 9-29



Table 9-11 lists the pin-outs for the 16-pin P3 connector of the 3X Receiver.

Table 9-12 lists the pin-outs for the 96-pin P5 connector of the Exciter.

11 14.2V GND REF GND

12 GND GND GND GND

Note Row A is make first, break last.


Pin No. Row A Row B Row C Row D Row E

1 GND GND GND

2 RX1

3 GND GND GND

4

5

6

7 GND GND GND

8 RX2 RX3

9 GND GND GND



1 28V 28V 28V

2 28V 28V 28V

3 14.2V 14.2V 14.2V

4 14.2V 14.2V 14.2V

5 5V 5V 5V

6 5V 5V 5V

7 GND GND EXT_VFWD

8 GND GND EXT_VREF

9

10 GND GND GND


Pin No. Row A Row B Row C Row D


9-30 6880801E35-E 22-Mar-06



11 GND GND VBLIN

12 GND GND RESET

13

14 GND GND GND

15 GND GND SPI_MISO

16 A0 GND GND

17 GND GND SPI_CLK

18 A1 GND WP*

19 GND GND GND

20 A5 GND SPI_MOSI

21 GND GND GND

22 A4 GND GND

23 GND GND CLK*

24 A3 GND GND

25 GND GND CLK

26 GND GND GND

27 GND GND SSI*

28 GND GND GND

29 GND GND SSI

30 GND GND GND

31 GND GND 2.1MHz_TX

32 GND GND GND

Note * = enabled low




22-Mar-06 6880801E35-E 9-31



Table 9-13 lists the pin-outs for the 96-pin P6 connector of the Power Amplifier.



1 VBLIN GND 28V

2 GND GND 28V

3 A0 GND 28V

4 GND GND 28V

5 A1 GND 28V

6 GND GND 28V

7 A2 GND 28V

8 GND GND 28V

9 A3 GND 28V

10 GND GND 28V

11 SPI_MISO GND 28V

12 GND GND 28V

13 SPI_MOSI GND 28V

14 GND GND 28V

15 SPI_CLK GND 28V

16 GND GND 28V

17 WP* GND 28V

18 GND GND 28V

19 GND GND 28V

20 GND GND 28V

21 GND GND 28V

22 GND GND 28V

23 GND GND 28V

24 GND GND 28V

25 GND 5V 28V

26 GND 5V 28V

27 GND 14.2V 28V


9-32 6880801E35-E 22-Mar-06



Table 9-14 lists the pin-outs for the 25-pin P7 Alarm connector.

28 GND 14.2V 28V

29 GND 14.2V 28V

30 GND 14.2V 28V

31 GND 28V 28V

32 GND 28V 28V



Pin No. Signal

1 SPI_MISO

2 SPI_MOSI

3 SPI_CLK

4 A0

5 A1

6 A2

7 A3

8 A4

9 A5

10 GND

11 28V

12 14.2V

13 14.2V

14 WP*

15 5V

16 GND

17 BATT_STAT

18 MTR_STAT

19 EXT_VFWD




22-Mar-06 6880801E35-E 9-33



Table 9-15 lists the pin-outs for the 9-pin P8 RS-232 connector.

Table 9-16 lists the pin-outs for P13. Table 9-17 through Table 9-20 list the pin-outs for the SMA and blindmate connectors for Receivers 1- 3, BRC, Exciter and PA.

20 EXT_VREF

21 GND

22 GND

23 BAT_TEMP

24 VAT_TEMP

25 GND



Pin No. Signal

1 CD

2 RxD

3 TxD

4 RCLK

5 GND

6 TCLK

7 RTS

8 CTS

9 BRG


Connector Signal

1 ETHERNET - A (or 5MHZ IN*)

Note * May appear as indicated in parenthesis on some production units.


Pin No. Signal


9-34 6880801E35-E 22-Mar-06



Table 9-21 lists the pin-outs for 78-pin P9 connector of the Power Supply.

Table 9-17 Legacy BR SMA Connectors- Receivers

Connector Signal

P19 RCV ONE RF IN

P20 RCV TWO RF IN

P21 RCV THREE RF IN

Table 9-18 Legacy BR Blind Mates - BRC

Connector Signal

P10 SPARE* (or 5MHZ/1 PPS - A)

P11 ETHERNET* (or ETHERNET - A)


Table 9-19 Legacy BR Blind Mates - Exciter

Connector Signal

P14 EXCITER OUT

P15 EXCITER FEEDBACK

Table 9-20 Legacy BR Blind Mates - PA

Connector Signal

P16 PA FEEDBACK

P17 PA IN

P18 PA RF OUT


Pin No. Signal

1 GND

2 GND

3 28V

4 28V

5 28V

6 28V

7 28V


22-Mar-06 6880801E35-E 9-35



8 28V

9 28V

10 28V

11 28V

12 28V

13 28V

14 28V

15 28V

16 14.2V

17 14.2V

18 14.2V

19 14.2V

20 14.2V

21 14.2V

22 14.2V

23 14.2V

24 5V

25 5V

26 5V

27 5V

28 5V

29 5V

30 5V

31 5V

32 GND

33 GND

34 GND

35 GND

36 GND


Pin No. Signal


9-36 6880801E35-E 22-Mar-06



37 GND

38 GND

39 GND

40 GND

41 GND

42 GND

43 GND

44 GND

45 GND

46 GND

47 GND

48 GND

49 GND

50 GND

51 GND

52 GND

53 GND

54 SCR_SHUT

55 SCR_THRESH

56 RELAY_ENABLE

57 SHUTDOWN

58 28V_AVG

59 BATT_TEMP

60 SPI_MISO

61 SPI_MOSI

62 SPI_CLK

63

64

65


Pin No. Signal


22-Mar-06 6880801E35-E 9-37



66

67 A0(CS1)

68 A1(CS2)

69 A5

70

71 A4

72

73 A3

74 GND

75 A2

76 GND

77 GND

78 GND


Pin No. Signal


9-38 6880801E35-E 22-Mar-06



Legacy Single Channel Base Radio Signals

Table 9-22 lists and describes the Base Radio signals.

Table 9-22 Legacy Base Radio Signal Descriptions

Signal Name Signal Description

GND Station ground

28V 28VDC

14.2V 14.2VDC

5.1V 5.1 VDC

A0,A1,A2,A3,A4,A5 The BRC uses these lines to address station modules and devices on those modules

SPI_MOSI Serial Processor Interface - Master out slave in Data

SPI_MISO Serial Processor Interface - Master in slave out Data

SPI_CLK Serial Processor Interface - Clock signal (100 KHz - 1 MHz)

AGC1, AGC2, AGC3, AGC4

BRC uses these lines to set the digital attenuator's on the receiver(s) for SGC functionality

2.1MHz_RX 2.1MHz generated on the BRC and used as a reference by the Receiver(s)

2.1MHz_TX 2.1MHz generated on the BRC and used as a reference by the Exciter

DATA1, DATA1* This differential pair carries receiver 1 data to the Base Radio Controller

DATA2 DATA2* This differential pair carries receiver 2 data to the Base Radio Controller

DATA3, DATA3* This differential pair carries receiver 3 data to the Base Radio Controller

ODC_1, ODC_2, ODC_3

Clocks used to clock differential receive data from each respective receiver to the BRC

SBI_1, SBI_2, SBI_3 Serial Bus Interface - These lines are used to program the custom receiver IC on each receiver

SSI, SSI* Differential transmit data from the Exciter to the BRC

CLK, CLK* Differential Data clock used to clock transmit data from the BRC to the Exciter

BRC/BLIN Programmable bias voltage generated on the Exciter and used to bias the Power amplifier devices


22-Mar-06 6880801E35-E 9-39



VBLIN Programmable bias voltage generated on the Exciter and used to bias the Power amplifier devices

RESET Output from BRC to Exciter (currently not used)

EXT_VFWD DC voltage representing the forward power at the antenna as measured by the external wattmeter

EXT_VREF DC voltage representing the reflected power at the antenna as measured by the external wattmeter

WP* Write protect line used by the BRC to write to serial EEPROMs located on each module

BAT_STAT Binary flag used to signal BRC to monitor the External battery supply alarm

METER_STAT Binary flag used by the BRC to indicate to the BRC it should monitor

1PPSGlobal Positioning System - 1 pulse per second (this may be combined with 5MHz at the site frequency reference

RCLK RS-232 - Receive clock

TCLK RS-232 - Transmit clock

CTS RS-232 - Clear to send

RTS RS-232 - Request to send

CD RS-232 - Carrier detect

RXD RS-232 - Receive data

TXD RS-232 - Transmit data

BRG RS-232 - Baud rate generator

5MHz / Spare signal currently not used

EXCITER_OUT Forward transmit path QQAM at approximately a 11dBm level

EXCITER_FEEDBACK

Signal comes from the PA at approximately a 16dBm. Used to close the cartesian RF_LOOP

PA_IN 4 dBm QQAM forward path of the transmitter

PA_FEEDBACK Signal to the Exciter at approximately 16dBm. Used to close the cartesian RF_LOOP

RX1_IN RF into Receiver 1

Table 9-22 Legacy Base Radio Signal Descriptions (continued)



9-40 6880801E35-E 22-Mar-06





5MHZ REFERENCE

5MHz station/site reference. Signal comes from the redundant site frequency reference and usually is multiplexed with the 1PPS signal from the global positioning satellite input to the site frequency reference

ETHERNET Interface between the BRC and the ACG. This connects the Base to the 10 MHz LAN

SCR_SHUT Signal currently not used

SCR_THRESH Signal currently not used

RELAY ENABLE Signal currently not used

SHUTDOWN Input signal from the BRC to the Power supply. Used to exercise a station “hard start”

28V_AVG Signal currently not used

BATT_TEMPDC voltage from the external batteries used to represent the temperature of the batteries. Signal used only with AC power supplies


Table 9-22 Legacy Base Radio Signal Descriptions (continued)



22-Mar-06 6880801E35-E 9-41


Generation 2 Single Channel Base Radio FRU Replacement Procedures


Replace suspected station modules with known non-defective modules to restore the station to proper operation. The following procedures provide FRU replacement instructions and post-replacement adjustments and/or verification instructions.

Generation 2 Single Channel Base Radio Replacement Procedure

Note The Base Radio removal and installation procedures are included for reference or buildout purposes. Field maintenance of Base Radios typically consists of replacement of FRUs within the Base Radio. Perform Base Radio FRU replacement in accordance with “Base Radio FRU Replacement Procedure” below.

Perform Base Radio (BR) replacement as described in the following paragraphs.

Removal

Remove BR from Equipment Cabinet as follows:




! WARNING

br weight exceeds 60 lbs (27 kg). use two-person lift when removing or installing br from equipment cabinet. make certain BR is fully supported when br is free from mounting rails.

4. While supporting the BR, carefully remove the BR from the Equipment Cabinet by sliding the BR from the front of cabinet.

Installation




9-42 6880801E35-E 22-Mar-06


Generation 2 Single Channel Base Radio FRU Re-



4. Connect the cabling to the BR rear panel connectors as tagged during the BR removal. If adding a BR, perform the required cabling in accordance with the Cabling Information subsection of the RFDS section applicable to the system.

5. Perform BR activation in accordance with the Generation 2 Single Channel BR Station Verification Procedures on page 9-45.


CAUTIONThe Base Radio contains static-sensitive devices. When replacing Base Radio FRUs, always wear a grounded wrist strap and observe proper anti-static procedures to prevent electrostatic discharge damage to Base Radio modules.








22-Mar-06 6880801E35-E 9-43



FRU Replacement Procedure

Perform the following steps to replace any of the Base Radio FRUs:Note When servicing Base Radios (BRs) in situations where the Control

Board or the entire BR is replaced, the integrated Site Controller (iSC) will automatically reboot the serviced BR if the BR has been off-line for a period not less than the value contained in “Replacement BRC Accept Timer” (default is 3 minutes). If the BR is turned on prior to that time value, power the BR down and wait the minimum timer length before re-powering the BR.






CAUTIONDO NOT slam or force the module into the chassis assembly. This will damage the connectors or backplane.



8. Perform the Station Verification Procedure provided below.

Generation 2 Single Channel BR Power Amplifier (PA) Fan FRU Replacement





4. Remove fan assembly from PA chassis. Note Reverse above procedure to install new fan kit.


9-44 6880801E35-E 22-Mar-06


Generation 2 Single Channel BR Station Verification

Generation 2 Single Channel BR Station Verification Procedures

Perform the Station Verification Procedures whenever you replace a FRU. The procedures verify transmit and receive operations. Each procedure also contains the equipment set-up.

Generation 2 Single Channel BR Replacement FRU Verification

All module specific information is programmed in the factory prior to shipment. Base Radio specific information (e.g., receive and transmit frequencies) is downloaded to the Base Radio from the network/site controller.

Replacement FRU alignment is not required for the Base Radio.

Generation 2 Base Repeater FRU Hardware Revision Verification

Note The following procedure requires the Base Radio to be out of service. Unless the Base Radio is currently out of service, Motorola recommends performing this procedure during off-peak hours. Performing this procedure then minimizes or eliminates disruption of service to system users.


2. Connect the other end of the RS-232 cable to the Service Access port, located on the front panel of the CNTL module.

3. After the BR is powered up using the front switch on the Power Supply Module, press the reset button on the Control Module front panel. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the field password, log in to the BR.To enter field mode, at the > prompt type login -ufield.

After entering the correct field password, the f ie ld> prompt is displayed on the service computer.


manufacturing. The password will be changed by the Operations and Maintenance Center (OMC) as soon as the controller takes a download. The OMC default field password is Motorola.The default factory set field password is motorola.

f ield>login -ufieldpassword:<login password>

field>


22-Mar-06 6880801E35-E 9-45





6. Set desired cabinet id and position and of BR by typing the following commands, with the final number on each command being the desired cabinet id and position. The command example below sets cabinet id to 5, and cabinet position to 2.

7. After checking all BRs, log out by keying the following command:

f ield>fv -oplatformf ield>

field>ci -oplatform -c5f ield> pi -oplatform -p2

f ield>

field>logoutf ield>


9-46 6880801E35-E 22-Mar-06



Generation 2 Transmitter Verification



Equipment Setup




3. Connect the other end of the RS-232 cable to the Service Access port located on the front panel of the BRC.


! CAUTION



6. Connect a 10 dB attenuator on the other end of the test cable.








22-Mar-06 6880801E35-E 9-47





Transmitter Verification Procedure

This procedure provides commands and responses to verify proper operation of the transmit path for 800 MHz Base Radios.

1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the Control Module front panel. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the field password, login to the BR.

To enter field mode, at the > prompt type login -ufield.




2. Dekey the BR to verify that no RF power is being transmitted. Set the transmit DSP test mode to “stop.” At the field> prompt, type:

Note The following command keys the transmitter. Make sure that transmission only occurs on licensed frequencies or into an RF dummy load.

f ie ld> login -ufieldpassword:<login password>

field>

f ield> power -otxch1 -p0

f ie ld> ptm -otx_all -mstop


9-48 6880801E35-E 22-Mar-06



3. Key the BR to 40 watts, following the steps below from the field> prompt: a) Set the transmitter frequency.

b) Enable the channel by setting a data pattern to “iden”

Note After the following command is entered, power will be transmitted at the output of the Power Amplifier.

c) Set the transmit power to 40 watts and key the BR.

4. After keying the Base Radio, verify the forward and reflected powers of the station along with the station VSWR with the parameters listed in Table 9-23.

Note The reported value for forward power is not indicative of Base Radio performance. This value is reported from the internal wattmeter. These limits are only for verification of operation and are not representative of true operating power of the transmitter.

a) At the field> prompt, type:


Table 9-23 Generation 2 BR Transmitter Parameters


Forward Power Greater than 36 Watts


VSWR Less than 2:1

f ie ld> freq -otxch1 -f860

f ie ld> dpm -otxch1 -miden

f ie ld> ptm -otx_all -mdnlk_framed

f ie ld> power -otxch1 -p40

f ield> power -otx_all


22-Mar-06 6880801E35-E 9-49



b) At the field> prompt, type:

If the alarms command displays alarms, refer to the System Troubleshooting section of this manual for corrective actions.


Figure 9-6 Generation 2 Carrier Spectrum

f ield> alarms -ofault_hndlr

EBTS071032394JNM


9-50 6880801E35-E 22-Mar-06



6. Dekey the BR to verify no RF power is being transmitted. Set the transmit DSP test mode to “stop.” At the field> prompt, type:


Use the following steps to disconnect equipment after verifying the trans-mitter.



3. Disconnect the other end of the RS-232 cable from the RS-232 connector located on the front panel of the BRC.

! CAUTION


4. Disconnect the test cable from the PA OUT connector located on the backplane of the Base Radio.

5. Connect the standard equipment cable to the PA OUT connector.

6. Disconnect the 10 dB attenuator from the other end of the test cable.

7. From the attenuator, disconnect the cable to the R2660 Communications Analyzer.

8. Restore power to the Base Radio by setting the Power Supply rocker switch to the ON (1) position.

9. If necessary, continue with the Receiver Verification Procedure.


f ield> ptm -otx_all -mstop


22-Mar-06 6880801E35-E 9-51



Receiver Verification Procedure: Generation 2 Base Radio with RFDS

This procedure provides commands and responses to verify proper operation of the Base Radio receiver paths. Perform the procedure on all four channels in each Base Radio in the EBTS.

1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the front of the EX/BRC module. Using the terminal program on the service computer, log onto the BR. Bold type indicates user input commands.





2. Set the Frequency of the R2660 to 810MHz. Power out should be set to –80 dBm.

3. Set the channel frequency.

4. Verify the R2660 signal level:


field>

field>freq -orxch1 -f810

f ield>enable -orxch1 -dbr1 -sonf ield>ppc -orxch1 -mchn -s1f ield>ppr -orxch1 -r1 -a50


9-52 6880801E35-E 22-Mar-06



5. The resulting output will look similar to this:

Note RX Path1 RSSI must read -80dBm ±1dB for the BER Floor verification to be accurate. Adjust the output level of the R2660 to compensate for loss in the test cables and three-way splitter.

BER Floor Measurement: Generation 2 Base Radio with RFDS

1. Verify that the R2660 is set to 810MHz and is producing a power level of -80dBm. (See Receiver Verification Procedure: Generation 2 Base Radio with RFDS on page 9-52.)

2. Using the MMI commands below, issue the command to put the BR into single branch mode. If the resulting bit error rate for receiver branches 1, 2, and 3 is less than 0.01%, the receiver has passed the test.

f ield>ppr -orxch1 -r1 -a100

SGC Atten.(dBm)=0.000000

Freq. Offset=-15.059323

Sync. Attempts=1.000000Sync. Successes=1.000000

BER%=0.000000

RX Path1 RSSI=-80.934021RX Path2 RSSI=-127.012520

RX Path3 RSSI=-127.012520

Chn sig. strength=-57.098698Chn intf. strength=-91.696739

field>


22-Mar-06 6880801E35-E 9-53



3. Check Receiver 1. At the prompt, type (inputs are in bold, comments are in italics):

4. Enter the command to return all active alarms of the Base Radio. At the prompt, type:

Note If the command displays alarms, refer to the System Troubleshooting section for corrective actions.

5. As shown below respectively for 800 MHz Generation 2 Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the field > prompt, type:

f ield> freq -orxch1 -f810

f ield> enable -orxch1 -soff

f ield> enable -orxch1 -dbr1 -son

field> ppr -orxch1 -a1000 -r1



f ield> ppr -orxch1 -a1000 -r1

(skip the step below i f the system is conf igured for 2 Branch Diversi ty)


f ield> enable -orxch1 -db3 -son


f ield>alarms -ofault_hndlr

f ield>fc –oplatform


9-54 6880801E35-E 22-Mar-06



Receiver Sensitivity Measurement: Generation 2 Base Radio with RFDS

The receiver sensitivity measurement consists of sending a calibrated RF level of -113.5dBm to the antenna ports at the top of the rack. This includes the RFDS in the receive channel and measures the combined performance of the Base Radio and the RFDS. The R2660 output must be calibrated prior to the taking of this measurement.

Calibration of the R2660 output level

1. Verify that the R2660 is set to 810MHz and adjust the output power to a level of -50dBm

2. Calibrate HP438A Power Meter. Refer to the HP users guide that came with the Meter. Below is a general procedure that can be followed.

a) Attach 8481D Power Sensor to the Sensor input on the front of the 437B.

b) Attach the included HP 11708A 30dB pad to the Power input on the front on the 473B.

c) Power on the 437B.d) Connect the Power Meter to the female end of the 30dB pad extruding

from the Power input.e) Press the “Zero” button on the 437B.f) Wait for Zeroing operation to complete.g) Press “Shift-Zero” to enter the Cal value. This is listed as CF on the

Power Sensor.h) Wait for Cal operation to complete.i) Press “Shift-Freq” to enter the Cal Factor. This is listed as Cf in a chart

vs. freq on the Power Sensor. Choose the closest frequency range for the application. For 800MHz measurements, interpolate between 1.0GHz and 0.5GHz to obtain a Cf of 99.0

j) For measurement of iDEN or Tornado 6:1 waveforms, press “Offset” and enter 7.78dB.

3. Disconnect Cable A (see Figure 9-7) from the Base Radio and connect it to the Power Sensor Head.


22-Mar-06 6880801E35-E 9-55



Figure 9-7 Generation 2 BR w/ RFDS Verification Test Setup

4. Increase the power level on the R2660 until the HP 437B Power Meter reads -50dB.

5. Record the DISPLAYED power level of the R2660 as Calfactor A.

6. The path loss through the cable and splitter system is Calfactor A + 50.

Example: R2660 reads -44dBmHP 437B reads -50dBmCalfactor A = -44, path loss = 6dB

7. Path loss must be determined for each Antenna cable A,B,C (see Figure 9-7). If comparable cables are used for all three the path losses of all three should be the same.

8. Additional power will be added to the R2660 in the sensitivity measurement to balance out the additional path loss value.

9. Reconnect cables A,B,C (see Figure 9-7) to Antenna Ports 1,2,3.


9-56 6880801E35-E 22-Mar-06



10. Set the R2660 to Frequency 810MHz and a Power level of -113.5dBm + path loss.

Example: If your path loss was 6dB, set the R2660 to-107.5dBm.













f ield> enable -orxch1 -db3 -son


f ield>alarms -ofault_hndlr


22-Mar-06 6880801E35-E 9-57



13. As shown below respectively for 800 MHz Generation 2 Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the prompt, type:

Receiver Verification: Measurement of the Generation 2 Base Radio (No RFDS)

The receiver verification procedure sends a known test signal into the Base Radio to verify the receive path. The signal is fed DIRECTLY into the ANTENNA PORTS in the back of the Base Radio. This excludes the RFDS and antenna cabling from the measurement. This verification procedure is recommended after replacing a Receiver, BRC, or Power Supply module.Note The following procedure requires the Base Radio to be out of service.

Unless the base radio is currently out of service, Motorola recommends performing this procedure during off-peak hours. This minimizes or eliminates disruption of services to system users.

Equipment Setup

Set up the equipment for the receiver verification as follows:




4. Disconnect the existing cables from the connectors labeled RX1, RX2, and RX3 on the back of the Base Radio. If the radio is configured for 2 Branch diversity, disconnect the RX1 and RX2 cables.

5. Connect test cables from each of the RX1, RX2, and RX3 connectors (Cables A,B,C in Figure 9-8) to the input ports of the 3-way splitter. For 2 Branch diversity tests, load the RX3 cable with an appropriate 50ohm load or connect it to the RX3 antenna port on the radio.

6. Connect an additional test cable (Cable D in Figure 9-8) from the summed port of the 3-way splitter to the RF IN/OUT connector on the R2660 Communications Analyzer.


f ield>fc –oplatform


9-58 6880801E35-E 22-Mar-06







Figure 9-8 RX Verification Test Setup

Note Due to the nature of the Generation 2 BR configuration, Antenna 2 MUST be connected to the R2660 for synchronization. All three RX inputs on the back of the EBTS must be connected to the R2660 and calibrated such that EACH input receives the calibrated RF signal. (See Calibration of the R2660 output level on page 9-55) If all RX inputs are not connected, some receive paths will not receive properly.


22-Mar-06 6880801E35-E 9-59



Receiver Verification Procedure: Generation 2 Base Radio

This procedure provides commands and responses to verify proper operation of the Base Radio receiver paths. Perform the procedure on the receiver in each Base Radio in the EBTS.

1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the front of the EBRC module. Using the terminal program on the service computer, log onto the BR. Bold type indicates user input commands.





2. Set the Frequency to of the R2660 to 810MHz. Power out should be set to –80 dBm.

3. Enable Global Synchronization.

4. Disable System Gain.

Note This step should only be performed if the Base Radio is being connected directly to the Base Radio Antenna ports. If verification is being performed at the top of the rack (adding an RFDS), disregard the above command.


field>

field>es -orx_all -tglobal f ield> freq -orxch1 -f810

f ield>sge -orx_all -soff


9-60 6880801E35-E 22-Mar-06



5. Verify the R2660 signal level.


Note RX Path1 RSSI must read -80dBm ± 1dB for the BER Floor verification to be accurate. Adjust the output level of the R2660 to compensate for loss in the test cables and three-way splitter.

f ield> enable -orxch1 -dbr1 -sonf ield> ppc -orych1 -mchn -s1f ield> ppr -orxch1 -r1 -a100

f ield>ppr -orxch1 -r1 -a100



Sync. Attempts=1.000000Sync. Successes=1.000000

BER%=0.000000

RX Path1 RSSI=-80.934021RX Path2 RSSI=-127.012520


Chn sig. strength=-57.098698Chn intf. strength=-91.696739

field>


22-Mar-06 6880801E35-E 9-61



BER Floor Measurement: Generation 2 Base Radio

1. Verify that the R2660 is set to 810MHz and is producing a power level of -80dBm. (See Receiver Verification Procedure: Generation 2 Base Radio with RFDS on page 9-52.)


3. Check Receiver. At the prompt, type (inputs are in bold, comments are in italics):

4. Enter the command to return all active alarms of the Base Radio. At the field> prompt, type:


f ie ld> ppc -orxch1 -mchn -s1

f ie ld> freq -orxch1 -f810

f ie ld> enable -orxch1 -soff

f ie ld> enable -orxch1 -dbr1 -son

f ie ld> ppr -orxch1 -a1000 -r1






f ie ld> enable -orxch1 -db3 -son


f ie ld> alarms -ofault_hndlr


9-62 6880801E35-E 22-Mar-06



5. As shown below respectively for 800 MHz Generation 2 Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the field> prompt, type:

Receiver Sensitivity Measurement: Generation 2 Base Radio

1. Verify that the R2660 is set to 810MHz and adjust the output power to a level of -50dBm.


a) Attach 8481D Power Sensor to the Sensor input on the front of the 437B.

b) Attach the included HP 11708A 30dB pad to the Power input on the front on the 473B.

c) Power on the 437B.d) Connect the Power Meter to the female end of the 30dB pad extruding

from the Power input.e) Press the “Zero” button on the 437B.f) Wait for Zeroing operation to complete.g) Press “Shift-Zero” to enter the Cal value. This is listed as CF on the


vs. freq on the Power Sensor. Choose the closest frequency range for the application. For 800MHz measurements, interpolate between 1.0GHz and 0.5GHz to obtain a Cf of 99.0



4. Increase the power level on the R2660 until the HP 437B Power Meter reads -50dB.



Example: R2660 reads -44dBmHP 437B reads -50dBmCalfactor A = -44, path loss = 6dB

f ie ld> fc –oplatform


22-Mar-06 6880801E35-E 9-63



7. Path loss must be determined for each Antenna cable A,B,C (see Figure 9-8). If comparable cables are used for all three, the path losses of all three should be the same.



10. Set the R2660 to Frequency 810MHz and a Power level of -108dBm + path loss.

Example: If your path loss was 6dB, set the R2660 to -102dBm.














f ie ld> enable -orxch1 -db3 -son




9-64 6880801E35-E 22-Mar-06



13. As shown below respectively for 800 MHz Generation 2 Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the prompt, type:






4. Disconnect the test cable from the RX 1 connector located on the backplane of the Base Radio.

5. Connect the standard equipment cable to the RX 1 connector.

6. Disconnect the cable to the R2660 Communications Analyzer.

7. Restore power to the Base Radio by setting the Power Supply rocker switch to the ON (1) position.This completes the Receiver Verification Procedure for the receiver.



22-Mar-06 6880801E35-E 9-65


Generation 2/EBRC Single Channel Base Radio Backplane


Backplane Signals Table 9-24 provides a list of all signals routed on the backplane interconnect board.

Table 9-24 BR Backplane Signal Descriptions

Signal Description

GND Station Ground

28.6 V 28.6 VDC Output from PS



A0, A1, A2, A3, A4, A5, A6** The BRC uses these lines to address station modules and devices on those modules

SPI_MOSI Serial Processor Interface- Master out, slave in Data

SPI_MISO Serial Processor Interface- Master in, slave out Data

SPI_CLK Serial Processor Interface- Clock Signal (100 KHz- 1MHz)

ACG1, ACG2, ACG3, ACG4

BRC uses these lines to set digital attenuators on the receiver(s) for SGC functionality

2.1MHZ_RX 2.1 MHz generated on the BRC and used as a reference by the Receiver(s)

2.1MHZ_TX 2.1 MHz generated on the BRC and used as a reference by the Exciter

DATA1, DATA1* This differential pair carries Receiver 1 data to the Base Radio Controller



ODC_1, ODC_2, ODC_3 Clocks used to clock differential receive data from each respective receiver to the BRC

SBI_1,S BI_2, SBI_3 Serial Bus Interface - these lines are used to program the custom receiver IC in each receiver

SSI, SSI* Differentiual transmit data from the Exciter to the BRC

CLK, CLK* Differential Data clock used to clock transmit data from the BRC to the Exciter

VBLIN Programmable bias voltage generated on the Exciter and used to bias PA stages


9-66 6880801E35-E 22-Mar-06


Generation 2/EBRC Single Channel Base Radio

RESET* Output from BRC to Exciter

EXT_VFWD DC voltage representing the forward power at the antenna as measured by the external watt meter

EXT_VREF DC voltage representing the reflected power at the antenna as measured by the external watt meter.

WP* Write protect line used by the BRC to write serial EPROMs located on each module

BAT_STAT Binary flag used to signal BRC to monitor the External battery supply alarm

METER_STAT Binary Flag used by the BRC to indicate to the BRC it should monitor

PA_ENABLE* The BRC uses this line to control PA bias.

1PPS Global Positioning System- 1 pulse per second (this may be combined with 5 MHz at the site frequency reference)

RCLK RS-232- Receive Clock

TCLK RS-232- Transmit Clock

CTS RS-232- Clear To Send

RTS RS-232- Request To Send

CD RS232- Carrier Detect

RxD RS232- RX Data

TxD RS232- TX Data

BRG RS-232 Baud Rate Generator

5 MHZ / Spare signal not currently used

EXCITER OUT Forward transmit path QQAM at approximately an 11 dBm level

EXCITER_FEEDBACK Signal comes from PA at approximately 16 dBm. Used to close the cartesian RF_LOOP

PA_IN 4 dBm QQAM forward path of the transmitter

PA_FEEDBACK Signal to the Exciter at approximately 16 dBm. Used to close the cartesian RF_LOOP

Rx1_IN RF into Receiver 1




Signal Description


22-Mar-06 6880801E35-E 9-67



Generation 2 Single Channel BR Backplane Connections

All external equipment connections are made on the Base Radio backplane. Table 9-25 lists and describes each of the connectors on the backplane.

5MHZ REFERENCE5 MHZ Station/Site reference. Signal comes from the redundant site frequency reference and usually is multiplexed with the 1 PPS signal from the Global Positioning Satellite input to the site frequency reference.

ETHERNET Interface between the BRC and the ACG. This connects the Base to the 10 MHz LAN

SCR_SHUT Not Used

SCR_THRESH Not Used

RELAY ENABLE Not Used

SHUTDOWN Input signal from the BRC to the Power Supply. Used to exercise a station “hard start”

28V_AVG Not Used

BATT_TEMP Not Used

Note * enabled lowNote ** SPI address A6 was added to enable additional SPI addresses. The Exciter only needs to be changed if the change is required to take advantage of additional SPI addresses. A6 pin A13 should be a NO CONNECT to enable A6 functionality on other modules.


Signal Description

Table 9-25 Generation 2 Base Radio Backplane Connectors

Connector Module Description Type

P1 EBRC Signal 96 pin EURO

P2 Rx Signal 48 pin AMP Z-Pack Futurebus

P3 Rx RF Harting Harpac

P4 not used not used not used

P5 EX Signal 96 pin EURO

P6 PA Signal 96 pin EURO

P7 External/Alarm Signal DB25

P8 External/RS232 Signal DB9

P9 PS Signal 78 pin AMP Teledensity


9-68 6880801E35-E 22-Mar-06



Figure 9-9 shows the locations of the Generation 2 Base Radio external connections.

P10 Ethernet B/5 MHz Spare not used/not populated BNC blindmate

P11 Ethernet Signal BNC Blindmate

P12 DC Input-48 VDC IN (not part of the backplane assembly)

8 pin AMP 530521-3

P13 5 MHz/ 1 PPS Signal BNC

P14 External/EX RF (EX to PA) SMA blindmate

P15 External/EX EX Feedback SMA blindmate

P16 External/PA PA Feedback SMA blindmate

P17 External/PA PA IN SMA blindmate

P18 External/PA PA OUT SMA blindmate

P19 Rx Branch 1 RF SMA



Table 9-25 Generation 2 Base Radio Backplane Connectors (continued)

Connector Module Description Type


22-Mar-06 6880801E35-E 9-69



Figure 9-9 Generation 2 Base Radio Backplane Connectors

Generation 2 Single Channel BR Backplane Connector Pinouts

Table 9-26 lists the pin-outs for the 96-PIN P1 connector. P1 provides power, digital signal, and analog signal interconnect to the BRC.

EX OUT

PA IN

EX

PA FB

DC POWER

AC POWER

RS 232ALARM

RX 1

RX 2

RX 3

5MHZ/1 PPS A

ETHERNET A

PA OUT

GROUND

EBTS327B080601JNM

RE BLACK

This port is not placed on the backplane

*

*

ETHERNET B

Table 9-26 P1 Gen 2/BR Connector Pin-outs

Pin Row A Row B Row C

1 AGC3 28.6 VDC AGC1

2 AGC4 14.2 VDC AGC2

3 GND GND GND

4 RESET* GND GND

5 BATT_STAT GND GND

6 CTS GND GND

7 RTS 5.1 VDC 5.1 VDC


9-70 6880801E35-E 22-Mar-06



8 5.1 VDC 5.1 VDC 5.1 VDC

9 5.1 VDC 5.1 VDC 5.1 VDC

10 SHUTDOWN 5.1 VDC

11 RCLK 5.1 VDC DATA1

12 ODC_1 5.1 VDC DATA1*

13 TCLK GND DATA3

14 ODC_3 GND DATA3*

15 RxD GND DATA2

16 ODC_2 BP ID_0 DATA2*

17 TxD BP ID_1 A6

18 SSI EXT_GPI_1 SBI_1

19 SSI* EXT_GPO_1* SBI_3

20 BRG GND SBI_2

21 CLK EXT_GPI_2‘* EXT_GPO_2*

22 CLK* GND A4

23 GND PA_ENABLE* A3

24 A5 GND A2

25 A0 GND A1

26 CD GND 5MHZ/1PPS (5 MHz SPARE)

27 METER_STAT GND SPI_MISO

28 WP* GND SPI_CLK

29 GND GND SPI_MOSI

30 GND GND GND

31 1PPS_GPS GND 2.1MHZ_TX



Table 9-26 P1 Gen 2/BR Connector Pin-outs (continued)



22-Mar-06 6880801E35-E 9-71



Table 9-27 lists 48-PIN P2 3X Receiver pin-outs

Table 9-28 lists the 48-pin P3 pin-outs for the 3X Receiver.

Table 9-27 Gen 2 BR P2 Rx Signal Connector Pinouts

Pin Row A Row B Row C Row D

1 GND AGC4 AGC3 A6

2 GND AGC2 AGC1 A0

3 GND RX1_DATA1 RX1_DATA1* A1

4 GND RX1_SBI RX1_ODC A2

5 GND RX2_DATA RX2_DATA* A3

6 5.1 VDC RX2_SBI RX2_ODC A4

7 GND RX3_DATA RX3_DATA* A5

8 GND RX3_SBI RX3_ODC WP*

9 14.2 VDC SPI_SCLK SPI_MOSI SPI_MISO

10 14.2 VDC GND GND GND

11 14.2 VDC GND 2.1MHZ_RX GND

12 GND GND GND GND

Note * Enabled lowNote Row A is the lowest row of pins. Pins on Row A are longer for mate first and break last connectionNote Pin1, Row D was changed from Ground to A6 between Legacy and Gen2 BR

Table 9-28 Gen 2 BR P3 3X Receiver Pin-outs

Pin Row A Row B Row C Row D Row E

1 GND GND GND

2 RX1

3 GND GND GND

4

5

6

7 GND GND GND


9-72 6880801E35-E 22-Mar-06



Table 9-29 lists the pin-outs for the 96-pin P5 connector of the Exciter.

8 RX2 RX3

9 GND GND GND

Note All pins in columns A, C and D are connected to ground. Note Connections in columns B and D are Rx input signals

Table 9-29 Gen 2 BR P5 Exciter Connector Pin-outs


1 28.6 V 28.6 V 28.6 V

2 28.6 V 28.6 V 28.6 V

3 14.2V 14.2V 14.2V

4 14.2V 14.2V 14.2V

5 5.1 V 5.1 V 5.1 V

6 5.1 V 5.1 V 5.1 V

7 GND GND EXT_VFWD

8 GND GND EXT_VREF

9

10 GND GND GND

11 GND GND VBLIN

12 GND GND RESET*

13 A6

14 GND GND GND

15 GND GND SPI_MISO

16 A0 GND GND

17 GND GND SPI_CLK

18 A1 GND WP*

19 GND GND GND

20 A5 GND SPI_MOSI

21 GND GND GND

Table 9-28 Gen 2 BR P3 3X Receiver Pin-outs (continued)

Pin Row A Row B Row C Row D Row E


22-Mar-06 6880801E35-E 9-73



Table 9-30 Lists the pinouts, signals and power for the 96-PIN P6 connector of the Power Amplifier.

22 A4 GND GND

23 GND GND CLK*

24 A3 GND GND

25 GND GND CLK

26 GND GND GND

27 GND GND SSI*

28 GND GND GND

29 GND GND SSI

30 GND GND GND

31 GND GND 2.1MHz_TX

32 GND GND GND

Note * = enabled lowNote SPI address A6 was added to the EBRC to enable additional SPI addresses. Only change the EX if taking advantage of additional SPI addresses via A6. A6 pin A13 should be no connect to enable A6 functionality on other modules.

Table 9-30 Gen 2 BR P6 PA Connector Pin-outs


1 VBLIN GND 28.6 VDC

2 GND GND 28.6 VDC

3 A0 GND 28.6 VDC

4 GND GND 28.6 VDC

5 A1 GND 28.6 VDC

6 GND GND 28.6 VDC

7 A2 GND 28.6 VDC

8 GND GND 28.6 VDC

9 A3 GND 28.6 VDC

10 GND GND 28.6 VDC

Table 9-29 Gen 2 BR P5 Exciter Connector Pin-outs (continued)



9-74 6880801E35-E 22-Mar-06



11 SPI_MISO GND 28.6 VDC

12 GND GND 28.6 VDC

13 SPI_MOSI GND 28.6 VDC

14 GND GND 28.6 VDC

15 SPI_CLK GND 28.6 VDC

16 GND PA_ENABLE* 28.6 VDC

17 WP* GND 28.6 VDC

18 GND GND 28.6 VDC

19 A6 GND 28.6 VDC

20 GND GND 28.6 VDC

21 GND GND 28.6 VDC

22 GND GND 28.6 VDC

23 GND GND 28.6 VDC

24 GND GND 28.6 VDC

25 GND 5.1 VDC 28.6 VDC

26 GND 5.1 VDC 28.6 VDC

27 GND 14.2 VDC 28.6 VDC

28 GND 14.2 VDC 28.6 VDC

29 GND 14.2 VDC 28.6 VDC

30 GND 14.2 VDC 28.6 VDC

31 GND 28.6 VDC 28.6 VDC

32 GND 28.6 VDC 28.6 VDC

Note * Enabled lowNote Pin B2 was re-defined for use with the EBRC- it went from GND for Legacy Controllers to PA_ENABLE with the EBRC.Note SPI address A6 was added to the EBRC to enable additional SPI addresses. If the PA does not use A6 pin A19, A6 Pin 19 should be no connect to enable A6 functionality on other modules.

Table 9-30 Gen 2 BR P6 PA Connector Pin-outs (continued)



22-Mar-06 6880801E35-E 9-75



Table 9-31 lists the pin-outs for the 25-pin P7 Alarm connector.

Table 9-31 Gen 2 BR P7 External Alarm Connector Pin-outs

Pin Signal

1 EXT_GPI_1*

2 EXT_GPO_1*

3 GND

4 EXT_GPI_2*

5 EXT_GPO_2*

6

7

8

9

10 GND

11 28.6 VDC

12 14.2 VDC

13 14.2 VDC

14

15 5.1 VDC

16 GND

17 BAT_STAT*

18 MTR_STAT*

19 EXT_VFWD

20 EXT_VREF

21 GND

22 GND

23 BATT_TEMP

24

25 GND



9-76 6880801E35-E 22-Mar-06



Table 9-32 lists the pin-outs for the 9-pin P8 RS-232 connector.

Table 9-33 lists the pinouts for the 78-pin P9 Power Supply Connector

Table 9-32 Gen 2 BR P8 External RS232 Connector Pin-outs

Pin No. Signal

1 CD

2 RxD

3 TxD

4 DTR (RCLK)

5 GND

6 DSR (TCLK)

7 RTS

8 CTS

9 BRG

Table 9-33 Gen2 BR P9 Power Connector

Pin No. Signal

1 GND

2 GND

3 28.6 V

4 28.6 V

5 28.6 V

6 28.6 V

7 28.6 V

8 28.6 V

9 28.6 V

10 28.6 V

11 28.6 V

12 28.6 V

13 28.6 V

14 28.6 V

15 28.6 V


22-Mar-06 6880801E35-E 9-77



16 14.2 V

17 14.2 V

18 14.2 V

19 14.2 V

20 14.2 V

21 14.2 V

22 14.2 V

23 14.2 V

24 5.1 V

25 5.1 V

26 5.1 V

27 5.1 V

28 5.1 V

29 5.1 V

30 5.1 V

31 5.1 V

32 GND

33 GND

34 GND

35 GND

36 GND

37 GND

38 GND

39 GND

40 GND

41 GND

42 GND

43 GND

44 GND

Table 9-33 Gen2 BR P9 Power Connector (continued)

Pin No. Signal


9-78 6880801E35-E 22-Mar-06



45 GND

46 GND

47 GND

48 GND

49 GND

50 GND

51 GND

52 GND

53 GND

54 SCR_SHUT

55 SCR_THRESH

56 RELAY_ENABLE

57 SHUTDOWN

58 28V_AVG

59 BATT_TEMP

60 SPI_MISO

61 SPI_MOSI

62 SPI_CLK

63 A6

64

65

66

67 A0(CS1)

68 A1(CS2)

69 A5

70

71 A4

72

73 A3


Pin No. Signal


22-Mar-06 6880801E35-E 9-79



Table 9-34 describes the coaxial P11 Ethernet connector on the Gen 2 BR.

Table 9-35 lists the pin-outs for the 5 MHz/1PPS P13 connector.

74 GND

75 A2

76 GND

77 GND

78 GND

Table 9-34 Gen 2 BR P11 Ethernet Connector Pinout

Coaxial Description

Center Ethernet

Outer GND

Note Ethernet ground on the outer conductor of P11 is DC isolated from station ground.

Table 9-35 Gen 2 BR P12 DC In Connector

Pin Description

1 + BATTERY

2 + BATTERY

3 - BATTERY (RTN)

4 - BATTERY (RTN)

5 + BATTERY

6 + BATTERY

7 - BATTERY (RTN)

8 - BATTERY (RTN)


Pin No. Signal


9-80 6880801E35-E 22-Mar-06



Table 9-36 through Table 9-40 list the pin-outs for the SMA and blindmate connectors for Receivers 1- 3, BRC, Exciter and PA.

Table 9-36 Gen 2 BR P13 Connector Pin-outs

Connector Signal

1 ETHERNET - A (or 5MHZ IN*)


Table 9-37 Gen 2 BR SMA Connectors- Receivers

Connector Signal

P19 RCV ONE RF IN

P20 RCV TWO RF IN

P21 RCV THREE RF IN

Table 9-38 Gen 2 BR Blind Mates - BRC

Connector Signal

P10 SPARE* (or 5MHZ/1 PPS - A)

P11 ETHERNET* (or ETHERNET - A)

Note *May appear as indicated in parenthesis on some production units.

Table 9-39 Gen 2 BR Blind Mates - Exciter

Connector Signal

P14 EXCITER OUT

P15 EXCITER FEEDBACK

Table 9-40 Gen 2 BR Blind Mates - PA

Connector Signal

P16 PA FEEDBACK

P17 PA IN

P18 PA RF OUT


22-Mar-06 6880801E35-E 9-81


QUAD Channel Base Radio/Base Radio FRU Replacement Procedures


Replace suspected station modules with known non-defective modules to restore the station to proper operation. The following procedures provide FRU replacement instructions, post-replacement adjustments and verification instructions.

QUAD Base Radio Replacement Procedure

Note Base Radio removal and installation procedures appear for reference or buildout purposes. Field maintenance of Base Radios typically consists of replacement of FRUs within the Base Radio. Perform Base Radio FRU replacement according to “Base Radio FRU Replacement Procedure” below.


! CAUTION

Improper lifting or dropping the BR could result in serious personal injury or equipment damage.

Base Radios are HEAVY!

Handle the BR with extreme caution, and according to local health and safety regulations.

Removal

Remove the BR from the Equipment Cabinet as follows:

! CAUTION

A Single Carrier BR can weigh up to 76 LBS (34 KG). A QUAD Carrier BR can weigh up to 91 LBS (41 KG). Handle the BR with extreme caution, and according to local health and safety regulations.




9-82 6880801E35-E 22-Mar-06


QUAD Channel Base Radio/Base Radio FRU Re-

3. Remove the Power Amplifier module to reduce the BR weight. Remove the two M10 TORX screws that secure the Power Amplifier module. Slide the module out of the chassis.


5. While supporting the BR, carefully remove the BR from the Equipment Cabinet by sliding the BR from the front of cabinet. When the BR becomes free from its mounting rails, be sure to fully support it.

Installation


! CAUTION

A Single Carrier BR can weigh up to 76 LBS (34 KG). A QUAD Carrier BR can weigh up to 91 LBS (41 KG). Handle the BR with extreme caution, and according to local health and safety regulations.


2. Remove the Power Amplifier module to reduce the BR weight. Remove the two M10 TORX screws that secure the Power Amplifier module. Slide the module out of the chassis.



5. Slide the Power Amplifier module back into the BR chassis. Replace two M10 TORX screws that secure the Power Amplifier module. Secure the module by tightening the screws to the specified torque of 5 in-lbs.

6. Connect the cabinet cabling to the BR. Refer to Backplane figure XX.

7. Perform BR activation in accordance with the QUAD Base Radio Station Verification Procedures on page 9-86.



22-Mar-06 6880801E35-E 9-83




CAUTIONThe Base Radio contains static-sensitive devices. Prevent electrostatic discharge damage to Base Radio modules! When replacing Base Radio FRUs, wear a grounded wrist strap. Observe proper anti-static procedures.







QUAD BRs Radio FRU Replacement Procedure

Perform the following steps to replace any of the Base Radio FRUs:Note After a Control Board or BR replacement, the integrated Site

Controller (iSC) reboots the BR. Whenever the BR goes off-line, the Replacement BRC Accept Timer begins counting down. A BR reboot occurs if the BR remains off-line as the timer times out. (The timer’s default period is three minutes.) If someone turns on the BR before the timer times out, power down the BR. Then wait for the minimum timer period before turning on the BR.

1. Notice the Power Supply rocker switch, behind the front panel of the Power Supply. Set the Power Supply rocker switch to the OFF (0) position. Turning off this switch removes power from the Base Radio.






9-84 6880801E35-E 22-Mar-06


QUAD Channel Base Radio/Base Radio FRU Re-

CAUTIONDO NOT slam or force the module into the chassis assembly. Rough handling can damage the connectors or backplane.



8. Perform the Station Verification Procedure.

QUAD BR Power Amplifier (PA) Fan FRU Replacement





4. Remove fan assembly from PA chassis. Note To install the new fan kit, reverse above procedure.


22-Mar-06 6880801E35-E 9-85


QUAD Base Radio Station Verification Procedures


Perform the Station Verification Procedures whenever you replace a FRU. The procedures verify transmit and receive operations. Each procedure also contains the equipment setup.

QUAD BR Replacement FRU Verification

Before shipment, the factory programs all module-specific information. Base Radio specific information (e.g., receive and transmit frequencies) involves a download to the Base Radio from the network/site controller.

The Base Radio does not require replacement FRU alignment.

QUAD BR Base Repeater FRU Hardware Revision Verification



2. Connect the other end of the RS-232 cable to the STATUS port, located on the front panel of the EX/CNTL module.

3. After the BR is powered up using the front switch on the Power Supply Module, press the reset button on the Control Module front panel. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the field password, log in to the BR.






field>


9-86 6880801E35-E 22-Mar-06



Note Future versions of the QUAD BR will ship with software that recognizes the BR cabinet position. Default Motorola Manufacturing BR programmed cabinet position is (0,0), which automatically sends the radio to Test Application software mode upon power up. Upon setting a valid cabinet position, the radio will default to the Call Processing mode of operation.



6. Set desired cabinet id, position, and of BR by typing the following commands, with the final number on each command being the desired cabinet id and position. The command example below sets cabinet id to 5, and cabinet position to 2.


Note To start Call Processing mode of operation, reset the Base Radio using the front panel switch.

QUAD BR Transmitter Verification



Equipment Setup


f ield>fv -oplatformf ield>

field>ci -oplatform -c5f ield>pi -oplatform -p2

f ield>

field> logout


22-Mar-06 6880801E35-E 9-87






! CAUTION




6. Connect a 10 dB attenuator (100 W or more average power dissipation) on the other end of the test cable.









Transmitter Verification Procedure(QUAD Carrier 800 MHz and 900 MHz Power Amplifiers)

This procedure provides commands and responses to verify proper operation of the transmit path for 800 MHz and 900 MHz QUAD Channel Base Radios.


9-88 6880801E35-E 22-Mar-06



1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the Control Module front panel. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the user_id -ufield and the field password, login to the BR.





2. Dekey the BR to verify that no RF power is being transmitted. Set the transmit DSP test mode to “stop.” At the field > prompt, type:

Note The following command keys the transmitter. Make sure that transmission only occurs on licensed frequencies or into an RF load.

3. Key the BR to 40 watts, following the steps below from the field > prompt:


field>



f ie ld> dpm -otxch1 -mnone





22-Mar-06 6880801E35-E 9-89



a) 800 MHz QUAD: Set the frequency of transmit channel 1 through 4.

b) 900 MHz QUAD: Set the frequency of transmit channel 1 through 4.

c) Enable the channels by setting a data pattern to “iden”


d) Set the transmit power to 40 watts and key the BR.


f ie ld> freq -otxch2 -f860.025














9-90 6880801E35-E 22-Mar-06




Note The reported value for forward power are not indicative of Base Radio performance. This value is reported from the internal wattmeter. These limits are only for verification of operation and are not representative of true operational power of the transmitter.

a) At the field > prompt, type:

This command returns all active alarms of the Base Radio.b) At the field > prompt, type:


5. View the spectrum of the transmitted signal on the R2660 Communications Analyzer in the Spectrum Analyzer mode. Figure 9-10 and Figure 9-11 shows a sample of the 800MHz and 900MHz spectrum, respectively.

Table 9-41 QUAD BR Transmitter Parameters




VSWR Less than 2:1

f ie ld> power -otx_all



22-Mar-06 6880801E35-E 9-91



Figure 9-10 800 MHz QUAD Carrier Spectrum


9-92 6880801E35-E 22-Mar-06



Figure 9-11 900 MHz QUAD Carrier Spectrum









22-Mar-06 6880801E35-E 9-93








! CAUTION









9-94 6880801E35-E 22-Mar-06



QUAD BR Receiver Verification: Base Radio with RFDS (Measurement at the top of Rack)

The receiver verification procedure sends a known test signal into the Base Radio via the antenna ports at the top of the rack to verify the receive path. This verification procedure is recommended after replacing a Receiver, BRC, or Power Supply module.Note The following procedure requires the Base Radio to be out of service.


Equipment Setup

Set up equipment for the receiver verification as follows:




4. Disconnect the existing cables from the connectors labeled RX1, RX2, and RX3 at the top of the EBTS rack. If the radio is configured for 2 Branch diversity, disconnect the RX1 and RX2 cables.

Note Connecting the R2660 to the EBTS rack antenna ports will introduce extra system gain into the measurement, which must be accounted for. This must be accounted for in the calibration procedure. (See Calibration of the R2660 output level on page 9-102.).




22-Mar-06 6880801E35-E 9-95



Figure 9-12 QUAD BR w/ RFDS Verification Test Setup





10. Apply power to the R2660.Note Due to the nature of the QUAD BR configuration, Antenna 2 MUST

be connected to the R2660 for synchronization (This is not required for SR9.6 and above). All three RX inputs on the back of the EBTS must be connected to the R2660 and calibrated such that EACH input receives the calibrated RF signal. (See Calibration of the R2660 output level on page 9-102.) If all RX inputs are not connected, some receive paths will not receive properly.


9-96 6880801E35-E 22-Mar-06



Receiver Verification Procedure: QUAD Base Radio with RFDS







2. Set the Frequency of the R2660 to 810 MHz (898 MHz for 900 MHZ). R2660 power out should be set to –80 dBm.

Note Replace 810 with 898 for 900 MHz in the following MMI command sessions.

3. Set all channel frequencies:


field>






22-Mar-06 6880801E35-E 9-97








f ie ld> ppr -orxch1 -r1 -a100




Sync. Attempts=1.000000

Sync. Successes=1.000000

BER%=0.000000




Chn sig. strength=-57.098698

Chn int f. strength=-91.696739

f ield>


9-98 6880801E35-E 22-Mar-06



BER Floor Measurement: QUAD Base Radio with RFDS

1. Verify that the R2660 is set to 810MHz (896 MHz for 900 MHZ QUAD Channel BR) and is producing a power level of -80dBm. (See Receiver Verification Procedure: QUAD Base Radio with RFDS on page 9-97.)


3. Check Receiver 1. At the prompt, type (inputs are in bold, comments are in italics).

Note Replace 810 with 898 for 900 MHz in the following MMI command sessions















22-Mar-06 6880801E35-E 9-99



Check Receiver 2. At the prompt, type:





























9-100 6880801E35-E 22-Mar-06






5. As shown below respectively for 800/900 MHz QUAD Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the prompt, type:

















22-Mar-06 6880801E35-E 9-101



Receiver Sensitivity Measurement: QUAD Base Radio with RFDS



1. Verify that the R2660 is set to 810 MHz for the 800 MHz QUAD Channel or 896 MHz for the 900 MHz QUAD, then adjust the output power to a level of -50dBm


a) Attach 8481D Power Sensor to the Sensor input on the front of the 438A.

b) Attach the included HP 11708A 30dB pad to the Power REF output on the front on the 438A.

c) Power on the 438A.d) Connect the Power Sensor to the female end of the 30dB pad extruding

from the Power Reference output.e) Press the “Zero” button on the 438A.f) Wait for Zeroing operation to complete.g) Press “Shift-Zero” to enter the Cal value. This is listed as CF on the


vs. freq on the Power Sensor. Choose the closest frequency range for the application. For 800/900 MHz measurements, interpolate between 1.0GHz and 0.5GHz.

j) For measurement of iDEN or 6:1 waveforms, press “Offset” and enter 7.78dB.

3. Disconnect Cable A (see Figure 9-12) from the Base Radio or Antenna Port and connect it to the Power Sensor Head.

4. Increase the power level on the R2660 until the HP 438A Power Meter reads -50dB.



Example: R2660 reads -44dBmHP 438A reads -50dBmCalfactor A = -44, path loss = 6dB


9-102 6880801E35-E 22-Mar-06



7. Path loss must be determined for each Antenna cable A,B,C (see Figure 9-12). If comparable cables are used for all three paths, losses of all three should be approximately the same.



10. Set the R2660 to Frequency 810 MHz for the 800 MHz QUAD Channel or 896 MHz for the 900 MHz QUAD and a Power level of -113.5dBm + path loss.


11. Using the MMI commands below, issue the command to put the BR into single branch mode. If the resulting bit error rate for receiver branches 1, 2, and 3 is less than 8.00%, the receivers passed the test.

Note Replace 810 with 898 for 900 MHz in the MMI command sessions below.











f ield> enable -orxch1 -dbr3 -so





22-Mar-06 6880801E35-E 9-103
































9-104 6880801E35-E 22-Mar-06






13. As shown below respectively for 800/900 MHz QUAD Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the prompt, type:

















22-Mar-06 6880801E35-E 9-105



Receiver Verification: Measurement of the QUAD Base Radio (No RFDS)

The receiver verification procedure sends a known test signal into the Base Radio to verify the receive path. The signal is fed DIRECTLY into the ANTENNA PORTS in the back of the Base Radio. This excludes the RFDS and antenna cabling from the measurement. This verification procedure is recommended after replacing a Receiver, BRC, or Power Supply module.Note The following procedure requires the Base Radio to be out of service.


Equipment Setup











9. Set the R2660 to the EXT REF mode


9-106 6880801E35-E 22-Mar-06



Figure 9-13 QUAD BR Rx Verification Test Setup.

10. Apply power to the R2660.Note Due to the nature of the QUAD BR configuration, Antenna 2 MUST

be connected to the R2660 for synchronization (This is not required for SR9.6 and above). All three RX inputs on the back of the EBTS must be connected to the R2660 and calibrated such that EACH input receives the calibrated RF signal. (See Calibration of the R2660 output level on page 9-102.) If all RX inputs are not connected, some receive paths will not receive properly.

QUAD BR Distributed Multicoupler

The QUAD BR uses an internal distributed multicoupler to distribute the RF signals from the 3 Antenna ports to the 4 Channels of the BR. Each Channel has 3 receivers.


22-Mar-06 6880801E35-E 9-107



Receiver Verification Procedure: QUAD Base Radio







2. Set the frequency to of the R2660 to 810MHz (898 MHz for 900 MHz). Power out should be set to –80 dBm.


3. Set all channel frequencies.


field>






9-108 6880801E35-E 22-Mar-06




Note This step should only be performed if the R2660, 3 way splitter and cables connected directly to the Base Radio Antenna ports. If verification is being performed at the top of the rack (adding an RFDS), disregard the above command.




f ie ld> sge -orx_all -soff








BER%=0.000000






f ield>


22-Mar-06 6880801E35-E 9-109



BER Floor Measurement: QUAD Base Radio

1. Verify that the R2660 is set to 810MHz for the 800 MHz QUAD or 896 MHz for the 900 MHz QUAD and is producing a power level of -80dBm. (See Receiver Verification Procedure: QUAD Base Radio on page 9-108.)


Note Replace 810 with 898 for 900 MHz in the MMI command sessions below.

3. Check Receiver 1.:
















9-110 6880801E35-E 22-Mar-06



Check Receiver 2:

Check Receiver 3:





























22-Mar-06 6880801E35-E 9-111



Check Receiver 4:



5. As shown below respectively for 800 MHz QUAD Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the field > prompt, type:

















9-112 6880801E35-E 22-Mar-06



Receiver Sensitivity Measurement: QUAD Base Radio

1. Verify that the R2660 is set to 810MHz (800 MHz QUAD BR) or 896 MHz (900 MHz BR) and adjust the output power to a level of -50dBm.





from the Power Reference output.e) Press the “Zero” button on the 438A.f) Wait for Zeroing operation to complete.g) Press “Shift-Zero” to enter the Cal value. This is listed as CF on the


vs. freq on the Power Sensor. Choose the closest frequency range for the application. For 800/900 MHz measurements, interpolate between 1.0GHz and 0.5GHz.









9. Reconnect cables A,B,C (see Figure 9-13) to Antenna Ports 1,2,3 on the Base Radio.

10. Set the R2660 to Frequency 810 MHz (896 MHz for 900 MHz QUAD) and a Power level of -108dBm + path loss.



22-Mar-06 6880801E35-E 9-113




Note Replace 810 with 898 for 900 MHz in the MMI command sessions below

Check Receiver 2:




























9-114 6880801E35-E 22-Mar-06



Check Receiver 3:

Check Receiver 4:









f ie ld> ppr -orxch3-a100 -r1



















22-Mar-06 6880801E35-E 9-115





13. As shown below for 800/900 MHz QUAD Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the prompt, type:






4. Disconnect the test cable from the RX 1, RX2, and RX3 connectors located on the backplane of the Base Radio.

5. Connect the standard equipment cable to the RX 1, RX2, and RX3 connectors.

6. Restore power to the Base Radio by setting the Power Supply rocker switch to the ON (1) position.This completes the Receiver Verification Procedure.

7. Repeat the Receiver Verification Procedure for each QUAD receiver in every Base Radio in the EBTS.




9-116 6880801E35-E 22-Mar-06


QUAD Channel BR Backplane


Backplane Connectors

The Base Radio backplane includes all external equipment connections. Table 9-42 lists and describes the backplane connectors.

Table 9-42 QUAD BR Backplane Connectors

Connector Module Description Connector Type

P1 EXBRC Signal 168 Pin AMP Z-Pack Futurebus

P2 RX1 Signal 72 Pin AMP Z-Pack Futurebus

P3 RX1 RF 6 coax Harting Harpak







P10 PA Signal 96 Pin EURO

P11 PS Signal & Power 78 Pin AMP Teledensity

P12* PS -48 Vdc Power In 8 Pin AMP 530521-3

P13 EX RF(EX from PA) SMA blindmate

P14 EX RF(EX to PA) SMA blindmate

P15 External / EXBRC Ethernet BNC blindmate

P16 External / PA RF (PA from EX) SMA blindmate

P17 External / PA RF (PA to EX) SMA Blindmate

P18 External / PA TX Output SMA blindmate

P19 RX Branch 1 RF SMA


22-Mar-06 6880801E35-E 9-117



Figure 9-14 shows the locations of the QUAD Base Radio external connec-tions.

Figure 9-14 QUAD Base Radio Backplane Connectors



P22** External RS232 Dsub-9

P23 External Alarm Dsub-25

P24 External 5MHz/1PPS BNC

Note * P12 is a cutout in the backplane with threaded inserts for securing the connector which mates directly to the power supply. Note ** P22 will not be placed on the backplane. However, the backplane shall be designed with P22 to allow for reuse on future products.

Table 9-42 QUAD BR Backplane Connectors


EX OUT

PA IN

ETHERNET

PA FB

DC POWER

AC POWER

RS 232 ALARM

RX 1(RED)

RX 2(GRN)

RX 3(YEL)

5MHZ/1 PPSPA OUT

GROUND

EBTS327Q112501JNM

RE BLACK

This port must be terminated by 50Ω load when configured for2 Branch Diversity. Also, the rx_fru_config parameter must be set to R12.

*

*

EX FB


9-118 6880801E35-E 22-Mar-06



QUAD BR Backplane Connector Pinouts

Table 9-43 lists the pin-outs for the Base Radio Controller board’s 168-pin P1 connector.

Table 9-43 EXBRC P1 Pinout, Signal and Power

Row A B C D

1 GND 3.3 Vdc 3.3 Vdc NC

2 GND 3.3 Vdc 14.2 Vdc 14.2 Vdc

3 GND 3.3 Vdc 14.2 Vdc 14.2 Vdc

4 GND GND GND GND

5 NC NC NC NC

6 GND GND GND GND

7 GND 16.8MHz_RX 16.8MHz_RX_RTN GND

8 GND GND GND GND

9 GND 5 MHz/1 PPS 3.3 Vdc 3.3 Vdc

10 NC NC NC 3.3 Vdc

11 TxD CTS DTR BRG

12 RTS RxD DSR CD

13 NC NC NC 3.3 Vdc

14 NC NC SHUTDOWN_ SLEEP_

15 PA_ENABLE NC 28.6 Vdc 14.2 Vdc

16 NC NC NC 3.3 Vdc

17 EXT_GPI_1_ EXT_GPI_2_ EXT_GPO_1_ EXT_GPO_2_

18 BAT_STAT_ MTR_STAT_ EXT_VFWD EXT_VREV

19 SPI_M3 SPI_M2 SPI_M1 SPI_M0

20 SPI_ENABLE SPI_MOSI SPI_MISO SPI_CLK

21 SPI_A2 SPI_A1 SPI_A0 WP_

22 NC RxRESET_ NC NC

23 NC Clock_SyncB_ NC NC

24 GND GND 3.3 Vdc 3.3 Vdc

25 SSI_Data_D SSI_CLK_D SSI_FS_D 3.3 Vdc


22-Mar-06 6880801E35-E 9-119



26 SSI_Data_D_RTN SSI_CLK_D_RTN NC 3.3 Vdc


28 DSPIb_MOSI DSPIb_CLK DSPIb_EN_1 DSPIb_EN_2

29 DSPIb_MOSI_RTN DSPIb_CLK_RTN DSPIb_EN_3 NC


31 GND SSI_Data_C SSI_CLK_C SSI_FS_C

32 GND SSI_Data_C_RTN SSI_CLK_C_RTN NC

33 NC Clock_SyncA_ NC NC


35 SSI_Data_B SSI_CLK_B SSI_FS_B 3.3 Vdc

36 SSI_Data_B_RTN SSI_CLK_B_RTN NC 3.3 Vdc


38 DSPIa_MOSI DSPIa_CLK DSPIa_EN_1 DSPIa_EN_2

39 DSPIa_MOSI_RTN DSPIa_CLK_RTN DSPIa_EN_3 NC


41 GND SSI_Data_A SSI_CLK_A SSI_FS_A

42 GND SSI_Data_A_RTN SSI_CLK_A_RTN NC

Table 9-43 EXBRC P1 Pinout, Signal and Power (continued)

Row A B C D

Table 9-44 EXBRC P13 Pinout, Exciter from PA

Coaxial Description

Center PA IN

Outer GND

Table 9-45 EXBRC P14 Pinout, Exciter to PA

Coaxial Description

Center PA Feedback

Outer GND


9-120 6880801E35-E 22-Mar-06



RX1 Connections

Table 9-46 EXBRC P15 Pinout, Ethernet

Coaxial Description

Center Ethernet

Outer GND

Table 9-47 RX1 P2 Pinout, Signal and Power

Row A B C D

1 NC GND GND Clock_SyncA_

2 GND DSPIa_MOSI_RTN DSPIa_CLK_RTN DSPIa_EN_1

3 GND DSPIa_MOSI DSPIa_CLK DSPIa_EN_2

4 GND GND GND GND

5 14.2 SSI_CLK_A_RTN SSI_FS_B SSI_CLK_B_RTN

6 14.2 SSI_CLK_A SSI_FS_A SSI_CLK_B

7 14.2 GND GND GND

8 14.2 SSI_Data_A_RTN GND SSI_Data_B

9 GND SSI_Data_A GND SSI_Data_B_RTN

10 GND NC NC NC

11 3.3 RxRESET_ GND (ID0) GND (ID1)

12 3.3 WP_ SPI_A0 SPI_A1

13 3.3 SPI_MISO SPI_CLK SPI_A2

14 GND SPI_M0 SPI_ENABLE SPI_MOSI

15 GND SPI_M1 SPI_M2 SPI_M3

16 GND GND GND NC

17 GND 16.8MHz_RX GND NC (WB switch)

18 GND 16.8MHz_RX_RTN GND NC (MC switch)


22-Mar-06 6880801E35-E 9-121



RX2 Connections

Table 9-48 RX1 P3 Pinout, RF Input and Output Connection

Row A B C D E

1 GND - GND - GND

2 - RX3_EXP3 - RX1_EXP3 -

3 GND - GND - GND

4 GND - GND - GND


6 GND - GND - GND

7 GND - GND - GND

8 - RX Branch 1 - RX1_EXP1 -

9 GND - GND - GND


Row A B C D

1 NC GND GND Clock_SyncA_

2 GND DSPIa_MOSI_RTN DSPIa_CLK_RTN DSPIa_EN_3

3 GND DSPIa_MOSI DSPIa_CLK DSPIa_EN_2

4 GND GND GND GND

5 14.2 SSI_CLK_B_RTN NC NC

6 14.2 SSI_CLK_B SSI_FS_B NC

7 14.2 GND GND GND

8 14.2 SSI_Data_B_RTN GND NC

9 GND SSI_Data_B GND NC

10 GND NC NC NC

11 3.3 RxRESET_ NC (ID0) GND (ID1)





9-122 6880801E35-E 22-Mar-06



RX3 Connections


16 GND GND GND NC



Table 9-49 RX2 P4 Pinout, Signal and Power (continued)

Row A B C D


Row A B C D E

1 GND - GND - GND


3 GND - GND - GND

4 GND - GND - GND


6 GND - GND - GND

7 GND - GND - GND


9 GND - GND - GND


Row A B C D

1 NC GND GND Clock_SyncB_

2 GND DSPIb_MOSI_RTN DSPIb_CLK_RTN DSPIb_EN_1

3 GND DSPIb_MOSI DSPIb_CLK DSPIb_EN_2

4 GND GND GND GND

5 14.2 SSI_CLK_C_RTN SSI_FS_D SSI_CLK_D_RTN

6 14.2 SSI_CLK_C SSI_FS_C SSI_CLK_D

7 14.2 GND GND GND

8 14.2 SSI_Data_C_RTN GND SSI_Data_D


22-Mar-06 6880801E35-E 9-123



9 GND SSI_Data_C GND SSI_Data_D_RTN

10 GND NC NC NC

11 3.3 RxRESET_ GND (ID0) NC (ID1)





16 GND GND GND NC

17 GND 16.8MHz_RX GND GND (WB switch)


Table 9-51 RX3 P6 Pinout, Signal and Power (continued)

Row A B C D


Row A B C D E

1 GND - GND - GND


3 GND - GND - GND

4 GND - GND - GND


6 GND - GND - GND

7 GND - GND - GND


9 GND - GND - GND


9-124 6880801E35-E 22-Mar-06



RX4 Connections


Row A B C D

1 NC GND GND Clock_SyncB_

2 GND DSPIb_MOSI_RTN DSPIb_CLK_RTN DSPIb_EN_3

3 GND DSPIb_MOSI DSPIb_CLK DSPIb_EN_2

4 GND GND GND GND

5 14.2 SSI_CLK_D_RTN NC NC

6 14.2 SSI_CLK_D SSI_FS_D NC

7 14.2 GND GND GND

8 14.2 SSI_Data_D_RTN GND NC

9 GND SSI_Data_D GND NC

10 GND NC NC NC

11 3.3 RxRESET_ NC (ID0) NC (ID1)





16 GND GND GND NC


18 GND 16.8MHz_RX_RTN GND GND (MC switch)


Row A B C D E

1 GND - GND - GND

2 - RX1_EXP3 - NC -

3 GND - GND - GND

4 GND - GND - GND

5 - RX2_EXP3 - NC -


22-Mar-06 6880801E35-E 9-125



PA Connections

6 GND - GND - GND

7 GND - GND - GND

8 - RX3_EXP1 - NC -

9 GND - GND - GND


Row A B C D E

Table 9-55 QUAD BR PA P10 Pinout, Signal and Power

Row A B C

1 SPI_ENABLE GND 28.6 Vdc

2 GND GND 28.6 Vdc

3 SPI_A0 GND 28.6 Vdc

4 GND GND 28.6 Vdc


6 GND GND 28.6 Vdc


8 GND GND 28.6 Vdc

9 SPI_M0 GND 28.6 Vdc

10 GND GND 28.6 Vdc


12 GND GND 28.6 Vdc


14 GND GND 28.6 Vdc


16 GND GND 28.6 Vdc

17 SPI_MISO GND 28.6 Vdc

18 GND GND 28.6 Vdc

19 SPI_MOSI GND 28.6 Vdc

20 GND GND 28.6 Vdc


9-126 6880801E35-E 22-Mar-06



21 SPI_CLK GND 28.6 Vdc

22 GND 3.3 Vdc 28.6 Vdc

23 WP* 3.3 Vdc 28.6 Vdc

24 GND GND 28.6 Vdc

25 PA_ENABLE GND 28.6 Vdc

26 GND 14.2 Vdc 28.6 Vdc

27 GND 14.2 Vdc 28.6 Vdc

28 GND 14.2 Vdc 28.6 Vdc

29 GND 14.2 Vdc 28.6 Vdc

30 GND 28.6 Vdc 28.6 Vdc

31 GND 28.6 Vdc 28.6 Vdc

32 GND 28.6 Vdc 28.6 Vdc

Table 9-55 QUAD BR PA P10 Pinout, Signal and Power (continued)

Row A B C

Table 9-56 EXBRC P16 Pinout, PA from Exciter

Coaxial Description

Center PA IN

Outer GND

Table 9-57 EXBRC P17 Pinout, PA to Exciter

Coaxial Description

Center PA Feedback

Outer GND

Table 9-58 EXBRC P18 Pinout, PA RF OUT

Coaxial Description

Center PA RF OUT

Outer GND


22-Mar-06 6880801E35-E 9-127



External Connections

Table 9-59 QUAD BR Backplane Coaxial and DC

Signal

P12 -48 Vdc Power

P13 EX Out

P14 Feedback

P15 Ethernet

P16 PA In

P17 PA Feedback

P18 PA RF OUT

P19 RX Branch 1

P20 RX Branch 2

P21 RX Branch 3

P24 5 MHz/1 PPS

Table 9-60 QUAD BR Backplane Alarm 25 Pin Dsub (P23)

Alarm Signal

1 EXT_GPI_1_

2 EXT_GPO_1_

3 GND

4 EXT_GPI_2_

5 EXT_GPO_2_

6

7

8

9

10 GND

11

12


9-128 6880801E35-E 22-Mar-06



13

14

15

16 GND

17 BAT_STAT_

18 MTR_STAT_

19 EXT_VFWD

20 EXT_VREV

21 GND

22 GND

23

24

25 GND

Table 9-61 QUAD BR Backplane RS-232 9 Pin Dsub (P22)

RS-232 Signal

1 CD

2 RxD

3 TxD

4 DTR

5 GND

6 DSR

7 RTS

8 CTS

9 BRG*

Table 9-60 QUAD BR Backplane Alarm 25 Pin Dsub (P23)

Alarm Signal


22-Mar-06 6880801E35-E 9-129



PS Connections

Table 9-62 QUAD PS Power and Signal (P11)

Pin Description Pin Description Pin Description

1 GND (Plug In) 31 3.3 Vdc 61 SPI_MOSI

2 GND 32 GND 62 SPI_CLK

3 GND 33 GND 63 N.C.

4 28.6 Vdc 34 GND 64 N.C.

5 28.6 Vdc 35 GND 65 N.C.

6 28.6 Vdc 36 GND 66 N.C.

7 28.6 Vdc 37 GND 67 SPI_A0

8 28.6 Vdc 38 GND 68 SPI_A1

9 28.6 Vdc 39 GND 69 SPI_M2

10 28.6 Vdc 40 GND 70 SPI_M3

11 28.6 Vdc 41 GND 71 SPI_M1

12 28.6 Vdc 42 GND 72 SLEEP_

13 28.6 Vdc 43 GND 73 SPI_M0

14 28.6 Vdc 44 GND 74 WP_

15 28.6 Vdc 45 GND 75 SPI_A2

16 14.2 Vdc 46 GND 76 GND

17 14.2 Vdc 47 GND 77 GND

18 14.2 Vdc 48 GND 78 GND

19 14.2 Vdc 49 GND

20 14.2 Vdc 50 GND

21 14.2 Vdc 51 GND

2 14.2 Vdc 52 GND

23 14.2 Vdc 53 GND

24 3.3 Vdc 54 NC (FAN CONTROL)

25 3.3 Vdc 55 N.C.

26 3.3 Vdc 56 N.C.


9-130 6880801E35-E 22-Mar-06



27 3.3 Vdc 57 SHUTDOWN_

28 3.3 Vdc 58 NC (Power sharing)

29 3.3 Vdc 59 SPI_ENABLE

30 3.3 Vdc 60 SPI_MISO

Table 9-62 QUAD PS Power and Signal (P11)

Pin Description Pin Description Pin Description

Table 9-63 QUAD BR 48 Vdc Battery Power (P12)

Pin Description Description Pin

1 + BATTERY + BATTERY 5

2 + BATTERY + BATTERY 6

3 - BATTERY (RTN) - BATTERY (RTN) 7

4 - BATTERY (RTN) - BATTERY (RTN) 8


22-Mar-06 6880801E35-E 9-131


QUAD Base Radio Signals


Table 9-64 lists and describes signals for the QUAD Base Radio.

Table 9-64 QUAD Base Radio Signal Descriptions

Signal Name Description Special

28.6 Vdc 28.6 Vdc output from PS



GND Station Ground

RX Branch 1 RX Branch 1 from RFDS 50 ¾



RX1_EXP1 RX1 (branch 1) expansion output 1 50 ¾









5 MHz/1 PPS 5 MHz/1 PPS reference to the BRC

SPI_ENABLE Host Centric SPI Enable

SPI_MISO Host Centric SPI MISO

SPI_MOSI Host Centric SPI MOSI

SPI_CLK Host Centric SPI Clock

SPI_A0 Host SPI Device Address Line A0



SPI_M0 Host SPI Module Address Line M0



9-132 6880801E35-E 22-Mar-06





WP_ Write Protect (active low)

PA_ENABLE Turns off PA bias with active low

SLEEP_ Sleep signal from PS

SHUTDOWN_ PS reset line from BRC

CD RS232 Carrier Detect

RxD RS232 RX Data

TxD RS232 TX Data

DTR RS232 Data Terminal Ready

DSR RS232 Data Set Ready

RTS RS232 Request to Send

CTS RS232 Clear to Send

BRG Baud Rate Generator

RxRESET_ Reset Signal to RX modules

16.8MHz_RX 16.8 MHz reference to RX differential

16.8MHz_RX_RTN 16.8 MHz reference to RX return differential

Clock_SyncA_ Clock Sync signal to RX1 & RX2 For Abacus III

Clock_SyncB_ Clock Sync signal to RX3 & RX4 For Abacus III

SSI_Data_A RX Data from RX module 1 differential

SSI_Data_A_RTN RX Data from RX module 1return differential

SSI_Data_B RX Data from RX module 2 differential

SSI_Data_B_RTN RX Data from RX module 2 return differential

SSI_Data_C RX Data from RX module 3 differential

SSI_Data_C_RTN RX Data from RX module 3 return differential

SSI_Data_D RX Data from RX module 4 differential

SSI_Data_D_RTN RX Data from RX module 4 return differential

Table 9-64 QUAD Base Radio Signal Descriptions (continued)



22-Mar-06 6880801E35-E 9-133



SSI_CLK_A RX Clock from RX module 1 differential

SSI_CLK_A_RTN RX Clock from RX module 1 return differential

SSI_CLK_B RX Clock from RX module 2 differential

SSI_CLK_B_RTN RX Clock from RX module 2 return differential

SSI_CLK_C RX Clock from RX module 3 differential

SSI_CLK_C_RTN RX Clock from RX module 3 return differential

SSI_CLK_D RX Clock from RX module 4 differential

SSI_CLK_D_RTN RX Clock from RX module 4 return differential

SSI_FS_A RX Frame Sync from RX module 1

SSI_FS_B RX Frame Sync from RX module 2

SSI_FS_C RX Frame Sync from RX module 3

SSI_FS_D RX Frame Sync from RX module 4

DSPIa_En_1 DSPa SPI RX1 Abacus enable

DSPIa_En_3 DSPa SPI RX2 Abacus enable

DSPIa_En_2 DSPa SPI RX1 & RX2 SGC enable

DSPIb_En_1 DSPb SPI RX3 Abacus enable

DSPIb_En_3 DSPb SPI RX4 Abacus enable

DSPIb_En_2 DSPb SPI RX3 & RX4 SGC enable

DSPIa_MOSI DSPa SPI MOSI differential

DSPIa_MOSI_RTN DSPa SPI MOSI return differential

DSPIb_MOSI DSPb SPI MOSI differential

DSPIb_MOSI_RTN DSPb SPI MOSI return differential

DSPIa_CLK DSPa SPI Clock differential

DSPIa_CLK_RTN DSPa SPI CLK return differential

DSPIb_CLK DSPb SPI Clock differential

DSPIb_CLK_RTN DSPb SPI CLK return differential

MTR_STAT_ External Wattmeter Status

BAT_STAT_ Battery Status

EXT_VFWD External Wattmeter Forward meter




9-134 6880801E35-E 22-Mar-06



EXT_VREV External Wattmeter Reflected meter

EXT_GPO_1_ General purpose output 1

EXT_GPO_2_ General purpose output 2

EXT_GPI_1_ General purpose input 1

EXT_GPI_2_ General purpose input 2

NC Not connected reserved




22-Mar-06 6880801E35-E 9-135


QUAD+2 Channel Base Radio/Base Radio FRU Replacement Procedures


Replace suspected station modules with known non-defective modules to restore the station to proper operation. The following procedures provide FRU replacement instructions, post-replacement adjustments and verification instructions.

QUAD+2 Base Radio Replacement Procedure



! CAUTION

Improper lifting or dropping the BR could result in serious personal injury or equipment damage.

Base Radios are HEAVY!

Handle the BR with extreme caution, and according to local health and safety regulations.

Removal

Remove the BR from the Equipment Cabinet as follows:

! CAUTION

A QUAD+2 BR can weigh up to 45 LBS (20 KG). Handle the BR with extreme caution, and according to local health and safety regulations.




9-136 6880801E35-E 22-Mar-06


QUAD+2 Channel Base Radio/Base Radio FRU Re-

3. Remove the fan assembly unit to gain access to the power amplifier module. See QUAD+2 BR Fan Assembly FRU Replacement for instruction on removing the fan unit.

4. Remove the Power Amplifier module to reduce the BR weight. See QUAD+2 BR Power Amplifier Module FRU Replacement Procedure for instruction on removing the power amplifier unit.

5. Using a T30 TORX bit, remove the four M6 screws which secure the BR front panel to the Equipment Cabinet mounting rails.

6. While supporting the BR, carefully remove the BR from the Equipment Cabinet by sliding the BR from the front of cabinet. When the BR becomes free from its mounting rails, be sure to fully support it.

Installation


! CAUTION

A QUAD+2 BR can weigh up to 45 LBS (20 KG). Handle the BR with extreme caution, and according to local health and safety regulations.



3. Remove the Power Amplifier module to reduce the BR weight. See QUAD+2 BR Power Amplifier Module FRU Replacement Procedure for instruction on removing the power amplifier unit.


5. Secure the BR to the equipment cabinet mounting rails using four M6 screws using a T30 TORX bit. Tighten the screws to 40 in-lb (4.5 Nm).

6. Slide the Power Amplifier module back into the BR chassis. See QUAD+2 BR Power Amplifier Module FRU Replacement Procedure for instruction on re-installing the power amplifier unit.

7. Re-install the fan assembly unit back into the BR. See QUAD+2 BR Fan Assembly FRU Replacement for instruction on re-installing the fan unit.

8. Connect the DC operation cable to the base radio filter "From Breaker Panel" connector using two 3.5 mm screws using a T15 TORX bit.


22-Mar-06 6880801E35-E 9-137



9. Connect the DC operation cable from the base radio filter to the DC power input connector on the QUAD+2 BR.

Note Ensure the power connections are oriented as the color coding on the base radio filter indicates; i.e. red to red and black to black.

Note If needed, remove the tie-wraps that secure the DC operation cable. The tie-wraps are used for shipping purposes only.

10. Connect the cabinet cabling to the BR. Refer to Backplane Figure 9-20.

11. Perform BR activation in accordance with the QUAD+2 Base Radio Station Verification Procedures on page 9-142.



CAUTIONThe Base Radio contains static-sensitive devices. Prevent electrostatic discharge damage to Base Radio modules! When replacing Base Radio FRUs, wear a grounded wrist strap. Observe proper anti-static procedures.







QUAD+2 BR Transceiver Module FRU Replacement Procedure


Controller (iSC) reboots the BR. Whenever the BR goes off-line, the Replacement BRC Accept Timer begins counting down. A BR reboot


9-138 6880801E35-E 22-Mar-06



occurs if the BR remains off-line as the timer times out. (The timer’s default period is three minutes.) If someone turns on the BR before the timer times out, power down the BR. Then wait for the minimum timer period before turning on the BR.

1. Set the Power Supply rocker switch to the OFF (0) position. Turning off this switch removes power from the Base Radio.

2. Remove the fan assembly unit to gain access to the transceiver module. See QUAD+2 BR Fan Assembly FRU Replacement for instruction on removing the fan unit.

3. Loosen the captive screws using a T20 bit. These are located on each side of the module being replaced.

4. Using the handle, gently pull the module straight out, along the guides on which it sits.

5. Slide the non-defective replacement module along the guiding rails until it is engaged.



7. Secure the replacement module by tightening the captive screws to the specified torque of 15 in-lbs.

8. Re-install the fan assembly unit



QUAD+2 BR Power Amplifier Module FRU Replacement Procedure


Controller (iSC) reboots the BR. Whenever the BR goes off-line, the Replacement BRC Accept Timer begins counting down. A BR reboot occurs if the BR remains off-line as the timer times out. (The timer’s default period is three minutes.) If someone turns on the BR before the timer times out, power down the BR. Then wait for the minimum timer period before turning on the BR.



22-Mar-06 6880801E35-E 9-139




3. Loosen the captive screws using a T20 bit. These are located on each side of the module being replaced.

4. Remove the RF output QN (quick-N) connector from the front of the module as follows:

a) Pull the module out of the chassis far enough so that the RF output QN connector is accessible.

b) Disconnect the cable from the module.

5. Using the handle, gently pull the module straight out, along the guides on which it sits.

6. Slide the non-defective replacement module along the guiding rails.

7. Reconnect the RF cable to the RF output QN connector on the front of the module as follows:

a) While holding the RF cable, slide the replacement module along the guiding rails until the RF cable connector can reach the RF connection on the front of the module.

b) Push the RF’s cable connector onto the module’s connector until it snaps securely into place.



9. Secure the replacement module by tightening the captive screws to the specified torque of 15 in-lbs.

10. Re-install the fan assembly unit.



QUAD+2 BR Power Supply FRU Replacement

Perform the following steps to replace the BR’s power supply.


2. Using a T20 bit, loosen the two captive screws located on the front of the power supply so that they disengage from the chassis.


9-140 6880801E35-E 22-Mar-06



! WARNING

It is recommended that you let the power supply module cool before performing the following step, which will expose surfaces of the module that can be extremely hot.

3. Pull on the metal handle to disengage the power supply from the backplane and remove it completely from the chassis.

4. Gently push the replacement module completely into the Base Radio chassis until it seats.

5. Tighten the two captive screws.


QUAD+2 BR Fan Assembly FRU Replacement

Perform the following steps to replace the BR fan assembly.

1. Using a T20 bit, loosen the three captive screws located on the front of the fan assembly so that they disengage from the chassis.

2. Using the handle on one end and the edge on the other side, gently pull the fan assembly straight out to disengage the connector.

3. Using the guide pins and the connector on the back of the new fan assembly, push the new fan assembly into place until it feels secure.

4. Tighten the three captive screws.



22-Mar-06 6880801E35-E 9-141


QUAD+2 Base Radio Station Verification Procedures


Perform the Station Verification Procedures whenever you replace a FRU. The procedures verify transmit and receive operations. Each procedure also contains the equipment setup.

QUAD+2 BR Replacement FRU Verification

Before shipment, the factory programs all module-specific information. Base Radio specific information (e.g., receive and transmit frequencies) involves a download to the Base Radio from the network/site controller.

The Base Radio does not require replacement FRU alignment.

QUAD+2 BR Base Repeater FRU Hardware Revision Verification



2. Connect the other end of the RS-232 cable to the STATUS port, located on the front panel of the XCVR module.

3. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the front of the XCVR module and hold for at least three seconds until the BR resets. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the user_id -ufield and the field password, login to the BR.






field>


9-142 6880801E35-E 22-Mar-06



Note Default Motorola Manufacturing BR programmed cabinet position is (0,0), which automatically sends the radio to Test Application software mode upon power up. Upon setting a valid cabinet position, the radio will default to the Call Processing mode of operation.



6. Set desired cabinet id, position, and of BR by typing the following commands, with the final number on each command being the desired cabinet id and position. The command example below sets cabinet id to 5, and cabinet position to 2.


Note To start Call Processing mode of operation, reset the Base Radio using the front panel switch.

QUAD+2 BR -- Transmitter Verification

The following procedures verify transmission from the system antennas.

Important Do not transmit to an antenna for any reason, unless those frequencies are properly licensed.

(Cavity Combining RFDS only)Prior to performing this procedure, perform the cavity tuning procedure described in the Cavity Combining RFDS section of this manual.

The transmitter verification procedure verifies the transmitter operation and the integrity of the transmit path. This verification procedure is recommended after replacing a Transceiver, Power Amplifier or Power Supply.Note The following procedure requires the Base Radio to be out of service.

Unless the Base Radio is currently out of service, Motorola

f ield> fv -oplatformf ield>

field>ci -oplatform -c5f ield>pi -oplatform -p2

f ield>

field> logout


22-Mar-06 6880801E35-E 9-143



recommends performing this procedure during off-peak hours. This minimizes or eliminates disruption of service to system users.

Equipment Setup


1. Remove power from the Base Radio by setting the Power Supply rocker switch to the OFF (0) position.



! CAUTION




6. Connect a 10 dB attenuator (100 W or more average power dissipation) on the other end of the test cable.










9-144 6880801E35-E 22-Mar-06



Transmitter Verification Procedure(QUAD+2 Power Amplifiers)

This procedure provides commands and responses to verify proper operation of the transmit path for QUAD+2 Channel Base Radios.

1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the front of the XCVR module and hold for at least three seconds until the BR resets. At the prompt, hit a Carriage Return on the service computer to enter the test application mode. Using the user_id -ufield and the field password, login to the BR.





2. Dekey the BR to verify that no RF power is being transmitted. Set the transmit DSP test mode to “stop.” At the field > prompt, type:

Note The following command keys the transmitter. Make sure that transmission only occurs on licensed frequencies or into an RF load.

3. Key the BR to 40 watts, following the steps below from the field > prompt:


field>



f ie ld> dpm -otx_all -mnone


22-Mar-06 6880801E35-E 9-145



a) Set the frequency of transmit channel 1 through 6 (800 MHz QUAD+2 Channel).

b) Set the frequency of transmit channel 1 through 6 (900 MHz QUAD+2 Channel).

c) Enable the channels by setting a data pattern to “iden”


d) Set the transmit power to 40 watts and key the BR.


Note The reported value for forward power are not indicative of Base Radio performance. This value is reported from the internal wattmeter. These limits are only for verification of operation and are not representative of true operational power of the transmitter.

a) At the field > prompt, type:


f ie ld> freq -otx_all - f860

f ie ld> freq -otx_all - f935

f ie ld> dpm -otx_all -miden



f ie ld> power -otx_all


9-146 6880801E35-E 22-Mar-06



b) At the field > prompt, type:


5. View the spectrum of the transmitted signal on the R2660 Communications Analyzer in the Spectrum Analyzer mode. Figure 9-15 and Figure 9-16 shows a sample of the 800MHz and 900MHz spectrum, respectively.

Table 9-65 QUAD+2 BR Transmitter Parameters




VSWR Less than 2:1



22-Mar-06 6880801E35-E 9-147



Figure 9-15 800 MHz QUAD+2 Carrier Spectrum


9-148 6880801E35-E 22-Mar-06



Figure 9-16 900 MHz QUAD+2 Carrier Spectrum




f ie ld> dpm -otx_all -mnone


22-Mar-06 6880801E35-E 9-149








! CAUTION









9-150 6880801E35-E 22-Mar-06



QUAD+2 BR Receiver Verification: Base Radio with RFDS (Measurement at the top of Rack)

The receiver verification procedure sends a known test signal into the Base Radio via the antenna ports at the top of the rack to verify the receive path. This verification procedure is recommended after replacing a Transceiver, Power Amplifier or Power Supply.Note The following procedure requires the Base Radio to be out of service.


Equipment Setup

Set up equipment for the receiver verification as follows:




4. Disconnect the existing cables from the connectors labeled RX1, RX2, and RX3 at the top of the EBTS rack. If the radio is configured for 2 Branch diversity, disconnect the RX1 and RX2 cables.

Note Connecting the R2660 to the EBTS rack antenna ports will introduce extra system gain into the measurement, which must be accounted for. This must be accounted for in the calibration procedure. (See Calibration of the R2660 output level on page 9-159.).

5. Connect test cables from each of the RX1, RX2, and RX3 connectors (Cables A,B,C in Figure 9-17) to the output ports of the 3-way splitter. For 2 Branch diversity tests, load the RX3 cable with an appropriate 50ohm load or connect it to the RX3 antenna port on the radio.



22-Mar-06 6880801E35-E 9-151



Figure 9-17 QUAD+2 BR w/ RFDS Verification Test Setup






QUAD+2 BR


9-152 6880801E35-E 22-Mar-06



Receiver Verification Procedure: QUAD+2 Base Radio with RFDS


1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the front of the XCVR module and hold for at least three seconds until the BR resets. Using the terminal program on the service computer, log onto the BR. Bold type indicates user input commands.





2. Configure the R2660 to transmit the iDEN inbound 1/6 BER test pattern. Set the Frequency of the R2660 to generate 810 MHz (898 MHz for 900 MHZ). R2660 power out should be set to –80 dBm with modulation.


3. Set RX channel 1 frequency.


field>



22-Mar-06 6880801E35-E 9-153









f ie ld> ppr -orxch1 -r1 -a1005-62




Freq. Offset=0.000000

BER%=0.000000






f ield>


9-154 6880801E35-E 22-Mar-06



BER Floor Measurement: QUAD+2 Base Radio with RFDS

1. Verify that the R2660 is set to 810MHz (898 MHz for 900 MHz) and is producing a power level of -80dBm. (See Receiver Verification Procedure: QUAD+2 Base Radio with RFDS on page 9-153)


3. Check Receiver 1. At the field> prompt, type (inputs are in bold, comments are in italics).
















22-Mar-06 6880801E35-E 9-155



Check Receiver 2:

Check Receiver 3:




























9-156 6880801E35-E 22-Mar-06



Check Receiver 4:

Check Receiver 5:




























22-Mar-06 6880801E35-E 9-157



Check Receiver 6:



The following command returns the kit numbers of the receiver and all other modules. At the field> prompt, type:

















9-158 6880801E35-E 22-Mar-06



Receiver Sensitivity Measurement: QUAD+2 Base Radio with RFDS



1. Verify that the R2660 is set to 810 MHz (898 MHz for 900 MHz QUAD+2 BR) and adjust the output power to a level of -50dBm



b) Attach the included HP 11708A 30dB pad to the Power REF (848ID sensor) output on the front on the 438A.


from the Power REF output.e) Press the “Zero” button on the 438A.f) Wait for Zeroing operation to complete.g) Press “Shift-Zero” to enter the Cal value. This is listed as Cf on the


vs. freq on the Power Sensor. Choose the closest frequency range for the application. For 800/900 MHz measurements, interpolate between 1.0GHz and 0.5GHz to obtain a Cf.

j) For measurement of iDEN 6:1 waveforms, press “Offset” and enter 7.78dB.

3. Disconnect Cable A (see Figure 9-17) from the Base Radio or Antenna Port and connect it to the Power Sensor Head.





7. Path loss must be determined for each Antenna cable A,B,C (see Figure 9-17). If comparable cables are used for all three paths, losses of all three should be approximately the same.


22-Mar-06 6880801E35-E 9-159





10. Set the R2660 to Frequency 810 MHz (898 MHz for 900 MHz QUAD+2 BR) and a Power level of -113.5dBm + path loss.


11. Using the MMI commands below, issue the command to put the BR into single branch mode. If the resulting bit error rate for receiver branches 1, 2, and 3 is less than 8.00%, the receivers passed the test.












f ield> enable -orxch1 -dbr3 -so





9-160 6880801E35-E 22-Mar-06



Check Receiver 2:

Check Receiver 3:




























22-Mar-06 6880801E35-E 9-161



Check Receiver 4:

Check Receiver 5:




























9-162 6880801E35-E 22-Mar-06



Check Receiver 6:



13. As shown below respectively for QUAD+2 Base Radios, the following command returns the kit numbers of the receiver and all other modules. At the field> prompt, type:

















22-Mar-06 6880801E35-E 9-163



Receiver Verification: Measurement of the QUAD+2 Base Radio (No RFDS)

The receiver verification procedure sends a known test signal into the Base Radio to verify the receive path. The signal is fed DIRECTLY into the ANTENNA PORTS in the back of the Base Radio. This excludes the RFDS and antenna cabling from the measurement. This verification procedure is recommended after replacing a Transceiver, Power Amplifier or Power Supply.Note The following procedure requires the Base Radio to be out of service.


Equipment Setup






5. Connect test cables from each of the RX1, RX2, and RX3 connectors (Cables A,B,C in Figure 9-18) to the output ports of the 3-way splitter. For 2 Branch diversity tests, load the RX3 cable with an appropriate 50ohm load or connect it to the RX3 antenna port on the radio.








9-164 6880801E35-E 22-Mar-06



Figure 9-18 QUAD+2 BR Rx Verification Test Setup

.

Receiver Verification Procedure: QUAD+2 Base Radio


1. Power on the BR using the front switch on the Power Supply Module. Press the reset button on the front of the XCVR module and hold for at least three seconds until the BR resets. Using the terminal program on the service computer, log onto the BR. Bold type indicates user input commands.




manufacturing. The password will be changed by the Operations and

QUAD+2 BR


22-Mar-06 6880801E35-E 9-165



Maintenance Center (OMC) as soon as the controller takes a download. The OMC default field password is Motorola.

2. Configure the R2660 to transmit the iDEN inbound 1/6 BER test pattern. Set the Frequency of the R2660 to generate 810 MHz (898 MHz for 900 MHZ). R2660 power out should be set to –80 dBm with modulation.


3. Set RX channel 1 frequency.


Note This step should only be performed if the R2660 is connected directly to the Base Radio Antenna ports. If verification is performed at the top of the rack (adding an RFDS), disregard the above command.



field>


f ie ld> sge -orx_all -soff




9-166 6880801E35-E 22-Mar-06









Freq. Offset=0.000000

BER%=0.000000






f ield>


22-Mar-06 6880801E35-E 9-167



BER Floor Measurement: QUAD+2 Base Radio

1. Verify that the R2660 is set to 810 MHz (898 MHz for 900 MHz) and is producing a power level of -80dBm. (See Receiver Verification Procedure: QUAD+2 Base Radio on page 9-165.)



3. Check Receiver 1:
















9-168 6880801E35-E 22-Mar-06



Check Receiver 2:

Check Receiver 3:





























22-Mar-06 6880801E35-E 9-169



Check Receiver 4:

Check Receiver 5:




























9-170 6880801E35-E 22-Mar-06



Check Receiver 6:



5. The following command returns the kit numbers of the receiver and all other modules. At the field> prompt, type:

















22-Mar-06 6880801E35-E 9-171



Receiver Sensitivity Measurement: QUAD+2 Base Radio

1. Verify that the R2660 is set to 810 MHz (898 MHz for 900 MHz) and adjust the output power to a level of -50dBm.





from the Power REF output.e) Press the “Zero” button on the 438A.f) Wait for Zeroing operation to complete.g) Press “Shift-Zero” to enter the Cal value. This is listed as CF on the


vs. freq on the Power Sensor. Choose the closest frequency range for the application. For 800/900 MHz measurements, interpolate between 1.0GHz and 0.5GHz to obtain a Cf.

j) For measurement of iDEN 6:1 waveforms, press “Offset” and enter 7.78dB.









10. Set the R2660 to Frequency 810 MHz (898 MHz for 900 MHz) and a Power level of -108dBm + path loss.



9-172 6880801E35-E 22-Mar-06





Check Receiver 2:




























22-Mar-06 6880801E35-E 9-173



Check Receiver 3:

Check Receiver 4:









f ie ld> ppr -orxch3-a100 -r1



















9-174 6880801E35-E 22-Mar-06



Check Receiver 5:

Check Receiver 6:




























22-Mar-06 6880801E35-E 9-175







9-176 6880801E35-E 22-Mar-06



The following command returns the kit numbers of the receiver and all other modules. At the BRC> prompt, type:






4. Disconnect the test cable from the RX 1, RX2, and RX3 connectors located on the backplane of the Base Radio.

5. Connect the standard equipment cable to the RX 1, RX2, and RX3 connectors.

6. Restore power to the Base Radio by setting the Power Supply rocker switch to the ON (1) position.This completes the Receiver Verification Procedure.

7. Repeat the Receiver Verification Procedure for each QUAD receiver in every Base Radio in the EBTS.



22-Mar-06 6880801E35-E 9-177


QUAD+2 Channel BR Backplane


Backplane Connectors

The Base Radio backplane includes all external equipment connections. Table 9-66 lists and describes the backplane connectors.

Figure 9-19 and Figure 9-20 shows the locations of the QUAD Base Radio internal (module-side)/external connections.

Table 9-66 QUAD+2 BR Backplane Connectors


AC PS AC AC

J1001 PS DC I/O Signal Vertical Multibeam 4P-24S-2P

P1011 XCVR Signal XCVR VHDM-L

P1012 XCVR Signal XCVR VHDM-L with Guide

P1013 XCVR RF 8 coax Harting Harpak

J1000 PA Signal Signal Elcon Mini-Pak1P-24S-1P

P1010 PA RF RF 6 coax Harting Harpak

P1009 Fan Power Signal Molex 4 Pos Header

P1005 External Wattmeter Dsub-25




J1002 External for Future Use Signal RJ-45 A

J1003 External for Future Use Signal RJ-45 B

P1001 External Ref 10Base2 Ethernet BNC

P1008 External / PS In -48 Vdc Power Input Plus and Minus Contact

P1006 External / Aux Pwr Signal SMA blindmate

P1000 External Ref 5MHz/1PPS BNC


9-178 6880801E35-E 22-Mar-06



Figure 9-19 QUAD+2 Base Radio Backplane Connectors (Module-Side)

J1001 P1009 J1000 P1010

P1013

P1012P1011

AC


22-Mar-06 6880801E35-E 9-179



Figure 9-20 QUAD+2 Base Radio Backplane Connectors (External)

QUAD+2 BR XCVR Connections

SITE CTRL A & B

Alarm (P1005)

DC (P1008)

AUX PWR OUTPUT (P1006)

5MHz/1PPS (P1000)Ethernet (P1001)

RX3 (P1004) RX2 (P1003) RX1 (P1002)

AC

NOTE: Not used in standard product configuration.

(J1002 and J1003)

SEE NOTE

SEE NOTE

SEE NOTE

Base Radio Filter

Table 9-67 XCVR Digital Connector (P1011 and P1012)

Pin I/O Assignment Pin I/O Assignment

P1011

A1 PS MAIN 28VDC D1 NC Reserved

A2 PS MAIN 28VDC D2 Ground

A3 PS MAIN 28VDC D3 Spare

A4 Ground D4 NC Reserved

A5 Ground D5 PS SPI CLK

A6 Spare D6 PS SPI EN

A7 Spare D7 Ground

A8 Ground D8 SPI_A2


9-180 6880801E35-E 22-Mar-06



A9 16.8MHz- D9 NC Reserved

A10 16.8MHz+ D10 PA ENABLE

B1 PS MAIN 28VDC E1 Ground

B2 PS MAIN 28VDC E2 Spare

B3 PS MAIN 28VDC E3 Spare

B4 Ground E4 Spare

B5 Ground E5 PS PRESENT DETECT

B6 Ground E6 SPI MISO

B7 NC Reserved* E7 Ground

B8 Ground E8 SPI_A1

B9 Ground E9 MTR_STAT_

B10 Ground E10 PA PRESENT DETECT

C1 Ground F1 EXT_REF

C2 Ground F2 Ground

C3 Ground F3 NC Reserved

C4 Ground F4 Spare

C5 NC Reserved** F5 PS FAULT INTERRUPT

C6 NC Reserved*** F6 SPI MOSI

C7 NC Reserved**** F7 Ground

C8 SPI_A3 F8 SPI_A0

C9 Spare F9 NC Reserved

C10 NC Reserved F10 PA SPI EN

P1012


A2 NC Reserved D2 Ground

A3 NC Reserved D3 NC Reserved

A4 Ground D4 Ground

A5 EXT_VREV D5 NC Reserved

Table 9-67 XCVR Digital Connector (P1011 and P1012) (continued)



22-Mar-06 6880801E35-E 9-181



A6 Ground D6 Ground


A8 28V_FAN D8 Ground

A9 28V_FAN D9 NC Reserved

A10 28V_FAN D10 PS_SEATED

B1 Ground E1 FAN_DETECT

B2 Ground E2 NC Reserved

B3 NC Reserved E3 Ground

B4 NC Reserved E4 NC Reserved

B5 Ground E5 Ground

B6 EXT_VFWD E6 NC Reserved

B7 Ground E7 Ground

B8 Ground E8 NC Reserved

B9 Ground E9 Ground

B10 28V_FAN E10 NC Reserved

C1 PA SPI CLK F1 FAN FAIL


C3 NC Reserved F3 Ground








* Reserved for Backplane version control (BP_VER_3)** Reserved for Backplane version control (BP_VER_0)*** Reserved for Backplane version control (BP_VER_1)**** Reserved for Backplane version control (BP_VER_2)

Table 9-67 XCVR Digital Connector (P1011 and P1012) (continued)



9-182 6880801E35-E 22-Mar-06



PA Connections

Table 9-68 XCVR RF Connector (P1013)

Pin I/O assignmentRF max,

avg(dBm)Freq

range(GHz)Return

Loss(dB)

B11 Rx1 input 20 DC to 2.5 15

D8 Rx3 input 20 DC to 2.5 15

D11 Rx2 input 20 DC to 2.5 15

B5 Exciter PA Feedback 20 DC to 2.5 15

D2 Exciter PA Forward 20 DC to 2.5 15

B2 Ethernet 20 DC to 2.5 15

Ground A1, A3, A4, A6, A7, A9, A10, A12, C1, C3, C4, C6, C7, C9, C10, C12, E1, E3, E4, E6, E7, E9, E10, E12

Table 9-69 PA DC Connector (J1000)

PinMax. Voltage

(V)Max. I

(A) Description

S6 3.3 0.01 SPI_A0

S4 3.3 0.01 SPI_A1

S8 3.3 0.01 SPI_A2

S7 3.3 0.01 SPI_A3

S2 3.3 0.01 PA SPI EN

S5 3.3 0.01 SPI MISO

S1 3.3 0.01 SPI MOSI

S3 3.3 0.01 PA SPI CLK

S17 ~0 / Open 0.01 PA ENABLE*

S24 12 0.05 NC Reserved

S22 12 0.05 NC Reserved

S12 ~0 / Open 0.01 FAN DETECT

S9 0.2 / Open 0.01 FAN FAIL

S10, S11 30.03 0.5 28V_FAN


22-Mar-06 6880801E35-E 9-183



S19 0 0.1 Ground**

S21 0 0.1 Ground***

S23 0 0.1 Ground****

S15 undefined 0.3 Spare

S13 undefined 0.3 Spare

S16 undefined 0.3 16.8MHz+*****

S18 undefined 0.3 16.8MHz-******

S14 undefined 0.3 NC Reserved

S20 0 0.1 PA PRESENT DETECT*******

B1, B2, B3, B3, B4, B5, B6, B7,

B8, B9, B1030.03 18.5 PS MAIN 28VDC

A1, A2, A3, A4, A5, A6, A7, A8,

A9, A100 18.5 Ground

* PA_Enable logic is as follows: low is enabled, high is disabled** Signal is VVA_FB_Ext inside of PA and allows for PA testing without BR*** Signal is VVA_Fwd_Ext inside of PA and allows for PA testing without BR**** Signal is Seated signal for PA and determines if PA is seated in backplane or not***** Signals are 100ohm differential****** Signals are 100ohm differential******* Signal is grounded inside the PA module

Table 9-69 PA DC Connector (J1000)

PinMax. Voltage

(V)Max. I

(A) Description

Table 9-70 PA RF Connector (P1010)

PinRFmax,avg

(dBm)RFmax, peak

(dBm)Freq Range

(MHz) Description

B2 20 20 32-960 Exciter PA Forward


9-184 6880801E35-E 22-Mar-06



External Connections

B8 20 20 32-960 Exciter PA Feedback

B5, D2, D5, D8 20 20 32-960 Spare

A1, A3, A4, A6, A7, A9, C1, C3, C4, C6, C7, C9, E1, E3, E4, E6, E7, E9

N/A N/A Ground

Table 9-70 PA RF Connector (P1010)

PinRFmax,avg

(dBm)RFmax, peak

(dBm)Freq Range

(MHz) Description

Table 9-71 RF (SMA) Connector (P1002, P1003, and P1004)

Signal Name Description

Rx3 input (P1004) RF input to receiver branch 3 from RMC for stand alone BR



Table 9-72 5MHz/1PPS - Time/Frequency (P1000)

Pin Signal

Center Conductor EXT_REF

Outer Conductor GND

Table 9-73 Site Control Ethernet 10Base2 (P1001)

Pin Signal

Center Conductor Ethernet

Outer Conductor GND


22-Mar-06 6880801E35-E 9-185



Table 9-74 For Future Use - Ethernet/Reference (J1002 & J1003)

Pin Signal

1 ETH_TX+

2 ETH_TX-

3 ETH_RX+

4 TDM_CK+

5 TDM_CK-

6 ETH_RX-

7 TDM_TD+

8 TDM_TD-

Table 9-75 Peripheral - 25-pin Dsub (P1005)

Pin Signal

1

2

3 GND

4

5

6

7

8

9

10 GND

11

12

13

14

15

16 GND


9-186 6880801E35-E 22-Mar-06



PS Connections

17

18 MTR_STAT_

19 EXT_VFWD

20 EXT_VREV

21 GND

22 GND

23

24

25 GND

Table 9-75 Peripheral - 25-pin Dsub (P1005)

Pin Signal

Table 9-76 DC I/O (J1001)

PinMax. Voltage

(V)Max. I

(A) Description

A3 3.3 0.01 SPI_A0

B3 3.3 0.01 SPI_A1

C3 3.3 0.01 SPI_A2

D3 3.3 0.01 SPI_A3

D2 3.3 0.01 PS SPI EN

A2 3.3 0.01 SPI MISO

B2 3.3 0.01 SPI MOSI

C2 3.3 0.01 PS SPI CLK

B5 30.03 0.01 NC Reserved

C5 0.0 0.01 Ground

A4 5.0 0.01 NC Reserved

B4 5.0 0.01 PS FAULT INTERRUPT

C4 0.0 0.1 PS PRESENT DETECT

A1 Spare

B1 Spare


22-Mar-06 6880801E35-E 9-187



C1 Spare

D1 Spare

A5 Spare

D5 Spare

A6 Spare

B6 Spare

C6 Spare

D6 Spare

D4 0.0 0.1 Power Supply Enable

P1_A1, P1_B1, P1_C1, P1_D1, P1_A2, P1_B2, P1_C2, P1_D2 30.03 18.5 PS MAIN 28VDC

P2_A1, P2_B1, P2_C1, P2_D1, P2_A2, P2_B2, P2_C2, P2_D2 30.03 10 28VDC Auxiliary Output

P3_A1, P3_B1, P3_C1, P3_D1, P3_A2, P3_B2, P3_C2, P3_D2, P4_A1, P4_B1, P4_C1, P4_D1, P4_A2, P4_B2, P4_C2, P4_D2

0 18.5 Ground

P6_A1, P6_B1, P6_C1, P6_D1, P6_A2, P6_B2, P6_C2, P6_D2 72 30 BATTERY INPUT (+)

P5_A1, P5_B1, P5_C1, P5_D1, P5_A2, P5_B2, P5_C2, P5_D2 0 30 BATTERY INPUT (-)

Table 9-76 DC I/O (J1001) (continued)

PinMax. Voltage

(V)Max. I

(A) Description

Table 9-77 AC Connector (AC)

Pin Description

1 AC LINE

2 AC GROUND

3 AC NEUTRAL


9-188 6880801E35-E 22-Mar-06



Fan/Alarm Connections

Table 9-78 Aux I/O (P1006)

Pin Description

1

28v Auxiliary Output2

3

4

5

Ground6

7

8

9

No Connect10

11

12

Table 9-79 QUAD+2 DC Input (P1008)

Pin Description

1, 2 BATTERY INPUT (+)

3, 4 BATTERY INPUT (-)

Table 9-80 QUAD+2 Fan Power/Alarm (P1009)

Pin Signal

1 Ground

2 FAN DETECT

3 FAN FAIL

4 28V_FAN


22-Mar-06 6880801E35-E 9-189


QUAD+2 Base Radio Signals


Table 9-81 lists and describes signals for the QUAD+2 Base Radio.

Table 9-81 QUAD+2 Base Radio Signal Descriptions


16.8MHz-16.8MHz differential signal from the Transceiver module to Power Amplifier module

16.8MHz+16.8MHz differential signal from the Transceiver module to Power Amplifier module

28V Auxiliary Ground28VDC Auxiliary Ground - Power Supply return path ground from the Auxiliary I/O connector

Power

28V Auxiliary Output28VDC Auxiliary Output from the Power Supply to the Auxiliary I/O connector

Power

28V_FANGated 28VDC supply from either the Transceiver or PA modules to the front panel Fan Module

Power

AC GROUND Power Supply AC connector ground return Power

AC LINE Backplane connector to Power Supply AC LINE signal Power

AC NEUTRAL Power Supply AC connector NEUTRAL signal Power

BATTERY INPUT (-)Battery (-) 48VDC Input signal from the backplane connector to the Power Supply Module

Power

BATTERY INPUT (+)Battery (+) 48VDC Input signal from the backplane connector to the Power Supply Module

Power

Ethernet

10Base2 Ethernet signal input from the Backplane BNC connector to the RF connector of the Transceiver module

Exciter PA feedback Power Amplifier RF output signal feedback to the Transceiver 50Ω

Exciter PA Forward Transceiver Exciter RF output signal to the Power Amplifier input 50Ω


9-190 6880801E35-E 22-Mar-06



EXT_REF

Site Control 5MHz_1PPS reference signal from the Backplane BNC connector to the Transceiver

EXT_VFWD

External wattmeter forward power signal level from the 25 pin Dsub backplane connector to the Transceiver

EXT_VREV

External wattmeter reverse power signal level from the 25 pin Dsub backplane connector to the Transceiver

FAN DETECT

Signal from the Front Panel fan to the transceiver and PA modules to indicate presence of the front panel fan module

FAN FAILFAN FAIL signal from the Front Panel fan module to the PA and transceiver modules

Fan Ground Ground from the backplane to the front panel fan module

Ground 28VDC return path ground of BR modules to the BR Power Supply

MTR_STAT_

External wattmeter presence detect signal from the 25 pin Dsub connector on the backplane to the Transceiver module

PA ENABLE

Enable control signal from the Transceiver to the Power Amplifier for RF Power Amplifier DC biasing, low is enabled, high is disabled

PA PRESENT DETECT

RF Power Amplifier module signal to the Transceiver indicating it's presence

PA SPI CLKSerial Peripheral Interface clock signal from the Transceiver to the RF Power Amplifier

PA SPI ENSerial Peripheral Interface enable signal from the Transceiver to the RF Power Amplifier

Table 9-81 QUAD+2 Base Radio Signal Descriptions (continued)



22-Mar-06 6880801E35-E 9-191



Power Supply Enable

Enable control signal tied to Ground on the backplane and input to the Power Supply to indicate insertion into the backplane

PS FAULT INTERRUPT

Fault interrupt signal from the Power Supply to the Transceiver

PS MAIN 28VDCPower Supply 28VDC output to Power Amplifier and other BR modules

Power

PS PRESENT DETECT

Signal from the Power Supply module to the Transceiver module indicating the presence of the Power Supply module

PS SPI CLKSerial Peripheral Interface clock signal from the Transceiver to the Power Supply

PS_SEATED

Transceiver input - grounded on the backplane to indicate that the Transceiver seated into slot and Transceiver power can be ramped up

PS_SPI_ENSerial Peripheral Interface enable signal from the Transceiver to the Power Supply

Rx1 input (P1002)RF input to receiver branch 1 from the Receive Multi Coupler (RMC for stand alone BR

50Ω


50Ω


50Ω

Spare Unused pins

SPI MISO

Serial Peripheral Interface Master Input/Slave Output signal from the Power Supply and Power Amplifier to the Transceiver




9-192 6880801E35-E 22-Mar-06



SPI MOSI

Serial Peripheral Interface Master Output/Slave Input signal from the Transceiver to the Power Supply and Power Amplifier

SPI_A0

Serial Peripheral Interface address signal from the Transceiver to the Power Supply and RF Power Amplifier

SPI_A1


SPI_A2


SPI_A3


NC Reserved No Connection but reserved for specific future signals Reserved




22-Mar-06 6880801E35-E 9-193




9-194 6880801E35-E 22-Mar-06

Appendix A

Parts and Suppliers


Overview ......................................................................................A-2

Surge Arrestors ............................................................................A-3

RF Attenuators .............................................................................A-5

Emergency Generator ..................................................................A-7

Portable Generator Connection ...................................................A-8

Site Alarms ...................................................................................A-9

Cabinet Mounting Hardware .......................................................A-11

Cable Connections .....................................................................A-12

Battery System Connections ......................................................A-13

Intercabinet Cabling ...................................................................A-16

Equipment Cabinet Power Connections .....................................A-18

Other Recommended Suppliers .................................................A-20

Spare Parts Ordering .................................................................A-22


1-Dec-06 68P80801E35-E A-1

Parts and Suppliers Volume 2

Overview

Overview 9

This appendix contains recommended part numbers (p/n) and manufacturers for various hardware, tools, and equipment used during installation of the EBTS.

Also contained in this appendix is other installation related information, such as determining types of wire lugs, lengths and sizes of various wires and cables, custom cabling information, and fuses.

All suppliers and model numbers listed are included due to their performance record in previous installations. Motorola cannot guarantee the effectiveness of the installation or performance of the system when using these or other suppliers’ parts.

Addresses, phone numbers, fax numbers, websites, and other information is presented for each of the recommended suppliers, when possible.Note In some listings, phone number and address are for corporate or main

sales office. Other sales locations may be available. Call number given or go to website for expanded listings.

Information herein is subject to change without notice.


A-2 68P80801E35-E 1-Dec-06

Volume 2 Parts and Suppliers

Surge Arrestors

Surge Arrestors 9

Two types of surge arrestors should be used in the EBTS site, including: AC Power and Telco Antenna Surge Arrestors

AC Power and Telco Surge Arrestors

The recommended AC Power and Telco surge arrestors are both manufactured by Northern Technologies. The model numbers are: AC power - LAP-B for 120/240 single-phase

LAP-C for 208 Vac three-phase Telco - TCS T1DS

Northern Technologies

23123 E. MissionLiberty Lake, WA 99019Phone: 800-727-9119Fax: 509-927-0435Internet: http://www.northern-tech.com


1-Dec-06 68P80801E35-E A-3


Surge Arrestors

Antenna Surge Arrestors

The recommended antenna surge arrestors are manufactured by Polyphaser Inc. The following models are recommended: Base Radio antenna (800 MHz tower top amplifier only) - 094-0801T-A

Base Radio antenna (800 MHz cavity combined, transmit only; up to 5 channels) - IS-CT50HN-MA

Base Radio antennas (800 MHz duplexed) - IS-CT50HN-MA

Base Radio antennas (900 MHz duplexed) - 097-0311G-A.2 GPS antennas - 092-082-0T-A

Lightning arrestor bracket kit - Contact your local Motorola Sales representative to order this kit

Receive Tower Top amplifier - 094-0801T-A

Tower top test port cable - IS-50NX-C2

Polyphaser, Inc.

P.O. Box 9000Minden, NV 89423-9000 Phone: 800-325-7170

775-782-2511Fax: 775-782-4476Internet: http://www.polyphaser.com

Motorola has set up several kits that contain the necessary arrestors with proper mounting hardware for the various antenna configurations. Contact your local Motorola representative for these OEM kits.


A-4 68P80801E35-E 1-Dec-06


RF Attenuators

RF Attenuators 9

Several RF attenuators are needed at a site to ensure proper receive adjust-ments. The attenuators are used at the LNA sites to offset the excess gain from the Tower Top amplifiers, to balance the receive path, and to attenuate the BMR signal path. Use the following specifications when choosing vendors: Specified frequency range

800 MHz systems – requires attenuator specification to include 806-821 MHz range

900 MHz systems – requires attenuator specification to include 896-901 MHz range

1 dB increments 0.5 dB accuracy or better Female N connector / Male N connector

Aeroflex / Weinschel

5305 Spectrum DriveFrederick, MD 21703-7362745Phone: 800-638-2048

301-846-9222Fax: 301-846-9116

Internet: http://www.aeroflex-weinschel.com

Alan Industries, Inc.

745 Green Way DriveP.O. Box 1203Columbus, IN 47202Phone: 800-423-5190

812-372-8869Fax: 812-372-5909

Internet: http://www.alanindustries.com

Huber + Suhner, Inc.

19 Thompson DriveEssex, VT 05452Phone: 802-878-0555Fax: 802-878-9880Internet: http://www.hubersuhnerinc.com


1-Dec-06 68P80801E35-E A-5


RF Attenuators

JFW Industries, Inc.

5134 Commerce Square DriveIndianapolis, IN 46237Phone: 877-887-4JFW

317-887-1340Fax: 317-881-6790

Internet: http://www.jfwindustries.com

Pasternack Enterprises

P.O. Box 16759Irvine, CA 92623-6759Phone: 949-261-1920Fax: 949-261-7451

Internet: http://www.pasternack.com

RF attenuators are also needed for test equipment. The attenuators must be used between frequency reference equipment, service monitors, and the Motorola EBTS equipment. The following attenuators should be used at the site during optimization: Female BNC connector / Male BNC connector, 10 dB attenuator (1 W)

between the Rubidium Standard and the R2660 Communications Analyzer. Refer to the System Testing section.

Female BNC connector / Male BNC connector, 30 dB attenuator (1 W) between the Rubidium Standard and the R2660. Refer to the System Testing, section.


A-6 68P80801E35-E 1-Dec-06


Emergency Generator

Emergency Generator 9

Several different sizes of generators are available. Determine the loading requirements of the site prior to ordering a generator. A recommended manufacturer of the emergency backup generator power system is:

Generac Corporation

P.O. Box 8Waukesha, WI 53187Phone: 262-544-4811Fax: 262-544-0770


1-Dec-06 68P80801E35-E A-7


Portable Generator Connection

Portable Generator Connection 9

The recommended portable generator connection is the AJA200-34200RS, manufactured by Appleton Electric. Figure A-1 is a view of a connector located on the building. An adapter may be required if local electrical standards conflict with the wiring configuration.

Figure A-1 Portable Generator Connector

An alternate supplier of the portable generator connection is the ARKTITE Heavy Duty Receptacle Model 80, Style 2, 200 Amps, manufactured by Crouse-Hinds.

Cooper IndustriesCrouse-Hinds, Inc.

P.O. Box 4999Syracuse, NY 13221Phone: 315-477-5531Fax: 315-477-5719

Internet: http://www.crouse-hinds.com

#!"

%


A-8 68P80801E35-E 1-Dec-06


Site Alarms

Site Alarms 9

Three types of alarms should be used in an EBTS site, including: Intrusion Alarm Smoke Alarm Temperature Alarm

Intrusion Alarm The intrusion alarm is the Sonitrol Door contact 29A.

Sonitrol

211 N. Union Street, Suite 350Alexandria, VA 22314Phone: 800-326-7475

703-684-6606Fax: 703-684-6612Internet: http://www.sonitrol.com

Smoke Alarm An available smoke alarm is the Sentrol 320CC. This smoke alarm provides a relay closure for the iMU alarm. These smoke detectors are available from many electrical wholesale distributors. For the location nearest you, call between 6 a.m. and 5 p.m. Pacific Standard Time and ask Sales for the location of the nearest EW (Electric Wholesale) distributor.

Sentrol, Inc.GE Interlogix

12345 SW Leveton DriveTualatin, OR 97062Phone: 800-547-2556

503-692-4052Internet: http://www.sentrol.com


1-Dec-06 68P80801E35-E A-9


Site Alarms

Temperature Alarm The recommended temperature alarm is the Grainger #2E206 thermostat. This alarm is manufactured by Dayton Electronics and distributed by W.W. Grainger:

W.W. Grainger

Locations Nationwide

Phone: 888-361-8649 Internet: http://www.grainger.com


A-10 68P80801E35-E 1-Dec-06


Cabinet Mounting Hardware

Cabinet Mounting Hardware 9

The cabinet mounting hardware is site dependent and must be procured locally.

Equipment Cabinets The mounting hardware used to secure the Equipment Cabinets containing control and/or RF hardware must be able to provide 1545 pounds of retention force. If the cabinets are to be secured to a concrete floor, 1/2” grade 8 bolts with

anchors are recommended. If the cabinets are to be secured to another type of floor, determine the

appropriate mounting hardware.

Power Supply Rack The Motorola offered Power Supply rack from Power Conversion Products is available in a standard and an earthquake rack.

Power Conversion Products, Inc.

115 Erick StreetCrystal Lake, IL 60039-0380Phone: 800-435-4872 (customer service)

815-479-0682Fax: 815-459-0453Internet: http://www.eltekenergy.com

If the earthquake rack is used, it must be bolted to the floor using the 02100-13 High Performance Anchor Kit, consisting of: anchors (qty. 4) load sharing plates (qty. 2) large square washers (qty. 8)

Hendry Telephone Products

55 Castilian DriveSanta Barbara, CA 93117-3080Phone: 805-968-5511Fax: 805-968-9561Internet: http://www.hendry.com


1-Dec-06 68P80801E35-E A-11


Cable Connections

Cable Connections 9

The recommended manufacturer for all wire lugs used during EBTS instal-lation is Thomas & Betts. All wire lug part numbers listed are for Thomas & Betts.

Thomas & Betts

8155 T&B BoulevardMemphis, TN 38125Phone: 800-888-0211 (general information)

800-248-7774 (sales/technical support)Internet: http://www.tnb.comNote Double hole wire lugs are preferred, but single hole wire lugs can be

used where mounting requirements dictate their use.

Selecting Master Ground Bar Lugs

Table A-1 identifies recommended part numbers for wire lugs used to connect chassis ground wiring to the master ground bar from each cabinet.

Selecting Cabinet Ground Lugs

Table A-2 identifies recommended part numbers for wire lugs used to connect chassis ground wiring to the grounding point of each cabinet.

Table A-1 Recommended Master Ground Bar Lugs

Wire Size Wire Type Lug Color Description P/N †

#2 AWG Stranded Brown Single 1/4” diameter hole 54107

#2 AWG Stranded Brown Double 1/4” diameter hole, 5/8” center 54207

#6 AWG Stranded Blue Single 1/4” diameter hole 54105

#6 AWG Stranded Blue Double 1/4” diameter hole, 5/8” center 54205

Note These lugs require the use of the TBM5-S crimping tool. Note † All part numbers are Thomas & Betts.

Table A-2 Recommended Junction Panel Ground Lugs

Wire Size Wire Type Lug Color Description P/N †

#2 AWG Stranded Brown Single 1/2” diameter hole 54145

#6 AWG Stranded Blue Single 3/8” diameter hole E6-12

Note These lugs require the use of the TBM5-S crimping tool.Note † All part numbers are Thomas & Betts.


A-12 68P80801E35-E 1-Dec-06


Battery System Connections

Battery System Connections 9

The cable loop length refers to the total length of wire within a given circuit. For example, the combined length of the -48 VDC (hot) lead and the DC return lead equals the cable loop length. This would mean that a cabinet that needs 16 feet of wire between the batteries and Power Supply Rack has a total loop length of 32 feet.

Determining Battery System Wire Size

The wire size for the connection between the batteries and the Power Supply Rack is determined by the required wire length and the maximum allowable voltage drop. The voltage drop in the loop must be kept to below 200 mV. The wire selected should be UL approved and contain a high number of strands for flexibility.

For a standard configuration, the Power Supply rack is located directly adjacent to the batteries with a cable loop length of 20 feet or less, which requires the use of a 4/0 wire. Table A-3 shows recommended wire sizes for various loop lengths. Larger wire sizes may be used if the recommended sizes are not available. The recommended wire sizes are large enough to allow site expansion to a fully loaded site.

Selecting Battery System Lugs

Depending on the wire size used and the manufacturer of the Batteries, different wire lugs are crimped onto the power cable ends. After the wire size has been determined from Table A-3, verify the manufacturer of the Batteries (Dynasty or Absolyte).

Two different battery systems are offered with the EBTS. The Dynasty system is a low to medium capacity, field expandable system supplied for smaller sites or sites with minimal backup hour requirements. This system is custom designed to Motorola specifications. The Dynasty system is manufactured by Johnson Controls:

Table A-3 Battery System Wire Size

Loop Length Wire size

20 feet 4/0 (or 250 MCM)

30 feet 350 MCM

45 feet 500 MCM


1-Dec-06 68P80801E35-E A-13



C & D TechnologiesDynasty Division

900 East Keefe AvenueP.O. Box 591Milwaukee, WI 53212Phone: 800-396-2789

414-967-6500Fax: 414-961-6506Internet: www.dynastybattery.com

The Absolute IIP battery system is a heavy duty, high capacity battery system manufactured by GNB Technologies:

GNB Technologies

829 Parkview BoulevardLombard, IL 60148Phone: 630-629-5200Fax: 630-629-2635Internet: www.gnb.com/stationary/stat-absp.html

Refer to Table A-4 to determine the proper wire lug for the connection of that wire to the Power Supply rack.

Table A-4 Power Supply Rack Connection Lugs

Wire Size Cabinet Lug Crimp Tool Lug P/N †

4/0 Double 3/8” hole, 1” center TBM5-S 54212

250 MCM Double 3/8” hole, 1” center TBM8-S 54213



Note † All part numbers are Thomas & Betts.


A-14 68P80801E35-E 1-Dec-06



Refer to Table A-5 to determine the proper wire lug for the connection to the batteries, based on the wire size and battery manufacturer. One column lists the selection for Dynasty and the other lists the selection for Absolyte IIP.

Anti-Oxidant Greases

Any one of the following anti-oxidant greases are recommended for connec-tions to the positive (+) and negative (-) terminals of the batteries: No-Ox OxGuard Penetrox

Table A-5 Battery Connection Lugs

Wire Size

Lug Color

Dynasty Absolyte IIP

Description P/N Description P/N

4/0 Purple Double 3/8” hole, 1” center 54212 Single 1/2” hole 54170

250 MCM Yellow Double 3/8” hole, 1” center 54215 Single 1/2” hole 54113

350 MCM Red Double 3/8” hole, 1” center 54218 Single 1/2” hole 54115

500 MCM Brown Double 3/8” hole, 1” center 54220 Single 5/8” hole 54118


1-Dec-06 68P80801E35-E A-15


Intercabinet Cabling

Intercabinet Cabling 9

Ethernet and alarm cables connecting to the junction panels of each cabinet are supplied with the system. These cables may not be suitable for every EBTS site. It may be necessary to locally manufacture cables for a custom fit. Information is provided for both supplied cables and custom cables.

Supplied Cables The cables listed in Table A-6 are supplied with the system. The length of these cables should be sufficient if the considerations outlined in the Pre-Installation section are followed.

Making Custom Cables

If custom Ethernet or 5 MHz cables must be locally manufactured, use the part numbers listed in Table A-7 for ordering the required materials.

Table A-6 Supplied Inter-Cabinet Cabling

Description Qty. P/N †

120" long, N-type Male to N-type male cable 3 0112004B24

108" long, BNC Male-to-BNC Male, RG400 cable

2* 3013943N45

210" long, 8-pin Modular plug cable 1* 3084225N42

186" long, PCCH redundancy control cable 1** 3082070X01

Phasing Harness 1 0182004W04

Note † All part numbers are Motorola.Note * Per RF rack.Note ** Per Control rack.

Table A-7 Parts for Ethernet and 5 MHz Cables


Connector, BNC male As required 2884967D01

Cable, RG400 As required 3084173E01


A-16 68P80801E35-E 1-Dec-06


Intercabinet Cabling

Table A-8 lists the part numbers for custom alarm cables.

Table A-9 lists the part numbers for custom PCCH cables.

Table A-8 Parts for Alarm Cables


Connector, 8-pin modular As required 2882349V01

Cable, 8-wire As required Locally procured

Note † All part numbers are Motorola.

Table A-9 Parts for Extending PCCH Redundancy Control Cables


8-pin male Telco to 8-pin male Telco extension cable, length: as needed

As required Locally procured

Note Motorola does not guarantee proper operation of system if longer PCCH cable is used.Note † All part numbers are Motorola.Note * Per Control rack.


1-Dec-06 68P80801E35-E A-17


Equipment Cabinet Power Connections

Equipment Cabinet Power Connections 9

Selecting Power Connection Lugs

Table A-10 identifies recommended part numbers for lugs used for power connections between the Power Supply rack and the Control and RF Cabinets. The maximum wire size accepted by the Control and RF Cabinets is 2/0. The Control and RF Cabinets use screw type compression connectors and do not require lugs.

Determining Power Connection Wire Size

The cable loop length refers to the total length of wire within a given circuit. For example, the combined length of the -48 VDC (hot) lead and the DC return lead equals the cable loop length. This would mean that a cabinet which needs 16 feet of wire between the Power Supply rack and equipment cabinets has a total loop length of 32 feet.

The wire size for the connection between the Power Supply rack and the equipment cabinets is determined by the required wire length and the maximum allowable voltage drop. The voltage drop in the loop must be kept to below 500 mV. The wire selected should be UL approved and contain a high number of strands for flexibility. Table A-11 shows the recommended wire sizes for various loop lengths of the RF Cabinet. Table A-12 shows the recommended wire sizes for loop lengths of the Control Cabinet

For a standard configuration, the equipment cabinets are located adjacent to the Power Supply rack with a cable loop length less than 35’.

Table A-10 Recommended Power Connection Lugs for Power Supply Rack

Size Lug Color Description P/N †

2/0 Black Double 3/8” hole, 1” center 54210

#2 AWG Brown Double 1/4” hole, 5/8” center 54207

#4 AWG Gray Double 1/4” hole, 5/8” center 54206

#6 AWG Blue Double 1/4” hole, 5/8” center 54205

Note † All part numbers are Thomas & Betts.

Table A-11 Power Connection Wire Size

Loop Length Wire Size

25 feet or less #6 AWG

25 to 40 feet #4 AWG


A-18 68P80801E35-E 1-Dec-06


Equipment Cabinet Power Connections

Each equipment cabinet has a total of four Power Supply Rack connections; two -48 VDC (hot) and two DC return. Each equipment cabinet contains two separate power distribution systems. A single hot wire and a single return wire are used for each side of the bus. Two return leads provide redundancy and allow a uniform wire size to be used for all 48 VDC power distribution system connections.

40 to 60 feet #2 AWG

60 to 130 feet 1/0 AWG

Note The wire sizes listed are large enough to allow full RF Cabinet Base Radio capacity.

Table A-12 Power Connection Wire Size for Control Cabinet


150 feet or less #6 AWG

Table A-11 Power Connection Wire Size (continued)



1-Dec-06 68P80801E35-E A-19


Other Recommended Suppliers

Other Recommended Suppliers 9

The following are the addresses of various suppliers for tools and equipment used during installation of the EBTS.

Test Equipment RubiSource

Symmetricom

2300 Orchard ParkwaySan Jose, California 95131Phone: 408-433-0910Fax: 408-428-7896Internet: http://www.symmetricom.com

Fluke 77 Digital Multimeter

Fluke Corporation

P.O. Box 9090Everett, WA 98206-9090Phone: 800-44-FLUKE

425-347-6100Fax: 425-356-5116Internet: http://www.fluke.com

Drive Test Equipment

A PC can be used for EBTS optimization and field service. The following are the minimum requirements: 19,200 bps serial port one floppy drive communication software, such as Smartcomm II or Procomm Plus

A drive test application is only available for the PC platform and is currently called iFTA (iDEN Field Test Application). Contact your local Motorola sales representative for more information.


A-20 68P80801E35-E 1-Dec-06


Other Recommended Suppliers

Software ProComm Plus software

Symantec Corporation

20330 Stevens Creek Blvd.Cupertino, CA 95014Phone: 408-517-8000Internet: http://www.symantec.com


1-Dec-06 68P80801E35-E A-21


Spare Parts Ordering

Spare Parts Ordering 9

Motorola Inc.

Accessories and Aftermarket Division

Attn: Order Processing

1307 E. Algonquin RoadSchaumburg, IL 60196

Returns:2222 Glavin DriveElgin, IL 60123

Phone: 800-422-4210 (sales/technical support)Fax: 847-538-8198

Newark Electronics

Call for a local phone number in your area to order parts

Phone: 800-463-9275 (catalog sales)773-784-5100

Fax: 847-310-0275Internet: http://www.newark.com


A-22 68P80801E35-E 1-Dec-06



N O T E S . . .


1-Dec-06 68P80801E35-E A-23




A-24 68P80801E35-E 1-Dec-06

Index0

AAlert

Caution with symbol definition ............................... xiCaution without symbol definition .......................... xi

Danger definition ................................................... xi

definitions .............................................................. xi

Important definition ............................................... xiNote definition ....................................................... xi

Warning definition ................................................. xi

BBase Radio

40W, 800 MHz Power Amplifier TLF2020 (version 1580A)...........................................9-11

40W, 800 MHz Power Amplifier TLF2020 (version 1580B)...........................................9-11

70W, 800 MHz Power Amplifier TLN3335 (version CTF1040) ......................................9-15

70W, 800 MHz Power Amplifier TLN3335 (version CTF1050) ......................................9-15

800 MHz, 3X Receiver CLN1283 and 900 MHz, 3X Receiver CLN1356 ................................................... 3-23, 7-5, 7-11 ............................................................ 7-3, 7-10 ......................................................................7-4 ............................................................ 7-7, 7-12

Backplane connector information (Base Radio section) .................................... 9-22, 9-66, 9-117, 9-178

Base Radio Controller ..........................................2-4, 2-18, 2-28, 2-39 ...................................2-7, 2-21, 2-32, 2-43, 3-9

Base Radio/Base Radio FRU replacement procedures (Base Radio section) ........................................9-6, 9-42, 9-82, 9-136

Controls and indicators (Base Radio section) ...................................1-4, 1-9, 1-16, 1-21, 1-27

DC Power Supply .............................................. 6-4, 6-7, 6-10, 8-2 ................................................6-1, 6-6, 6-9, 8-1 ..................................................... 6-5, 6-8, 6-11

Exciter ............................................... 4-3, 4-12, 4-16 ............................................ 4-4, 4-9, 4-13, 4-17

Overview (Base Radio section) .................. 1-3, 1-8, 1-9, 1-15, 1-20, 1-25, 2-15

Performance specifications (Base Radio section) ....... 1-4, 1-16, 1-21, 1-27

Station verification procedures (Base Radio section) ................ 9-9, 9-45, 9-86

Theory of operation (Base Radio section) .................................1-6, 1-13, 1-18, 1-23, 1-30

CCaution with symbol

General Safety definition ....................................... xi

Caution without symbolGeneral Safety definition ....................................... xi

DDanger


Document ConventionsGeneral Safety ...................................................... xi

keystrokes ............................................................. xi

mouse clicks ......................................................... xi

new terms ............................................................. xiscreen output ........................................................ xi

sub-menu commands ........................................... xi

user input .............................................................. xi

GGeneral Safety

Caution with symbol definition .............................. xi

Caution without symbol definition ......................... xi

Danger definition ................................................... xidocument conventions .......................................... xi

Important definition ............................................... xi

Note definition ....................................................... xiWarning definition ................................................. xi

IImportant


KKeystrokes

document conventions .......................................... xi

MMouse clicks


NNew Terms


NoteGeneral Safety definition ....................................... xi

PParts and Suppliers (Appendix B)SScreen Output


Sub-Menu Commandsdocument conventions .......................................... xi

UUser Input


WWarning



1-Dec-06 68P80801E35-E INDEX-1

Index 0

N O T E S . . .


INDEX-2 68P80801E35-E 1-Dec-06

MOTOROLA and the Stylized M logo are registered in the U.S. Patent andTrademark Office. All other product or service names are the property oftheir respective owners.© Motorola, Inc. 2006

68P80801E35-E