ec303 memory elements new

CHAPTER 5. Memory Element

Amir Abu BakarElectrical Engineering

DepartmentPTSS

EC303 – COMPUTER ARCHITECTURE & ORGANIZATION

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Learning Outcomes

After learning of this chapter, student should be able:-

To know the computer memory organization

To understand Virtual Memory OrganizationTo understand cache memoryTo understand decoderTo realize connecting memory chips to

computer bus

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Brainstorming

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Computer Memory Organization

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Memory

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Main memory consists of a number of storage locations, each of which is identified by a unique address

The ability of the CPU to identify each location is known as its addressability

Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 16, 24, 32 or as many as 64 bits.

A large word length improves system performance, though may be less efficient on occasions when the full word length is not used

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Block Diagram of Memory

• An M-bit data value can be read or written at each unique N-bit address• Read operation- take data out of the specified address in the memory• Write operation – put data into a specified address in memory

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Memory

2N words(M-bit per word)Read/Write

Chip Select(Chip Enable)

M-bit Data Output(for Read/Write)

M

• Example: Byte-addressable 2MB memory M = 8 (because of byte-

addressability) N = 21 (1 word = 8-bit)

N-bit address lines

N

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D7

D2D1

D0

A10

A8

A7

A0

2K x 82K x 8

R/WCS

RAM CHIP

• Design a 2K x 8 memory chips

0 = Write1 = Read

CS = CHIP SELECTCS = 0 enables the output buffers

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Describe the buses line to interface memory

• In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.

How the RAM chip works?

a) Data bus -Carry informationb) Address bus- Determine where it

should be sentc) Control bus - Determine its

operation

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OPERATION OF µP SYSTEM (Fetch & Execute Cycles cont…)

• Read Cycle :- CPU sends a signal via control bus. If the

bus is busy, CPU is put on Wait state.- If the bus is free, CPU will place instruction

address on the address bus.- This address will be decoded or translated

by the circuitry in the memory or I/O interface.

- Finally the data at the specific address is obtained and is placed on the data bus.

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OPERATION OF COMPUTER SYSTEM – Fetch & Execute Cycles Cont..

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• Write cycles :- Write cycle enables CPU sends data to the

memory or I/O devices.- CPU will send a signal (request to write) to

the control bus.- If the data bus is free, the data is placed

on the data bus, whereas the location address will be placed on the address bus.

- CPU will then send the data to the destination with respect to the address.

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RAM CHIP

• Design a 8-word 3 bit RAM chip ?

D2D1D0 8 X 38 X 3

R/WCS

A0

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Q & A

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How to design a 1Mx8 computer system using 1Mx4 memory chips

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Building Memory in Hierarchy

• Design a 1Mx8 using 1Mx4 memory chips

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D3

D2

D1

D0

A19A18A17

A0

1Mx41Mx4

R/WCS

D7

D6

D5

D4

A19A18

1Mx41Mx4

R/WCS

A17

A0CS

Prof. Sean Lee’s Slide, Georgia Tech

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Q & A

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How to design a 2Mx4 using 1Mx4 memory chips

1) How many chip ? Chip needed = system needed chip used2) Calculate the address line for chip used3) Calculate the address line for system4) Decide the decoder needed

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A19A18A17

A0

1Mx41Mx4

R/WCS

A19A18A17

A0

1Mx41Mx4

R/WCS

A20 1-to-2Decoder

CS

1

0

D3

D2

D1

D0


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Q & A

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How to design a 64Kx8 computer system using 16Kx8 memory chips

1) How many chip ? Chip needed = system needed chip used2) Calculate the address line for chip used3) Calculate the address line for system4) Decide the decoder needed

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• Design a 64Kx8 using 16kx8 memory chips

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A13A12A11

A0

16kx816kx8

CS R/W

A13A12A11

A0

16kx816kx8

CS R/W

A13A12A11

A0

16kx816kx8

CS R/W

A13A12A11

A0

16kx816kx8

CS R/W

D7

D6

D5

D4

D3

D2

D1

D0

A13A12A11

A0

A14

2-to-4Decoder

CS

1

0


A152

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Memory Organization Example

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1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4 words x 8 bits 2-to-4

Decoder

A0

A1

CS

Chip Select

Wordline (WL)

BitLine

Modified from Prof Sean Lee’s Slide, Georgia Tech

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How to Address Memory

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0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

2-to-4

DecoderA0=1

A1=0

Access address = 0x1

CS

Chip Select=1

4 words x 8 bits


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Storage Hierarchies :Computer data storage often called storage or memory, refers to

computer components and recording media that retain digital data. Data storage is one

ofthe core functions and fundamental components of computers.

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PRIMARY STORAGE

• Primary storage (or main memory or internal memory), often referred to simply as memory, is the only one directly accessible to the CPU. The CPU continuously reads instructions stored there and executes them as required. Any data actively operated on is also stored there in uniform manner.

RAM:• Processor registers are located inside the processor. Each register typically holds a

word of data (often 32 or 64 bits). CPU instructions instruct the arithmetic and logic unit to perform various calculations or other operations on this data (or with the help of it). Registers are the fastest of all forms of computer data storage.

• Processor cache is an intermediate stage between ultra-fast registers and much slower main memory. It's introduced solely to increase performance of the computer. Most actively used information in the main memory is just duplicated in the cache memory, which is faster, but of much lesser capacity.

• Main memory is directly or indirectly connected to the central processing unit via a memory bus. It is actually two buses ): an address bus and a data bus. The CPU firstly sends a number through an address bus, a number called memory address, that indicates the desired location of data. Then it reads or writes the data itself using the data bus.

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SECONDARY STORAGE

• Secondary storage (also known as external memory or auxiliary storage), differs from primary storage in that it is not directly accessible by the CPU. The computer usually uses its input/output channels to access secondary storage and transfers the desired data using intermediate area in primary storage. Secondary storage does not lose the data when the device is powered down—it is non-volatile.

• Example: Flash drive, CD and DVD drives, floppy disks, punch cards.

TERTIARY STORAGE • Tertiary storage or tertiary memory, provides a third level of storage. Typically it

involves a robotic mechanism which will mount (insert) and dismount removable mass storage media into a storage device according to the system's demands; this data is often copied to secondary storage before use.

• Example: useful for extraordinarily large data stores, accessed without human operators(robotic arms). Typical examples include tape libraries and optical jukeboxes.

Off-line storage• Off-line storage is a computer data storage on a medium or a device that is not under

the control of a processing unit. The medium is recorded, usually in a secondary or tertiary storage device, and then physically removed or disconnected. It must be inserted or connected by a human operator before a computer can access it again. Unlike tertiary storage, it cannot be accessed without human interaction.

• Example : Optical discs and flash memory devices

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Memory Devices Hierarchy

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Memory HierarchyTypical Memory Parameters

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As you can see in the diagram above, the CPU accesses memory according to a distinct hierarchy. Whether it comes from permanent storage (the hard drive) or input (the keyboard), most data goes in random access memory (RAM) first.

The CPU then stores pieces of data it will need to access, often in a cache, and maintains certain special instructions in the register. We'll talk about cache and registers later.

All of the components in your computer, such as the CPU, the hard drive and the operating system, work together as a team, and memory is one of the most essential parts of this team.

From the moment you turn your computer on until the time you shut it down, your CPU is constantly using memory

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The most important parameters of a memory system are:

Capacity - the maximum number of units of data that it can store.

Access time - the time taken to access the data in memory.

Data transfer rate - the number of bits per second at which data can be read.

Cycle time - A measure of low often a memory can be accessed.

Cost - Usually expressed in terms of dollars per bit.

Mainly the computer memory system is divided into two:

Internal memory External memory

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Virtual Memory Organization

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Introduction

Solves problem of limited memory spaceCreates the illusion that more memory

exists than is available in systemTwo types of addresses in virtual memory

systemsVirtual addresses – Referenced by processesPhysical addresses- Describes locations in main

memory

Memory management unit (MMU)Translates virtual addresses to physical address

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Virtual Memory System

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Virtual memory combines active RAM and inactive memory in disk form into a large range of contiguous addresses.

– Solves problem of limited memory space– Creates the illusion that more memory exists than is available in system

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Virtual Memory System

• A virtual memory system offers the following benefits: It presents a simple memory programming model to

applications so that application developers need not know how the underlying memory hardware is arranged.

It allows processes to see linear ranges of bytes in their address space, regardless of the physical layout or fragmentation of the real memory.

It gives us a programming model with a larger memory size than available physical storage (e.g., RAM) and enables us to use slower but larger secondary storage (e.g., disk) as a backing store to hold the pieces of memory that don’t fit in physical memory.

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TWO common approaches of Virtual Memory Organization

• Two common approaches of Virtual Memory Linear Virtual Memory Segmented Virtual Memory

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How Virtual Memory is Organized?

• Virtual memory is organized by either:- paging or segmentation

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Paging

• Virtual memory is divided into fixed-size blocks called pages typically a few kilobytes should be a natural unit of transfer to/from disk

• Page replacement LRU, MRU, Clock… etc

• Page placement Fully associative - efficient

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Paging

• Page Identification Virtual address is divided into

<virtual page number, page offset> The virtual page number is translated into a

physical page number Provides indirection

• Indirection is always good

Translation cached in a buffer

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Segmentation

• Supports user view of memory. • Virtual memory is divided into

variable length regions called segments

• Virtual address consists of a segment number and a segment offset <segment-number, offset>

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• Paging Paging is memory management technique where

memory divided into equal parts like 4k,4k,4k, etc. When Primary memory space is less than processor swap the virtual memory from Secondary memory that time if virtual memory configured into paging technique than only page will be swap as per requirement similarly if need more virtual space than similar space of 4k block will swap for the e.g.:-if there is need of 16kb data than 4pages will be swap like 4k,4k,4k,4k.

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• Segmentation Very few systems use the concept of segmentation for

implementing virtual memory. In segmentation memory is divided in variable size

segments. Segment number and an offset within the segment together form a virtual address.

If a processor wants a particular data item it first looks up for its segment number in a segment table to find a segment descriptor.

Segment descriptor gives information whether the offset within the segment is less than the length of the segment and if it isn't an interrupt is generated to notify that the segment is found.

If the processor is unable to find the segment in the main memory it generates a hardware interrupt prompting the operating system to swap in the segment.

The operating system then searches for the segments that were not in use for a long time and swaps them out of main memory in order to make space for the new segments to be read in.

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Contrast Paging Vs Segmentation

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• Paging: Block replacement

easy• Fixed-length blocks

• Segmentation: Block replacement

hard• Variable-length

blocks• Need to find

contiguous, variable-sized, unused part of main memory

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• Paging: Invisible to application

programmer No external

fragmentation There is internal

fragmentation • Unused portion of

page Units of code and data

are broken up into separate pages

• Segmentation: Visible to application

programmer No internal

fragmentation• Unused pieces of

main memory There is external

fragmentation Keeps blocks of code

or data as single units

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Cache Memory

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Cache- Introduction

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• Small amount of fast memory• Sits between normal main memory and CPU• May be located on CPU chip or module

Small capacity, fast

Large capacity, slow

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• Is an intermediate buffer between CPU and main memory.

• Objective :- to reduce the CPU waiting time during the main memory accesses.

• Without cache memory, every main memory access results in delay in instruction processing.

• Due to main memory access time is higher than processor clock period.

• High speed CPU’s time wasted during memory access (instruction fetch, operand fetch or result storing)

• To minimize the waiting time for the CPU, a small but fast memory is introduced as a cache buffer between main memory and CPU

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• A portion of program and data is brought into the cache memory in advance.

• The cache controller keeps track of locations of the main memory which are copied In cache memory

• When CPU needs for instruction or operand, it receives from the cache memory (if available) instead of accessing the main memory.

• Thus the memory access is fast because the slow main memory appears as a fast memory.

• The cache memory capacity is very small compared to main memory but the speed is several times better than main memory.

• Transfer between the CPU and cache memory usually one word at a time.

• The cache memory usually can be physically with processor IC as internal cache, also known as on-chip cache.

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Cache Memory Structure

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Cache consists of C-lines.

Each line contains K words and a tag of a few bits.

The number of words in the line referred as line size.

Tag- a portion of main memory address.

Each line includes a tag identifies which particular block is currently being stored.

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Cache Operation - Overview

• CPU requests contents of memory location• Check cache for this data• If present, get from cache (fast)• If not present, read required block from

main memory to cache• Then deliver from cache to CPU• Cache includes tags to identify which block

of main memory is in each cache slot

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Typical Cache Organization

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Direct mapping cache example

• In a direct mapping cache with a capacity of 16 KB and a line length of 32 bytes, determine the following;

i) How many bits are used to determine the byte that a memory operation references within the cache line?

ii) How many bits are used to select the line in the cache that may contain the data.

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Direct mapping

• Each block of main memory maps to only one cache line i.e. if a block is in cache, it must be in one

specific place• Address is in two parts• Least Significant w bits identify unique word• Most Significant s bits specify one memory

block• The MSBs are split into a cache line field r

and a tag of s-r (most significant)

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Direct Mapping Address Structure : Example

Tag Line or Slot Word

s-r r w

• EXAMPLE : TAG=8, LINE = 14, WORD=2• 24 bit address• 2 bit word identifier (4 byte block)• 22 bit block identifier

8 bit tag (=22-14) 14 bit slot or line

• No two blocks in the same line have the same Tag field• Check contents of cache by finding line and checking

Tag

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Direct Mapping Cache Line Table

Cache line Main Memory blocks held 0 0, m, 2m, 3m…2s-m

1 1,m+1, 2m+1…2s-m+1. .. .. .

m-1 m-1, 2m-1,3m-1…2s-1

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Direct Mapping Cache Organization

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Direct Mapping Example

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Decoder

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Decoder• A decoder is a device which does the reverse of an encoder, undoing

the encoding so that the original information can be retrieved.

Four-output decoder and a parallel decoder

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Determine the digital circuit in a tree-type decoding network with 16 output lines

• The first stage is a 2-to-4-line decoder. A new variable is introduced in each successive stage; it or its inverse becomes one input to each of the two-input AND gates in this stage. The second input to each AND gate comes from the preceding stage. For example, one of the outputs of the second stage will be AB'C. This will result in two outputs from the next stage, AB'CD and AB'CD'. This design does avoid the fan-out problem in the early stages but not in the later stages. Nevertheless, the problem exists only for the variables introduced in those stages.

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A balanced multiplicative decoder network

• Requires the minimum number of diodes

• This decoder circuit is the fastest and most regular.

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Connecting Memory Chips To Computer Bus

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Describe the buses line to interface memory

• In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.

How the RAM chip works?

a) Data bus -Carry informationb) Address bus- Determine where it

should be sentc) Control bus - Determine its

operation

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Read cycle for a RAM chip• Read Bus Cycle: Describes the operations carried out by the processor

when a memory read is executed.

Step of Read Bus Cycle:• Processor initiates a read bus cycle by floating the address of the memory

location on the address lines.• Once the address lines are stable, the processor asserts the address strobe

signal on the bus. The address strobe signals the validity of the address lines.

• Processor then sets the Read/Write* signal to high, i.e. read.• Now the processor asserts the data strobe signal. This signals to the memory

that the processor is ready to read data.• The memory subsystem decodes the address and places the data on the

data lines.• The memory subsystem then asserts the data acknowledge signal. This

signals to the processor that valid data can now be latched in.• Processor latches in the data and negates the data strobe. This signals to the

memory that the data has been latched by the processor.• Processor also negates the address strobe signal.• Memory subsystem now negates the data acknowledgement signal. This

signals the end of the read bus cycle.

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Read cycle

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• Write Bus Cycle: Sequence of operations in memory write is described here.

Step of Write Bus Cycle:• Processor initiates a write bus cycle by floating the address of the memory

location on the address lines.• Once the address lines are stable, the processor asserts the address strobe

signal on the bus. The address strobe signals the validity of the address lines.• Processor then sets the Read/Write* signal to low, i.e. write.• The processor then places the data on the data lines.• Now the processor asserts the data strobe signal. This signals to the memory

that the processor has valid data for the memory write operation.• The memory subsystem decodes the address and writes the data into the

addressed memory location.• The memory subsystem then asserts the data acknowledge signal. This signals

to the processor that data has been written to the memory.• Then the processor negates the data strobe, signaling that the data is no

longer valid.• Processor also negates the address strobe signal.• Memory subsystem now negates the data acknowledgement signal, signaling

an end to the write bus cycle.

Write cycle for a RAM chip

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Design interface chip for 8K X 3 RAM

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How CPU read from memory and write to memory

The computer loads the operating system (OS) from the hard drive into the system's RAM. Generally, the critical parts of the operating system are maintained in RAM as long as the computer is on.

This allows the CPU to have immediate access to the operating system, which enhances the performance and functionality of the overall system.

When you open an application, it is loaded into RAM. To conserve RAM usage, many applications load only the essential parts of the program initially and then load other pieces as needed.

After an application is loaded, any files that are opened for use in that application are loaded into RAM.

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When you save a file and close the application, the file is written to the specified storage device, and then it and the application are purged from RAM.

In the list above, every time something is loaded or opened, it is placed into RAM. This simply means that it has been put in the computer's temporary storage area so that the CPU can access that information more easily.

The CPU requests the data it needs from RAM, processes it and writes new data back to RAM in a continuous cycle. In most computers, this shuffling of data between the CPU and RAM happens millions of times every second.

When an application is closed, it and any accompanying files are usually purged (deleted) from RAM to make room for new data. If the changed files are not saved to a permanent storage device before being purged, they are lost.

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Static Random Access Memory (SRAM)

• Typically each bit is implemented with 6 transistors (6T)

• Read operation The bitline and its inverse are precharged to Vdd (1) Then set Wordline (WL) high Depending on the value stored, either bitline or ~bitline goes low

• Write operation Put the new value on Bitline and its inverse on ~Bitline Then set the Wordline to high

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BitLineBitLine

Wordline (WL)


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Dynamic Random Access Memory (DRAM)

• 1-transistor DRAM cell

• Write operation Put value on bitline and then set WL=1

• Read operation Precharge bitline to Vdd (1) Assert WL to 1

• Storage decays, thus requires periodic refreshing Read bitline data and write it periodically to keep the value in the memory cell

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Bitline

Wordline (WL)


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Memory Description

• Capacity of a memory is described as # addresses x Word size

• Examples:

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Memory # of addr # of data lines

# of addr lines

# of total bytes

1M x 8 1,048,576

8 20 1 MB

2M x 4 2,097,152

4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304

32 22 16 MB

16K x 64 16,384 64 14 128 KB

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Example

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Memory with 2 Decoders

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0

1

2

3

8 words x 4 bits2-to-4

RowDecoder

A1

A2

1-to-2 Column Decoder

D0D1D2D3

TristateBuffer (read)

0 1

A0

CS

Chip Select CS


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Read Operation

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0

1

2

3

8 words x 4 bits

A1

A2

D0D1D2D3

0 1

A0 = 0

CS

Chip Select CS

Rd/Wr = 0


2-to-4

RowDecoder


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Write Operation

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0

1

2

3

A1

A2

D0D1D2D3

0 1

A0 = 1

CS

Chip Select CS

Rd/Wr = 1


8 words x 4 bits2-to-4

RowDecoder


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D3

D2

D1

D0

A19A18A17

A0

1Mx41Mx4

R/WCS

D7

D6

D5

D4

A19A18

1Mx41Mx4

R/WCS

A17

A0CS


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A19A18A17

A0

1Mx41Mx4

R/WCS

A19A18A17

A0

1Mx41Mx4

R/WCS

A20 1-to-2Decoder

CS

1

0

D3

D2

D1

D0


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A19A18A17

A0

1Mx41Mx4

CS R/W

A19A18A17

A0

1Mx41Mx4

CS R/W

A19A18A17

A0

1Mx41Mx4

CS R/W

A19A18A17

A0

1Mx41Mx4

CS R/W

D7

D6

D5

D4

D3

D2

D1

D0

A19A18A17

A0

A20 1-to-2Decoder

CS

1

0


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Read-Only Memory (ROM)

• Non-volatile memory Permanent binary information is stored Power off does not erase information stored

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ROM

2k words(N-bit per word)

N-bit Data OutputK-bit address lines NK


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32 x 8 (32 words x 8 bits) ROM

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32 X 8 ROM85

0123

28293031

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder

Each represents 32 wires


• To read the cell, the bitline is weakly pulled HIGH. Then, the wordline is turned ON If the transistor is present, it pulls the bitline LOW If the transistor is not present, the bitline remanins HIGH

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Programming the 32x8 ROM

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A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 1 1 0 0 0 1 0 1

0 0 0 0 1 1 0 0 0 1 0 1 1

0 0 0 1 0 1 0 1 1 0 0 0 0

… … … … … … … … … … … … …

1 1 1 0 1 0 0 0 1 0 0 0 0

1 1 1 1 0 0 1 0 1 0 1 1 0

1 1 1 1 1 1 1 1 0 0 0 0 1

012

293031

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder


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Other Flavors of ROMs

• Reprogrammable ROMs EPROM (Erasable Programmable ROM)

• Use UV (Ultra Violet) light for erasing

EEPROM (Electrically Erasable Programmable ROM)

• Flash memory Read and Writable Non-volatile

• Power off does not erase information stored

• Modern ROMs are not really read-only They can be reprogrammed as well

• Flash memory has become extremely popular to store large amounts of data in portable systems such as cameras and music players

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The End

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ec303 memory elements new

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