ece 260b – cse 241a parasitic extraction 1 ece260b – cse241a winter 2005 parasitic extraction...
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ECE 260B – CSE 241A Parasitic Extraction 1 http://vlsicad.ucsd.edu
ECE260B – CSE241A
Winter 2005
Parasitic Extraction
Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B – CSE 241A Parasitic Extraction 2 http://vlsicad.ucsd.edu
Conventional Design Flow
Funct. Spec
Logic Synth.
Gate-level Net.
RTL
Layout
Floorplanning
Place & Route
Front-end
Back-end
Behav. Simul.
Gate-Lev. Sim.
Stat. Wire Model
Parasitic Extrac.
ECE 260B – CSE 241A Parasitic Extraction 3 http://vlsicad.ucsd.edu
Technology Scaling
Process technology evolves with shrinking feature sizes
Parasitic effects become more significant with smaller feature sizes Increasing wire resistance, fringing and coupling capacitances...
Interconnect delay dominates VLSI system performance
The performance of today’s DSM ICs is strongly determined by the parasitic effects of the passive structures interconnecting active devices
Accurate, high-speed tools and methods are needed to extract and simulate these parasitic effects in order to perform precise timing analysis to the circuit
ECE 260B – CSE 241A Parasitic Extraction 4 http://vlsicad.ucsd.edu
Layout Parasitic Extraction
Necessary step after routing Back-annotation
Account for non-ideal nature of interconnect Wire capacitance Wire and via resistance
Parasitic information is used in post-layout verification Timing verification of synchronous circuits Functional verification of asynchronous circuits
Design performance is ultimately limited by parasitics
ECE 260B – CSE 241A Parasitic Extraction 5 http://vlsicad.ucsd.edu
Parasitic Extraction: Why do we need it?
Example: to produce RC tree network for elmore delay analysis
Example: to produce RC tree network for capacitive cross-talk analysis
R1
C1
s
R 2
C2R 4
C4
C3
R3
Ci
Ri
1
2
3
4
i
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 6 http://vlsicad.ucsd.edu
Parasitic Extraction
Parasitic Extraction
thousands of wirese.g. critical pathe.g. gnd/vdd grid
tens of circuitelements for gate level spice simulation
identify some ports
produce equivalent circuit that models response of wires at those ports
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 7 http://vlsicad.ucsd.edu
Parasitic Extraction (the two steps)
ElectromagneticAnalysis
million of elements
thin volume thin volume filamentsfilamentswith constant with constant currentcurrent
small surface small surface panelspanelswith constant with constant chargecharge
Model OrderReduction
tens of elements
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 8 http://vlsicad.ucsd.edu
Parasitic Extraction / Back-Annotation
Input data Technology data
- Metal and via resistances- Capacitance coefficients
Library data- Input pin capacitances
Design data- Routing- Boundary conditions (load and drive information)
Output data Parasitic information:
- DSPF- RSPF- Set_load
Interpreted parasitic information- Custom WLM- LEF coefficients
ECE 260B – CSE 241A Parasitic Extraction 9 http://vlsicad.ucsd.edu
Active Device Parasitics
Gate output capacitance mainly from gate oxide tox
Substrate coupling resistances and capacitances
Characterized by cell libraries
Figure courtesy, A. Nardi
ECE 260B – CSE 241A Parasitic Extraction 10 http://vlsicad.ucsd.edu
Interconnect Parasitics
Wires are not ideal. Parasitics:
Resistance Capacitance Inductance
Why do we care? Impact on delay noise energy consumption power distribution
Picture from “Digital Integrated Circuits”, Rabaey, Chandrakasan, Nikolic
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 11 http://vlsicad.ucsd.edu
Wire
ViaGlobal (up to 5)
Intermediate (up to 4)
Local (2)
Passivation
Dielectric
Etch Stop Layer
Dielectric Capping Layer
Copper Conductor with Barrier/Nucleation Layer
Pre Metal DielectricTungsten Contact Plug
SEMATECH Prototype BEOL stack, 2000
•Slide courtesy of Chris Case, BOC Edwards
ECE 260B – CSE 241A Parasitic Extraction 12 http://vlsicad.ucsd.edu
Interconnect Resistance
W
L
T
R = T W
L
Sheet ResistanceR
R1 R2
Resistance seen by current going from left to right is same in each block
ECE 260B – CSE 241A Parasitic Extraction 13 http://vlsicad.ucsd.edu
Resistance Scaling
• Resistance scales badly
• True scaling would reduce width and thickness by S each node
• R ~ S2 for a fixed line length and material
• Reverse scaling wires get smaller and slower, devices get smaller and faster
• At higher frequencies, current crowds to edges of conductor (thickness of conduction = skin depth) increased R
ECE 260B – CSE 241A Parasitic Extraction 14 http://vlsicad.ucsd.edu
Interconnect Capacitance
w S
Line dimensions: W, S, T, H
Sometimes H is called T in the literature, which can be confusing
Lateral cap
ECE 260B – CSE 241A Parasitic Extraction 15 http://vlsicad.ucsd.edu
Capacitance Estimation
• Empirical capacitance models are easiest and fastest
• Handle limited configurations (e.g., range of T/H ratio)
• Some limiting assumptions (e.g., no neighboring wires)
• Rules of thumb: e.g., 0.2 fF/um for most wire widths < 2um
• Cf. MOSFET gate capacitance ~ 1 fF/um width
• Pattern-matching approaches applied to multilayer cross-sections
5.025.0
06.106.177.0ILD
wire
ILDILDoxwire H
T
H
W
H
WC
Capacitance per unit length
ECE 260B – CSE 241A Parasitic Extraction 16 http://vlsicad.ucsd.edu
Inductance Inductance is the flux induced by current variation
Measures ability to store energy in the form of a magnetic field
Consists of self-inductance and mutual inductance terms
At high frequencies, can be significant portion of total impedance Z = R + jL ( = 2f = angular freq)
1S2S
1111
1
dsBS
2112
2
dsBS
I
Self InductanceI11
d
d
I12
Mutual Inductanced
d
ECE 260B – CSE 241A Parasitic Extraction 17 http://vlsicad.ucsd.edu
Coil Inductance
V = L d I/d t V2 = M12 d I1/d t
Faraday’s lawV = N d (B A) / d t
B = (N / l) I
L = N2 A / l
V = voltage
N = number of turns of the coil
B = magnetic flux
A = area of magnetic field circled by the coil
l = height of the coil
t = time
ECE 260B – CSE 241A Parasitic Extraction 18 http://vlsicad.ucsd.edu
Filament Inductance
Where the integral is over the volume of the conductors,
r is the position in a given filament, and
li is the unit vector in the direction of current flow for conductor i
dVdVrr
ll
aaL
i jV V
ji
jiij '
|'|4 '
ECE 260B – CSE 241A Parasitic Extraction 19 http://vlsicad.ucsd.edu
Inductance Scaling
If where
Copper interconnects R is reduced
Faster clock speeds
Thick, low-resistance (reverse-scaled) global lines
Chips are getting larger long lines large current loops
Frequency of interest is determined by signal rise time, not clock frequency
RL
rtf
1
22
Massoud/Sylvester/Kawa, Synopsys
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
ECE 260B – CSE 241A Parasitic Extraction 20 http://vlsicad.ucsd.edu
Inductance Trends Inductance = weak (log) function of conductor dimensions
Inductance = strong function of distance to current return path (e.g., power grid) Want nearby ground line to provide a small current loop (cf. Alpha 21164)
Inductance most significant in long, low-R, fast-switching nets
Clocks are most susceptible
ECE 260B – CSE 241A Parasitic Extraction 21 http://vlsicad.ucsd.edu
Inductance is Important …
On-chip inductance is negligible, and usually alleviate performance degradation due to the presence of capacitance
Seesaw effect between inductance and capacitance
Package inductance is significant when coupled with large magnitude of currents in the same frequency range
Complete analysis needs to include package inductance since signals cannot be assumed ideal at pads
For the idealized case of a lossless homogeneous dielectric with an array of conductors, the inductance matrix [L] can be derived directly from the capacitance matrix [C] by
where v0 is the phase velocity of the medium
However in the IC domain, these assumptions do not hold up and we need inductance extraction
120
][1
][ Cv
L
ECE 260B – CSE 241A Parasitic Extraction 22 http://vlsicad.ucsd.edu
Inductance Return Path
Inductance is a loop quantity
Knowledge of return path is required, but hard to determine
For example, the return path depends on the frequency
Signal Line
Return Path
Massoud/Sylvester/Kawa, Synopsys
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
ECE 260B – CSE 241A Parasitic Extraction 23 http://vlsicad.ucsd.edu
Frequency-Dependent Return Path
At low frequency, and current tries to minimize impedance minimize resistance use as many returns as possible (parallel resistances)
At high frequency, and current tries to minimize impedance minimize inductance use smallest possible loop (closest return path) L dominates, current returns
“collapse” Power and ground lines always available as low-impedance current returns
Signal Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
)( LjR
)( LR
)( LR )( LjR
Signal Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
ECE 260B – CSE 241A Parasitic Extraction 24 http://vlsicad.ucsd.edu
Extracting Inductance vs. Capacitance
Capacitance Locality problem is easy: electric field lines “suck up” to nearest
neighbor conductors Boundary element approach requires discretization of only the
surfaces of conductors Charge density over the conductor is rarely uniform, needs to solve
the integral form of Laplace’s equation for many times
Inductance Locality problem is hard: magnetic field lines are not local; current
returns can be complex Local calculation is easy: no strong geometry dependence;
analytic formulae work very well Current density and direction is constant in each conductor when
the frequency is low enough to ignore the skin effect Conductors are divided into bundles of filaments each with a
constant current density, compute a circuit solution for return current distribution
ECE 260B – CSE 241A Parasitic Extraction 25 http://vlsicad.ucsd.edu
Outline
Problem Statement
Parasitics
Extraction Methods Resistance extraction Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave)
Future Trends
ECE 260B – CSE 241A Parasitic Extraction 26 http://vlsicad.ucsd.edu
Interconnect Resistance Extraction
Sheet resistance R□
Series resistance
R = R□ * Length / Width / Thickness
Inaccuracies arise in irregular geometries, e.g., corners of a route Apply Laplace’s equation 2=0, or
Discretize an interconnect conductor into grids
Solve a partial differential equation with known boundary conditions
Table Lookup for better efficiency
0
Eij ij
ji
R
VV
02
2
2
2
2
2
zyx
ECE 260B – CSE 241A Parasitic Extraction 27 http://vlsicad.ucsd.edu
Outline
Problem Statement
Parasitics
Extraction Methods Resistance extraction Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave)
Future Trends
ECE 260B – CSE 241A Parasitic Extraction 28 http://vlsicad.ucsd.edu
C_fringe C_fringe
C_parallel
Parasitic Extraction Accuracy
Above 0.5μm feature size, wire cross-section was rectangular
Interconnect modeled as parallel plate over ground plane Parallel plate capacitance Fringe capacitance
2-D extraction accurate enough: Area + Fringe
ECE 260B – CSE 241A Parasitic Extraction 29 http://vlsicad.ucsd.edu
Capacitance Extraction
2-D extraction Wire cap includes parallel plate (area), fringing, and coupling cap C = k1 Area + k2 Perimeter + k3 Coupling_length / Coupling_spacing These coefficients are fit in for an average environment of a wire Table Lookup Intra-layer capacitances are not well modeled
3-D extraction Solve for real 3-D geometries of wiring
2.5-D extraction Compromise between speed and
accuracy Models 3-D effects by a combination
of two orthogonal 2-D structures E.g., two cross-section views on the
x-z and y-z planes, z is the vertical axis going through layers
ECE 260B – CSE 241A Parasitic Extraction 30 http://vlsicad.ucsd.edu
How Capacitance Extractor Works Technology pre-characterization
generates coefficients through solving the 3-D equations for “representative” sample of topologies
Really, cross-sections through “tunnel” that contains a section of the victim net
Creates look-up table Time consuming, but only done once Each layer of interconnect added roughly doubles time for
coefficient generation
Pattern compression Reduces the total number of pre-characterization patterns
Geometric parameter extraction Reduce the number of geometric parameters considering the
shielding effect
Extraction matches topologies to entries in look-up table
ECE 260B – CSE 241A Parasitic Extraction 31 http://vlsicad.ucsd.edu
Extraction to Floating Metal
Dummy fills (as floating metals) are required by modern CMP process
Extraction to floating metal similar to extraction for cross talk analysis Net to net capacitance required Effective capacitance to floating metal dependent on potential of
floating metal E.g., Cadence HyperExtract models floating metal as grounded If we model floating metal as grounded, this is pessimistic
Below 0.18m with “local fill” requirements, fill metal can impact timing
Floatingmetal
ECE 260B – CSE 241A Parasitic Extraction 32 http://vlsicad.ucsd.edu
Capacitive ExtractionExample: Intel 0.25 micron Process
5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric.Taken from “Digital Integrated Circuits”, 2nd Edition, Rabaey, Chandrakasan, Nikolic
fringing parallel
Consider only electric field (capacitive) couplingSlide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 33 http://vlsicad.ucsd.edu
Capacitive ExtractionWhy? E.g. Analysis of Delay of Critical Path
ECE 260B – CSE 241A Parasitic Extraction 34 http://vlsicad.ucsd.edu
Capacitance ExtractionProblem Formulation
Given a collection of N conductors (of any shape and dimension)
fringing parallel
qvC ?
Calculate the couplingcapacitance matrix C
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 35 http://vlsicad.ucsd.edu
Capacitance ExtractionSolution Procedure
For i = 1 to N, apply one volt to conductor i and ground all the others
NiN
i
i
q
q
q
C
C
C
2
1
,
,2
,1
0
1
01iv?iq?q
?q ?q ?q
?q
solve the electrostatic problem and find the resulting vector of charges on all conductors
that is the i-th column of the conductance matrix
2
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 36 http://vlsicad.ucsd.edu
Overview
Problem Statement
Parasitics
Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave)
Future Trends
ECE 260B – CSE 241A Parasitic Extraction 37 http://vlsicad.ucsd.edu
Picture Thanks to Coventor
Inductance and Resistance ExtractionExample: IC package
package
IC
wirebonding
lead frames
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 38 http://vlsicad.ucsd.edu
Inductance and Resistance ExtractionWhere do we need to account for inductance? chip to package and package to board connections are highly
inductive
inductance can create Ldi/dt noise on the gnd/vdd network
inductance can limit communication bandwidth
inductive coupling between leads or pins can introduce noise
IC
on-package decouplingcapacitors
on-boarddecoupling capacitors
packagePCB
pins or solder ballsfrom package to PCB
wire bonding and lead framesor solder balls from IC to package
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 39 http://vlsicad.ucsd.edu
Inductance and Resistance Extraction Why also resistance? Skin and Proximity effects
proximity effect: opposite currents in nearby conductors attract each other
skin effect: high frequency currents crowd toward the surface of conductors
Simple ExampleSimple Example
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 40 http://vlsicad.ucsd.edu
Inductance and Resistance ExtractionSkin and Proximity effects (cont.) Why do we care?
Skin and proximity effects change interconnect resistance and inductance
hence they affect performance (propagation delay) and noise (magnetic coupling)
When do we care? frequency is high enough that wire width OR thickness are less than
two “skin-depths” e.g. on PCB at and above 100MHz e.g. on packages at above 1GHz e.g. on-chip at and above 10GHz note. clock at 3GHz has significant harmonics at 10GHz!!
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 41 http://vlsicad.ucsd.edu
Inductance and Resistance ExtractionProblem Formulation
Given a collection of interconnected N wires of any shape and dimension
Identify the M input ports Picture byPicture byM. ChouM. Chou
viLjR ??
Calculate the MxM resistance and the inductance matrices for the ports,
that is the real and immaginary part of the impedance matrix
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 42 http://vlsicad.ucsd.edu
Inductance and Resistance ExtractionSolution Procedure
Typically instead of calculating impendance we calculate the admittance matrix.
For each pair of input terminals,
ivY
ivZ
ivLjR
1
1
MiM
i
i
i
i
i
Y
Y
Y
2
1
,
,2
,1
0
1
0
0
2
J
AjJ
JA
apply a unit voltage source and
solve magneto quasit-static problem (MQS) to calculate all terminal currents
that is one column of the admittance matrix [R+jwL]-1
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 43 http://vlsicad.ucsd.edu
Overview
Problem Statement
Parasitics
Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave)
Future Trends
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 44 http://vlsicad.ucsd.edu
Combined RLC ExtractionExample: current distributions on powergrid
input terminals
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 45 http://vlsicad.ucsd.edu
Combined RLC Extraction Example: analysis of resonances on powergrid
* 3 proximity templates per cross-section- 20 non-uniform thin filaments per cross-section
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 46 http://vlsicad.ucsd.edu
Combined RLC ExtractionExtraction Example: analysis of substrate coupling
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 47 http://vlsicad.ucsd.edu
Combined RLC ExtractionExample: resonance of RF microinductors
At frequency of operation the current flows in the spiral and creates magnetic energy storage (it works as an inductor: GOOD)
Picture thanks to Univ. of PisaPicture thanks to Univ. of Pisa
But for higher frequencies the impedance of the parasitic capacitors is lower and current prefers to “jump” from wire to wire as displacement currents (it works as a capacitor: BAD)
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 48 http://vlsicad.ucsd.edu
Combined RLC ExtractionProblem Formulation
Given a collection of interconnected N wires of any shape and dimension
Identify the M input ports Picture byPicture byM. ChouM. Chou
viZ ?
Calculate the MxM IMPEDANCE matrix for the ports,
that is the real and immaginary part of the impedance matrix
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 49 http://vlsicad.ucsd.edu
Combined RLC ExtractionSolution Procedure Same as RL extraction.
Typically calculate admittance matrix
For each pair of input terminals,
ivY
MiM
i
i
i
i
i
Y
Y
Y
2
1
,
,2
,1
0
1
0
jJn
J
AjJ
JA
ˆ
0
2
2 apply a unit voltage source and solve electro-magneto quasit-static problem (EMQS) to calculate all terminal currents
that is one column of the admittance matrix [R+jwL]-1
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 50 http://vlsicad.ucsd.edu
Outline
Problem Statement
Parasitics
Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave)
Future Trends
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 51 http://vlsicad.ucsd.edu
The Electromagnetic Interference (EMI)Problem description
Electronic circuits produce and are subject to Electromagnetic Interference (EMI). in particular when wavelengths ~ wire lengths
EMI is a problem because it can severely and randomly affect analog and digital circuit functionality!!!
PCBPCB
ICIC
PCPCBB
ICIC
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 52 http://vlsicad.ucsd.edu
EMI analysisEMI at board, package and IC level Traces on PCB can pick up
EMI and transmit it to IC’s
IC’s can produce high frequency conducted emissions that can radiate from PCB’s
IC’s themselves can directly produce radiated emissions high-frequency current loops
Vdd-decap-gnd on package or inside IC’s.
high-frequency current loops inside IC (near future)
IC radiation amplified by heat sinks!
PCBPCB
PCBPCB
ICIC
ICIC
ICIC
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 53 http://vlsicad.ucsd.edu
EMI a problem for ICs design?
So far: dimensions too small and wavelengths too large
Trend: larger chip dies and higher frequencies
Future’s IC: • clocks ~ 3GHz• harmonics ~ 30GHz • wavelengths ~ 1cm • dimensions ~ 1cm
Today’s PCB:• clocks ~ 300MHz• harmonics ~ 3GHz• wavelengths ~ 10cm• dimensions ~ 10cm
d
d
this gives resonances on PCB today,this gives resonances on PCB today,hence it might on IC tomorrow!hence it might on IC tomorrow!
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 54 http://vlsicad.ucsd.edu
EMI analysisSolution Procedure Typically, EMI analysis is a two-step process:
1) determine accurate current distributions on conductors
2) calculate radiated fields from the current distributionsEE
1I
2I
1I
2ISlide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 55 http://vlsicad.ucsd.edu
Need for full-board analysis Interconnect impedances depend on complicated return
paths.
Unbalanced currents generate most of the interference.
Hence need FULL-BOARD analysis
1I
12 II
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 56 http://vlsicad.ucsd.edu
jJn
J
AjJ
JA
ˆ
0
22
22
Need for full-wave analysis
Circuit dementions are not negligible compared to wavelength
dt
dIi
d
ct
dt
dILv i
jij ,
coupling NOT instantaneus,speed of light creates retardation
d
Need to solve FULLWAVE equations (same as for RLC extraction plus wave term)
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 57 http://vlsicad.ucsd.edu
Industry
Mentor – xCalibre
Synopsys – Raphael
Cadence – Simplex Fire & Ice, Celestry Nautilus
Frequency – Columbus
MIT – FastCap, FastHenry, etc. http://rel-vlsi.mit.edu/fastcap
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 58 http://vlsicad.ucsd.edu
Outline
Problem Statement
Parasitics
Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave)
Future Trends
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 59 http://vlsicad.ucsd.edu
Future Trends
Accuracy and efficiency improvement to handle increasing large designs and increasing complex structures
Growing inductance effect What happen on PCB today will be in ASIC tomorrow
Combining parasitic extraction and model order reduction to characterize interconnect in Laplace domain transfer function parameters (poles, residues) directly
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 60 http://vlsicad.ucsd.edu
Parasitic Extraction (the two steps)
ElectromagneticAnalysis
million of elements
thin volume thin volume filamentsfilamentswith constant with constant currentcurrent
small surface small surface panelspanelswith constant with constant chargecharge
Model OrderReduction
tens of elementsSlide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 61 http://vlsicad.ucsd.edu
Thanks