ece 331 – digital system design multi-bit adder circuits, adder/subtractor circuit, and multiplier...
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ECE 331 – Digital System Design
Multi-bit Adder Circuits,Adder/Subtractor Circuit,
andMultiplier Circuit
(Lecture #12)
ECE 331 - Digital System Design 2
Implementations of Multi-bit Adders:
1. Ripple Carry Adder2. Carry Lookahead Adder
ECE 331 - Digital System Design 3
Ripple Carry Adder
Multi-bit Adder Circuits
ECE 331 - Digital System Design 4
FA
x n – 1
c n c n 1 ”
y n 1 –
s n 1 –
FA
x 1
c 2
y 1
s 1
FA
c 1
x 0 y 0
s 0
c 0
MSB position LSB position
Ripple Carry Adder
Carry ripples from one stage to the next
Carry-inCarry-out
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Ripple Carry Adder in VHDL
2 2
2
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Ripple Carry Adder in VHDL
library ieee;use ieee.std_logic_1164.all;use work.pack.all;
ENTITY add3bit ISPORT (a : IN std_logic_vector(2 downto 0);
b : IN std_logic_vector(2 downto 0); cin : IN std_logic; s : OUT std_logic_vector(2 downto 0); cout : OUT std_logic);
END add3bit;
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Ripple Carry Adder in VHDL
ARCHITECTURE struct OF add3bit IS
SIGNAL cin1, cin2: std_logic;
BEGINfa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 );fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 );fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout );
END struct;
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Ripple Carry Adder in VHDL
Cin Cout
ARCHITECTURE struct OF add3bit IS
SIGNAL cin1, cin2: std_logic;
BEGINfa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 );fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 );fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout );
END struct;
ECE 331 - Digital System Design 9
Ripple Carry Adder in VHDL
ARCHITECTURE struct OF add3bit IS
SIGNAL cy : std_logic_vector (3 downto 0);
BEGINfa0: fa PORT MAP(a(0),b(0),cy(0), s(0), cy(1));fa1: fa PORT MAP(a(1),b(1),cy(1), s(1), cy(2));fa2: fa PORT MAP(a(2),b(2),cy(2), s(2), cy(3));
END struct;
Cin Cout
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Ripple Carry Adder in VHDLARCHITECTURE struct OF add3bit IS
SIGNAL cy : std_logic_vector (3 downto 0);
BEGIN Adders:
FOR i IN 0 TO 2 GENERATE myfa:fa PORT MAP(a(i),b(i),cy(i),s(i),cy(i+1)); END GENERATE;
cout <= cy(3);cy(0) <= cin;
END struct;
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The Ripple Carry Adder is slow!
Why?
How can the speed of the adder be increased?
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Increasing the speed of the Adder
Method A: Include all inputs and outputs in the design
Inputs = Xi, Yi, Cin,i; Outputs = Si, Cout,i
1-bit 3 inputs 2 outputs 2-bit 5 inputs 3 outputs 4-bit 9 inputs 5 outputs
n-bit 2n+1 inputs n+1 outputs
Large number of operands, but only 2 logic levels Increase in speed Increase in area required
decrease propagation delay
increase # of logic gates
Use Truth Table and K-Map to derive logic functions
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Increasing the speed of the Adder
Method B: Manipulate the Boolean Expressions
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Carry Lookahead Adder
Multi-bit Adder Circuits
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Carry Lookahead Adder
1 0 0 1
0 0 1 1+
1
Carry Generate
1 1 0 1
Carry End
11
Carry Propagate
0 1 1 1
1 0 1 0
0 0 0 1
0 0
1 0
1 0
11
X
Y
ECE 331 - Digital System Design 16
Carry Lookahead Adder
Carry Generate G
i = X
i . Y
i
Always generates a carry if Gi evaluates to
true. Carry Propagate
Pi = X
i + Y
i
Generates a carry if Pi evaluates to true AND
there was a Carry-In. Propagates the Carry-In if true.
ECE 331 - Digital System Design 17
x 1 y 1
g 1 p 1
s 1
Stage 1
x 0 y 0
g 0 p 0
s 0
Stage 0
c 0
c 1 c 2
carry-in
carry generate
carry propagate
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Carry Lookahead Adder
The Carry Generate (Gi) and Carry Propagate (P
i)
can be created directly from the inputs.
no ripple delay only 1 gate delay
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Carry Lookahead Adder
Cout,i
is a function of Gi and P
i
Cout,i
= (Xi.Y
i) + ( (X
i + Y
i).(C
in,i) )
This is the Cout
of the Full Adder
Cout,i
= (Gi) + ( (P
i).(C
in,i) )
where Cin,i
= Cout,i-1
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Carry Lookahead Adder
For the LSB, C
out,i = (G
0) + ( (P
0).(C
in,0) )
no ripple delay
ECE 331 - Digital System Design 21
Carry Lookahead Adder
For LSB+1:
Cout,1 = (G1) + ( (P1) . Cin,1 )
Cout,1 = (G1) + ( (P1) . Cout,0 )
Cout,1 = (G1) + ( (P1) . (G0 + P0.Cin,0) )
Cout,1 = G1 + P1.G0 + P1.P0.Cin,0 All G and P terms derived directly from
associated inputs No ripple delay
ECE 331 - Digital System Design 22
Carry Lookahead Adder
For LSB+2:
Cout,2 = (G2) + ( (P2) . Cin,2 )
Cout,2 = (G2) + ( (P2) . Cout,1 )
Cout,2 = (G2) + ( (P2) . (G1 + P1.Cin,1) )
Cout,2
= (G2) + ( (P
2) . (G
1 + P
1.C
out,0) )
Cout,2 = G2 + P2.G1 + P2.P1.Cout,0
Similar for LSB+3, LSB+4, etc.
Must be expanded in terms of G
0, P
0,
and Cin,0
ECE 331 - Digital System Design 23
x 1 y 1
g 1 p 1
s 1
x 0 y 0
s 0
c 2
x 0 y 0
c 0
c 1
g 0 p 0
ECE 331 - Digital System Design 24
Carry Lookahead Adder Sum: S
i is a function of X
i, Y
i, and C
in,i
Si = X
i xor Y
i xor C
in,i
Si = X
i xor Y
i xor C
out,i-1
Carry: Cout,i
derived from Gi and P
i
Gi and P
i are functions of the inputs
Carries do not ripple from one stage to the next Delay ~ log
2(n)
Area required ~ (n)*(log2(n))
Greater than area required for RCA
ECE 331 - Digital System Design 25
Carry Lookahead Adder
74LS283: 4-bit Binary Adder with Fast Carry
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Hierarchical Design:
Building a bigger Adder
Multi-bit Adder Circuits
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Block
x31 24–
c32 c24
y31 24–
s31 24–
x15 8–
c16
y15 8–
s15 8–
c8
x7 0– y7 0–
s7 0–
c03Block
1Block
0
Hierarchical Design
Carry Lookahead Adder
Ripple carry (between blocks)
ECE 331 - Digital System Design 28
Adder / Subtractor using Two's Complement
ECE 331 - Digital System Design 29
Adder / Subtractor using Two’s Complement
Could build separate binary adder and subtractor Not common
Use Two’s Complement integer representation Addition uses binary adder Subtraction uses binary adder with the Two’s
Complement representation for the subtrahend Issues
Cannot directly convert the most negative n-bit binary number to Two’s complement representation
Must detect overflow
ECE 331 - Digital System Design 30
s 0 s 1 s n 1 –
x 0 x 1 x n 1 –
c n n -bit adder
y 0 y 1 y n 1 –
c 0
Add Sub control
Adder / Subtractor
ECE 331 - Digital System Design 31
Detecting Overflow
Compare sign of operands with sign of result Overflow occurs if operands have same sign
and result has different sign Addition of two positive #s results in negative # Addition of two negative #s results in positive #
Logic function(s) for overflow (for a 4-bit Adder)
Overflow = X3.Y
3.S
3' + X
3'.Y
3'.S
3
Overflow = C3 xor C
4 = C
3'.C
4 + C
3.C
4'
ECE 331 - Digital System Design 32
Multiplier Circuit
ECE 331 - Digital System Design 33
Multiplier Circuit
Multiplication requires two basic operations: Addition Logical Shift
A binary multiplier circuit can be designed hierarchically using
Full Adders AND gates
ECE 331 - Digital System Design 34
Binary Multiplication
1 1 1 0
1 1 1 01 0 1 1
1 1 1 0
1 0 0 1 1 0 1 0
Multiplicand MMultiplier Q
Product P
(11)(14)
(154)
+
1 0 1 0 10 0 0 0+
0 1 0 1 0
1 1 1 0+
Partial product 0
Partial product 1
Partial product 2
4 bits
4 bits
8 bits
# of bits in P = # of bits in M + # of bits in Q
ECE 331 - Digital System Design 35
Binary Multiplication
M (Multiplicand) = m3m2m
1m
0
Q (Multiplier) = q3q
2q
1q
0
PP0 = m3.q0 m
2.q
0 m
1.q
0 m
0.q
0
0 pp03 pp0
2 pp0
1 pp0
0
+ m3.q1m
2.q
1 m
1.q
1 m
0.q
1 0
PP1 = pp14 pp13 pp1
2 pp1
1 pp1
0
partialproduct
ECE 331 - Digital System Design 36
Multiplier Circuit
PP1
PP2
ECE 331 - Digital System Design 37
Multiplier Circuit
Bit of PPi