ece 331 – digital system design sequential circuit design (lecture #23) the slides included herein...
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![Page 1: ECE 331 – Digital System Design Sequential Circuit Design (Lecture #23) The slides included herein were taken from the materials accompanying Fundamentals](https://reader036.vdocuments.net/reader036/viewer/2022062320/56649d755503460f94a5662a/html5/thumbnails/1.jpg)
ECE 331 – Digital System Design
Sequential Circuit Design
(Lecture #23)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
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Fall 2010 ECE 331 - Digital System Design 2
Material to be covered …
Chapter 16: Sections 1 – 5
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Fall 2010 ECE 331 - Digital System Design 3
Sequential Circuit Design• Understand specifications
• Draw state graph (to describe state machine behavior)
• Construct state table (from state graph)
• Perform state minimization (if necessary)
• Encode states (aka. state assignment)
• Create state-assigned table
• Select type of Flip-Flop to use
• Determine Flip-Flop input equations and FSM output equation(s)
• Draw logic diagram
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Sequential Circuit Design
1. Given the problem statement, determine the required relationship between the input and output sequences and derive a state table. For many problems it is easiest to first construct a state graph.
2. Reduce the table to a minimum number of states. First, eliminate duplicate rows by row matching and, then, form an implication table and follow the procedure in Section 15.3.
3. If the reduced table has m states (2n – 1 < m ≤ 2n), n flip-flops are required. Assign a unique combination of flip-flop states to correspond to each state in the reduced table. The guidelines given in Section 15.8 may prove helpful in finding an assignment which leads to an economical circuit.
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Sequential Circuit Design1. Form the transition table by substituting the assigned flip-flop
states for each state in the reduced state table. The resulting transition table specifies the next states of the flip-flops and the output in terms of the present states of the flip-flops and the input.
2. Plot next-state maps and input maps for each flip-flop and derive the flip-flop input equations. (Depending on the type of gates to be used, either determine the sum-of-products form from the 1’s on the map or the product-of-sums form from the 0’s on the map.) Derive the output functions.
3. Realize the flip-flop input equations and the output equations using the available logic gates.
4. Check your design by signal tracing, computer simulation, or laboratory testing.
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Examples
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Design a sequential logic circuit to realize the following state table:
Example #1: FSM Design
P.S. N.S. Z
X = 0 X = 1
a i c 1
b b i 1
c c g 1
d i c 0
e d e 0
f i c 0
g e f 0
h h a 1
i a c 1
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Design in progress …
Example #1: FSM Design
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Example #1: FSM Design
My solution using D Flip-Flops:
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The author's solution using D Flip-Flops:
Example #1: FSM Design
Stateassignment
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Example #1: FSM Design
My solution using JK Flip-Flops:
![Page 16: ECE 331 – Digital System Design Sequential Circuit Design (Lecture #23) The slides included herein were taken from the materials accompanying Fundamentals](https://reader036.vdocuments.net/reader036/viewer/2022062320/56649d755503460f94a5662a/html5/thumbnails/16.jpg)
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The author's solution using JK Flip-Flops:
Example #1: FSM Design
![Page 20: ECE 331 – Digital System Design Sequential Circuit Design (Lecture #23) The slides included herein were taken from the materials accompanying Fundamentals](https://reader036.vdocuments.net/reader036/viewer/2022062320/56649d755503460f94a5662a/html5/thumbnails/20.jpg)
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Future site of a second example.
Example #2: FSM Design
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Questions?