ece 353 introduction to microprocessor systems michael j. schulte week 11
DESCRIPTION
Why Use Interrupts? Maximize processor utilization and efficiency Allow use of sleep/idle states when nothing to do to save power Minimize latency in responding to complex input/output structures Facilitate event driven applicationsTRANSCRIPT
ECE 353Introduction to Microprocessor Systems
Michael J. Schulte
Week 11
TopicsInterrupt Concepts80C188EB Interrupt HandlingHardware Interrupts80C188EB Interrupt Control Unit (ICU)Interrupt Service Routines (ISRs)Interrupt Driven SystemsSoftware Interrupts and ExceptionsInterrupt Priority and LatencyInterrupt ControllersDebugging Interrupt Hardware and Software
Why Use Interrupts?Maximize processor utilization and efficiencyAllow use of sleep/idle states when nothing to do to save powerMinimize latency in responding to complex input/output structuresFacilitate event driven applications
Interrupt PrimerTerminology Event – an occurrence that the processor
must respond to Asynchronous events – events that occur at
unpredictable times while program is running Pending interrupt – an IRQ signal has been
received, but it has not been serviced yet. Interrupt Service Routine (ISr) – the code
executed in response to an IRQ signal. Interrupt-driven I/O – I/O devices that use
interrupts to signal when they require service Critical code section – a section of code that
cannot be interrupted
Basic Interrupt Hardware
Types of Interrupts Maskable interrupt – an interrupt that
can be disabled when desired Nonmaskable interrupt (NMI) – an
interrupt that cannot be disabled. Level-sensitive interrupts – an
interrupt request is said to exist whenever the IRQ signal is at the designated level
Edge-sensitive interrupts – an interrupt is only recognized on the signal’s transition
Multiple Interrupt SourcesMultiple interrupt sources handled by Polled interrupts - single ISR is invoked
for all interrupts and ISR must check all the possible interrupt sources
Vectored interrupts - each interrupt source is associated with a unique ISR and the processor hardware selects the correct ISR The starting address of the ISR is obtained
from a look-up table (vector table) Interrupt processing begins at a fixed, unique
location based on the interrupt source
Multiple Interrupt Structure
G IEIERIFR
FFDevice
#1
FFDevice
#2
FFDevice
#3
FFDevice
#4
CPU
IRQ 0
IRQ 1
IRQ 2
IRQ 3
Interrupt PriorityPriority schemes determine the order in which interrupts are serviced
Software Interrupts & Exceptions
Software interrupts provide another mechanism for changing control flow Interrupt instructions – Often used by
applications to communicate with OS x86 features the INT <type> instruction
Exceptions – software interrupts that are invoked by some unusual condition Division by zero Page fault
80C188EB Interrupts
Interrupt Processing Sequence
Saved and Restored StateState saved
on interrupt
Save restored with RETI
Interrupt Vector TableEach interrupt is identified by an 8-bit type codeThe interrupt vector table contain 256 32-bit ISR starting addresses (IP, CS)
Starts at 00000h Not relocatable in the 80C188 1024 bytes long (1KB)
Structure
Initializing Interrupt Vectors
mov di, INT_TYPE * 4clipush dsxor ax, axmov ds, ax ;segment 0000hmov ax, offset ISR_Xmov [di], ax ;load offsetmov ax, seg ISR_Xmov [di+2], ax ;load segmentpop dssti
80C1888EB Hardware Interrupts
Modular core interrupts INTR – Generated by ICU
Interrupt Enable Flag (IF) STI / CLI
NMI – Nonmaskable interrupt HALT – Causes CPU to stopInterrupt example Hardware Software (vector table)
80C188EB ICUPerforms synchronization and prioritization of interrupts to CPU (block diagram)Functions Masking (IMASK, PRIMSK) Priorities (TCU/SCU, INT0-1, INT2-4)
Default Synchronization/prioritization (REQST, INSERV) External interrupts (INT0-1, INT2-4) Internal interrupts (TCU/SCU, INTSTS)Polling interrupt sources (POLLSTS, POLL)
Interrupt Service RoutinesISR prerequisitesISR implementation Context save Clear IRQ FF (if necessary) Allow nesting (if desired) Handle interrupt Clear INSERV bit Context restore IRET
EOI register use (EOI)Shared procedures and resources
Interrupt Driven SystemsForeground vs. background tasksEvents determine order of execution
Initialization
Main ProgramLoop
ISRcISRbISRa
Software Interrupts & Exceptions
INT instructionExceptions Divide error Single-step Breakpoint INTO BOUND Invalid Opcodes ESC
Interrupt Priority and Latency
Overall priorities and resolution Defaults INTR, NMI, and exceptionsInterrupt timing Latency Response time 80C188EB ICU specifics
82C59A PIC82C59A structure and capabilities Can be cascaded IBM PC used two of them to get 15 IRQ lines
Now usually part of chip setPrioritization schemes Fixed Rotating HierarchicalInterrupt Acknowledge Bus Cycles Run to get type number of interrupt source 82C59A handles placing data on the bus
Interrupt IssuesUsing periodic interrupts to perform iterative tasksWhat to do when good interrupts go bad… Software debugging Hardware debugging Real-time issues Inter-process communication (IPC)
issues
In-Class Assessment QuizWhat sort of safeguards might you need to design into NMI hardware?For the 80C188EB, describe what happens between an IRQ being asserted and the actual execution of the ISR.What are the differences between vectored interrupts and polled interrupts?
In-Class Assessment QuizWhat is a ‘level-sensitive’ interrupt?What problems can arise when using a semaphore to control access to a resource used by the main program and an ISR? What 80C188 instructions help handle this?Draw a flowchart for a periodic (1 KHz) ISR that will be used to generate precise delays. Only a single word variable is to be used to communicate with the ISR.
VectorTable
Interrupt Example - Hardware
IMASK
PRIMSK
REQST
INSERV
POLL
POLLSTS
EOI
INTSTS
REQST
TCUCON, SCUCON
I2CON,I3CON,I4CON
I0CON,I1CON
ICU Latency and Response Time
Default Interrupt PrioritiesInterrupt Name Priority LevelExceptions/NMI 1Timer 0 2aTimer 1 2bTimer 2 2cSerial Receive 3aSerial Transmit 3bINT4 4INT0 5INT1 6INT2 7INT3 8
Letters indicate relative priority within a level
ICU Block Diagram
INTABus Cycles