LAB PROJECT 1NAME: LAKSHMI YASASWI KAMIREDDYUIN: 651771619

Problem Description:The aim of the project is to design 16 bit adders using different adders and design styles and to understand how these parameters effect the gate count, propagation delay and the RTL view of the design. The components designed are a Full Adder (gate level), a RCA 16-bit adder, a 2’s compliment adder/subtractor (gate level and behavioral level) and a Linear Carry Select Adder.

Full Adder – Gate Level DesignThe functionality of a Full Adder is to calculate sum and carry when a sum of two input bits and a carry in is performed.

Truth Table:

Schematic:

RTL View:The RTL View shows that the Full adder design matches the Schematic.

Code:

16 bit RCA:

It is designed by connecting 16 full adders as shown in the schematic. A and B are 16 bit input vectors, Cin is the carry in, Sum is the 16 bit output vector and Cout is the carry out. This adder will have large delay because of its worst case path (shown in the schematic) going through all the full adders which will be 16*delay of FA.

Schematic:

Code:

Gate Level Description

Test Bench:

RTL View:

RTL Simulation Waveform:The waveform shows the functionality of the RCA.

Gate Level Simulation Waveform in slow model (with a sample delay):

Number of combinational functions:

Maximum propagation delay:

2’s compliment Adder/Subtractor:

Using the RCA built an adder/subtractor is designed as shown in the Schematic. An XOR is for the input B and Add/Sub bit because when subtraction has to be done 2’compliment needs to be calculated. The XOR with 1 gives the 1’s compliment and through Cin which is the add/sub input, a 1 is added with gives the 2’compliment result. Worst case delay will be delay of the RCA + 2*XOR delay. Schematic:

Code:

Test Bench:

RTL View:

RTL Simulation Waveform Unsigned:

To check if the B is negative and perform 2’s compliment

RTL Simulation Signed:

Gate Level Simulation Slow mode Unsigned:

Gate Level Simulation Slow mode signed:

Number of combinational functions:

Maximum Propagation Delay:

Adder/Subtractor Behavioral

In this case if the add/sub bit is 1 i.e, Cin=1 then we do X-Y else we do X+Y using behavioral statements.

Code:

Testbench

Behavioral statements

RTL View

RTL Simulation - Unsigned

RTL Simulation – Signed

Gate Level Simulation - Unsigned

Gate Level Simulation - Signed

Number of combinational functions:

Maximum Propagation delay:

Linear Carry Select Adder:Schematic:

Code:Carry select 4 bit

Note that the delay decreased when compared to the gate level model but the number of combinational functions increased.

Carry Select 16 bit

Test Bench:

Behavioral

Structural

RTL View:CSA 4 bit

CSA 16 bit

RTL Simulation

Gate Level Simulation

Number of Combinational functions:

Maximum Propagation Delay

Design Number of Combinational

Functions

Maximum Propagation delay

RCA 16 bit gate level 38 18.968Adder/Subtractor

RCA gate level33 23.185

Adder/Subtractor behavioral

34 14.642

Carry Select Adder 60 16.996

The table above shows that if an efficient gate level design can be done then we can reduce the number of combinational functions but a behavioral design is very efficient in reducing the delay. It can also be seen that CSA performs better in terms of delay but has a high number of combinational functions. Higher the number of combinational functional higher will be the number of gates in the circuit.

Propagation delay reduces as compared to RCA but the number of combinational functions almost doubles.

Both cases Delay decreases

Huge increase in number means CSA has very high area

Almost equal