ece 524 final project report

CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

FPGA/ASIC DESIGN(ECE 625)

PROJECT REPORT ON

UNIVERSAL ASYNCHRONOUS

RECEIVER/TRANSMITTER (UART)PROFESSOR: SHAHNAM MIRZAEI

BY

SAMEER PANDIT (104249481)

ABHIRUP JANNU (103501097)

NARENDRA VARMA UDDARAJU (104247505)

December 19, 2011 ECE 524 FINAL PROJECT REPORT

Table of Contents

PROJECT STATEMENT….…………………………………………………………………………..….5

FUNCTIONAL SPECIFICATION...............................................................................................................5

Introduction................................................................................................................................................5

Basic Concept............................................................................................................................................6

Serial Communication...............................................................................................................................7

Approach....................................................................................................................................................7

Oversampling Procedure............................................................................................................................8

Baud Rate Generator..................................................................................................................................8

Baud rate generator Simulation.....................................................................................................................9

UART Receiver.......................................................................................................................................10

UART TRANSMITTER..........................................................................................................................11

RTL SCHEMATIC..................................................................................................................................12

Transmitter...................................................................................................................................................12

Receiver.......................................................................................................................................................13

RTL SCHEMATIC OF TOP MODULE.................................................................................................14

SYNTHESIS REPORT AND TIMING ANALYSIS..............................................................................15

TESTING STRATEGY...........................................................................................................................22

RUNNING ON ACTUAL HARDWARE...............................................................................................22

Basic Steps...................................................................................................................................................22

California State University, Northridge | 2


HyperTerminal Setup...............................................................................................................................23

ANNEXURE A............................................................................................................................................26

RECEIVER..............................................................................................................................................26

TRANSMITTER......................................................................................................................................30

INTERFACE CIRCUIT – FIFO BUFFER..............................................................................................35

RECEIVER FIFO........................................................................................................................................35

TRANSMITTER FIFO................................................................................................................................40

BAUD GENERATOR.............................................................................................................................45

UART TOP MODULE............................................................................................................................46



FIGURES

FIGURE 1 : TRANSMISSION OF A BYTE...........................................................................................................6FIGURE 2: 9 BIT SERIAL COMMUNICATION.....................................................................................................7FIGURE 3: WAVEFORM SIMULATION OF BAUD RATE GENERATOR...............................................................9FIGURE 4: ASMD OF RECEIVER...................................................................................................................10FIGURE 5: TRANSMITTER STATE DIAGRAM.................................................................................................11FIGURE 6: RTL SCHEMATIC OF TRANSMITTER............................................................................................12FIGURE 7: DETAILED SCHEMATIC OF TRANSMITTER...................................................................................12FIGURE 8: RTL SCHEMATIC OF RECEIVER...................................................................................................13FIGURE 9: DETAILED SCHEMATIC OF RECEIVER..........................................................................................13FIGURE 10: RTL SCHEMATIC OF TOP MODULE...........................................................................................14FIGURE 11: DETAILED SCHEMATIC OF TOP MODULE..................................................................................14FIGURE 12: SYNTHESIS REPORT...................................................................................................................15FIGURE 13: OPENING A NEW CONNECTION IN HYPERTERMINAL.................................................................23FIGURE 14: CONNECTING TO THE SCREEN...................................................................................................23FIGURE 15: SETTINGS...................................................................................................................................24FIGURE 16: TRANSMITTER SETTINGS...........................................................................................................24Figure 17: Receiver Settings........................................................................................................................25



PROJECT STATEMENT

To develop a VHDL based Universal Asynchronous Receiver/Transmitter (UART), and demonstrate the working of both the receiver and the transmitter module by interfacing it with Microsoft Windows Hyper Terminal.

FUNCTIONAL SPECIFICATION

Introduction

UART is a device that is capable of both, receiving and transmitting serial data. It is a circuit that sends parallel data through a serial line. UARTs are frequently used in conjunction with the EIA (Electronic Industries Alliance) RS-232 standard, which specifies the electrical, mechanical, functional, and procedural characteristics of two data communication equipment. The Spartan 3E board basically handles the RS-232 standard and we only need to concentrate on the design of the UART circuit.

The transmitter is essentially a special shift register that loads data in parallel and then shifts it out bit by bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then reassembles the data. When it is idle, the serial line is always logic ‘1’. The transmission starts with a start bit, which is ‘0’, followed by the data bits and an optional parity bit and ends with a stop bit which is logic ‘1’.



Basic Concept

As discussed, UART transmitter controls transmission by fetching a data word in parallel format and directing the UART to transmit it in a serial format. Likewise, the Receiver must detect transmission, receive the data in serial format, strip of the start and stop bits, and store the data word in a parallel format.

The number of data bits can be 6, 7, or 8. The optional parity bit is used for error detection. For odd parity, it is set to ’0’ when the data bits have an odd number of 1’s. For even parity, it is set to ’0’ when the data bits have an even number of 1’s. The number of stop bits can be 1, 1.5, or 2.

No clock information is conveyed through the serial line. Before the transmission starts, the transmitter and receiver must agree on a set of parameters in advance, which include the baud rate (i.e., number of bits per second), the number of data bits and stop bits, and use of the parity bit. The commonly used baud rates are 2400, 4800, 9600 and 19,200 bauds. The design is customized for a UART with a 19,200 baud rate, 8 data bits, 1 stop bit, and no parity bit.

Figure 1 : Transmission of a byte



Serial Communication

Serial Port used for UART is RS-232. It is a nine pin connector with each pin assigned

with different functionality.

Figure 2: 9 bit serial communication



Approach

We approached the given problem statement by implementing the receiver and the transmitter independently. We started with the receiver as it is more complex and difficult to implement. However, for starting with the receiver or the transmitter, we also needed implement a baud rate generator. Since no clock information is conveyed from the transmitted signal, the receiver can retrieve the data bits only by using the predetermined parameters. We use an oversampling scheme to estimate the middle points of transmitted bits and then retrieve them at these points accordingly.

Oversampling Procedure

The most commonly used sampling rate is 16 times the baud rate, which means that each serial bit is sampled 16 times. Assume that the communication uses N data bits and M stop bits. The oversampling scheme works as follows:

1. Wait until the incoming signal becomes 'O', the beginning of the start bit, and then start the sampling tick counter.

2. When the counter reaches 7, the incoming signal reaches the middle point of the start bit. Clear the counter to 0 and restart.

3. When the counter reaches 15, the incoming signal progresses for one bit and reaches the middle of the first data bit. Retrieve its value, shift it into a register, and restart the counter.

4. Repeat step 3 N-1 more times to retrieve the remaining data bits.5. If the optional parity bit is used, repeat step 3 one time to obtain the parity bit.6. Repeat step 3 M more times to obtain the stop bits.

The oversampling scheme basically performs the function of a clock signal. Instead of using the rising edge to indicate when the input signal is valid, it utilizes sampling ticks to estimate the middle point of each bit. While the receiver has no information about the exact onset time of the start bit, the estimation can be off by at most 1/16. The subsequent data bit retrievals are off by at most 1/16 from the middle point as well. Because of the oversampling, the baud rate can only be a small fraction of the system clock rate, and thus this scheme is not appropriate for a high data rate.



Baud Rate Generator

The baud rate generator generates a sampling signal whose frequency is exactly 16 times the UART’s designated baud rate. To avoid creating a new clock domain and violating the synchronous design principle, the sampling signal should function as enable ticks rather than the clock signal to the UART receiver.

For the 19,200 baud rate, the sampling rate has to be 307,200 (i.e., 19,200*16) ticks per second. Since the system clock rate is 50 MHz, the baud rate generator needs a mod-163 (50*10^6/307200) counter, in which the one-clock-cycle tick is asserted once every 163 clock cycles.

Baud rate generator Simulation

Figure 3: Waveform Simulation of Baud Rate Generator



UART Receiver



Figure 4: ASMD of Receiver



UART TRANSMITTER

Figure 5: Transmitter State Diagram



RTL SCHEMATIC

Transmitter

Figure 6: RTL Schematic of Transmitter

Figure 7: Detailed Schematic of Transmitter



Receiver

Figure 8: RTL Schematic of Receiver



Figure 9: Detailed schematic of Receiver

RTL SCHEMATIC OF TOP MODULE

Figure 10: RTL Schematic of Top Module



Figure 11: Detailed Schematic of Top Module

SYNTHESIS REPORT AND TIMING ANALYSIS

Figure 12: Synthesis Report

* Synthesis Options Summary *

---- Source ParametersInput File Name : "uart_test.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "uart_test"Output Format : NGC



Target Device : xc3s500e-5-fg320---- Source OptionsTop Module Name : uart_testAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YESResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 24Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : autoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Library Search Order : uart_test.lsoKeep Hierarchy : NONetlist Hierarchy : as_optimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100



Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5---- Other OptionsCores Search Directories : {"ipcore_dir" }

* HDL Synthesis *

Performing bidirectional port resolution...Synthesizing Unit <debounce>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/debounce_uart.vhd". Found finite state machine <FSM_0> for signal <state_reg>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 10 | | Inputs | 2 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | zero | | Power Up State | zero | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 21-bit subtractor for signal <q_next$addsub0000> created at line 62. Found 21-bit register for signal <q_reg>. Summary:

inferred 1 Finite State Machine(s).inferred 21 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).

Unit <debounce> synthesized.Synthesizing Unit <baud_gen>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/baud_gen.vhd". Found 8-bit adder for signal <r_next$addsub0000> created at line 30. Found 8-bit register for signal <r_reg>. Summary:

inferred 8 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).

Unit <baud_gen> synthesized.Synthesizing Unit <uart_rx>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/uart_rx.vhd". Found finite state machine <FSM_1> for signal <state_reg>.



----------------------------------------------------------------------- | States | 4 | | Transitions | 12 | | Inputs | 5 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal <b_reg>. Found 3-bit register for signal <n_reg>. Found 3-bit adder for signal <n_reg$addsub0000> created at line 83. Found 4-bit register for signal <s_reg>. Found 4-bit adder for signal <s_reg$share0000> created at line 56. Summary:


Unit <uart_rx> synthesized.Synthesizing Unit <fifo>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/fifo_buffer.vhd". Found 8-bit 4-to-1 multiplexer for signal <r_data>. Found 32-bit register for signal <array_reg>. Found 1-bit register for signal <empty_reg>. Found 2-bit comparator equal for signal <empty_reg$cmp_eq0000> created at line 97. Found 1-bit 4-to-1 multiplexer for signal <empty_reg$mux0000> created at line 91. Found 1-bit register for signal <full_reg>. Found 2-bit comparator equal for signal <full_reg$cmp_eq0000> created at line 105. Found 1-bit 4-to-1 multiplexer for signal <full_reg$mux0000> created at line 91. Found 2-bit register for signal <r_ptr_reg>. Found 2-bit 4-to-1 multiplexer for signal <r_ptr_reg$mux0000> created at line 91. Found 2-bit adder for signal <r_ptr_succ$add0000> created at line 78. Found 2-bit register for signal <w_ptr_reg>. Found 2-bit 4-to-1 multiplexer for signal <w_ptr_reg$mux0000> created at line 91. Found 2-bit adder for signal <w_ptr_succ$add0000> created at line 77. Summary:

inferred 38 D-type flip-flop(s).inferred 2 Adder/Subtractor(s).inferred 2 Comparator(s).



inferred 14 Multiplexer(s).Unit <fifo> synthesized.Synthesizing Unit <uart_tx>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/uart_tx.vhd". Found finite state machine <FSM_2> for signal <state_reg>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 12 | | Inputs | 4 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal <b_reg>. Found 3-bit register for signal <n_reg>. Found 3-bit adder for signal <n_reg$addsub0000> created at line 93. Found 4-bit adder for signal <s_next$add0000> created at line 80. Found 4-bit register for signal <s_reg>. Found 1-bit register for signal <tx_reg>. Summary:


Unit <uart_tx> synthesized.Synthesizing Unit <uart>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/top.vhd".Unit <uart> synthesized.Synthesizing Unit <uart_test>. Related source file is "C:/Users/Sameer/Desktop/524 Project/uart/uart_test.vhd".WARNING:Xst:647 - Input <btn<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:646 - Signal <tx_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 8-bit adder for signal <rec_data1>. Summary:

inferred 1 Adder/Subtractor(s).Unit <uart_test> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for


warning:Xst:646%20-%20Signal%20%3Crx_empty%3E%20is%20assigned%20but%20never%20used.%20This%20unconnected%20signal%20will%20be%20trimmed%20during%20the%20optimization%20process.?&DataKey=SolutionRecord

warning:Xst:646%20-%20Signal%20%3Ctx_full%3E%20is%20assigned%20but%20never%20used.%20This%20unconnected%20signal%20will%20be%20trimmed%20during%20the%20optimization%20process.?&DataKey=SolutionRecord

warning:Xst:647%20-%20Input%20%3Cbtn%3C2:1%3E%3E%20is%20never%20used.%20This%20port%20will%20be%20preserved%20and%20left%20unconnected%20if%20it%20belongs%20to%20a%20top-level%20block%20or%20it%20belongs%20to%20a%20sub-block%20and%20the%20hierarchy%20of%20this%20sub-block%20is%20preserved.?&DataKey=SolutionRecord


reduced device utilization. For improved clock frequency you may try to disable resource sharing.HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 11 2-bit adder : 4 21-bit subtractor : 1 3-bit adder : 2 4-bit adder : 2 8-bit adder : 2# Registers : 25 1-bit register : 5 2-bit register : 4 21-bit register : 1 3-bit register : 2 4-bit register : 2 8-bit register : 11# Comparators : 4 2-bit comparator equal : 4# Multiplexers : 10 1-bit 4-to-1 multiplexer : 4 2-bit 4-to-1 multiplexer : 4 8-bit 4-to-1 multiplexer : 2

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information:-----------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 143 |-----------------------------------+------------------------+-------+



Asynchronous Control Signals Information:---------------------------------------------------------------------------+------------------------+-------+Control Signal | Buffer(FF name) | Load |-----------------------------------+------------------------+-------+rst | IBUF | 143 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 9.165ns (Maximum Frequency: 109.116MHz) Minimum input arrival time before clock: 9.416ns Maximum output required time after clock: 6.230ns Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)

* Final Report *Final ResultsRTL Top Level Output File Name : uart_test.ngrTop Level Output File Name : uart_testOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 15Cell Usage :# BELS : 339# GND : 1# INV : 21# LUT1 : 1# LUT2 : 14# LUT2_D : 1# LUT2_L : 2# LUT3 : 65# LUT3_D : 2# LUT3_L : 3# LUT4 : 127# LUT4_D : 11# LUT4_L : 10# MUXCY : 26# MUXF5 : 33# VCC : 1# XORCY : 21# FlipFlops/Latches : 143# FDC : 68# FDCE : 72



# FDP : 3# Clock Buffers : 1# BUFGP : 1# IO Buffers : 12# IBUF : 3# OBUF : 9

TESTING STRATEGY

We use a loop-back circuit and a PC to verify the UART’s operation. The serial port of the Spartan 3E board is connected to the serial port of a PC. When we send a character from the PC, the received data word is stored in the UART receiver’s four-word FIFO buffer. When retrieved (via the r-data port), the data word is incremented by 1 and then sent back to the transmitter (via



the w-data port). The debounce pushbutton switch produces a single one-clock-cycle tick when pressed and it is connected to the rd-uart and wr-uart signals. When the tick is generated, it removes one word from the receiver’s FIFO and writes the incremented word to the transmitter’s FIFO for transmission. For example, we can first type SAM in the PC and the three data words are stored in the FIFO buffer of the UART receiver. We then can push the button on the Spartan 3E board three times. The three successive characters, TBN, will be transmitted back and displayed.

RUNNING ON ACTUAL HARDWARE

Basic Steps

In Xilinx click on Generate Programming File and then when it is complete click on Configure device (iMPACT).

Then program the chip using this utility and on successful completion we will get an alert.

Now we are ready to use it on hardware. We then have to configure the HyperTerminal as explained in next section. Now for receiver code if we type something on HyperTerminal, the value will be

reflected on LEDs and in transmitter anything given from switches will be displayed on HyperTerminal.

For transmitter first we select from two switches what we want to send. Then we reset, followed by load followed by shift. The character chosen will be then displayed on HyperTerminal.

For receiver first we need to put on the enable switch and then anything typed on HyperTerminal will be displayed on LEDs.



HyperTerminal Setup

Figure 13: Opening a new connection in HyperTerminal

Figure 14: Connecting to the screen



Figure 15: Settings



Figure 16: Transmitter Settings



Figure 17: Receiver Settings



ANNEXURE A

RECEIVER

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity uart_rx is

generic(

Data_bit : integer := 8 ;

SB_TICK: integer := 16

);

port(

clk ,rst : in std_logic ;

rx : in std_logic ;

s_tick : in std_logic ;

rx_done_tick : out std_logic ;

dout : out std_logic_vector(7 downto 0)

) ;

end uart_rx ;



architecture arch of uart_rx is

type state_type is ( idle, start, data, stop ) ;

signal s_reg , s_next : unsigned (3 downto 0) ;

signal n_reg , n_next : unsigned (2 downto 0) ;

signal b_reg , b_next : std_logic_vector (7 downto 0) ;

signal state_reg, state_next : state_type ;

begin

process (clk, rst)

begin

if (rst = '1') then

state_reg <= idle ;

s_reg <= (others => '0') ;

n_reg <= (others => '0') ;

b_reg <= (others => '0') ;

elsif (clk' event and clk = '1') then

state_reg <= state_next ;

s_reg <= s_next ;

n_reg <= n_next ;

b_reg <= b_next ;



end if ;

end process ;

process (state_reg, s_reg, n_reg, b_reg, s_tick, rx)

begin

state_next <= state_reg ;

s_next <= s_reg ;

n_next <= n_reg ;

b_next <= b_reg ;

rx_done_tick <= '0' ;

case state_reg is

when idle =>

if rx = '0' then

state_next <= start ;

s_next <= (others => '0') ;

end if ;

when start =>

if (s_tick = '1') then

if (s_reg = 7) then

state_next <= data ;


n_next <= (others => '0') ;



else

s_next <= s_reg + 1 ;

end if ;

end if ;

when data =>


if (s_reg = 15) then


b_next <= rx & b_reg (7 downto 1) ;

if n_reg = (Data_bit -1) then

state_next <= stop ;

else

n_next <= n_reg+1 ;

end if ;

else

s_next <= s_reg + 1;

end if ;

end if ;

when stop =>


if s_reg = (SB_TICK-1) then

state_next <= idle ;

rx_done_tick <= '1' ;



else


end if ;

end if ;

end case ;

end process ;

dout <= b_reg ;

end arch ;

TRANSMITTER

library ieee;


use ieee.numeric_std.all ;

entity uart_tx is

generic (

Data_bit : integer := 8 ;

SB_TICK: integer:= 16

) ;



port (

clk, rst: in std_logic;

tx_start : in std_logic;

s_tick: in std_logic;

din: in std_logic_vector (7 downto 0);

tx_done_tick: out std_logic;

tx: out std_logic

) ;

end uart_tx ;

architecture arch of uart_tx is

type state_type is (idle, start, data, stop);

signal state_reg, state_next : state_type;

signal s_reg , s_next : unsigned (3 downto 0) ;

signal n_reg , n_next : unsigned (2 downto 0) ;

signal b_reg , b_next : std_logic_vector (7 downto 0) ;

signal tx_reg , tx_next : std_logic ;

-- FSMD state C? data registers

begin

process (clk, rst)

begin

if rst= '1' then

state_reg <= idle;



s_reg <= (others => '0' ) ;

n_reg <= (others => '0' ) ;

b_reg <= (others => '0' ) ;

tx_reg <= '1';

elsif (clk' event and clk = '1' ) then

state_reg <= state_next;

s_reg <= s_next;

n_reg <= n_next;

b_reg <= b_next;

tx_reg <= tx_next;

end if ;

end process ;

process (state_reg, s_reg, n_reg, b_reg, s_tick, tx_reg, tx_start, din)

begin

state_next <= state_reg;

s_next <= s_reg;

n_next <= n_reg;

b_next <= b_reg;

tx_next <= tx_reg;

tx_done_tick <= '0';



case state_reg is

when idle =>

tx_next <= '1' ;

if tx_start = '1' then

state_next <= start ;

s_next <= ( others => '0' ) ;

b_next <= din ;

end if ;

when start =>

tx_next <= '0' ;


if s_reg = 15 then

state_next <= data ;


n_next <= (others => '0') ;

else


end if ;

end if ;

when data =>

tx_next <= b_reg(0) ;




if s_reg = 15 then


b_next <= '0' & b_reg (7 downto 1) ;

if n_reg = (Data_bit - 1) then

state_next <= stop ;

else

n_next <= n_reg + 1 ;

end if ;

else


end if ;

end if ;

when stop =>

tx_next <= '1' ;


if s_reg = (SB_TICK -1) then

state_next <= idle ;

tx_done_tick <= '1';

else


end if ;

end if ;

end case ;



end process ;

tx <= tx_reg ;

end arch ;

INTERFACE CIRCUIT – FIFO BUFFER

RECEIVER FIFO

library ieee;



entity fifo is

generic(

B: natural:= 8; -- number of bits

W: natural:= 4 -- number of address bits

) ;



port(

clk, rst : in std_logic;

rd, wr: in std_logic;

w_data: in std_logic_vector (B-1 downto 0) ;

empty, full : out std_logic;

r_data: out std_logic_vector (B-1 downto 0)

);

end fifo;

architecture arch of fifo is

type reg_file_type is array (2**W-1 downto 0) of std_logic_vector (B-1 downto 0) ;

signal array_reg : reg_file_type ;

signal w_ptr_reg, w_ptr_next, w_ptr_succ : std_logic_vector (W-1 downto 0) ;

signal r_ptr_reg, r_ptr_next, r_ptr_succ : std_logic_vector (W-1 downto 0) ;

signal full_reg, empty_reg, full_next, empty_next : std_logic;

signal wr_op: std_logic_vector(1 downto 0) ;

signal wr_en : std_logic ;

begin

--=====================

--Register File



--=====================

process (clk, rst)

begin

if (rst = '1') then

array_reg <= (others => (others => '0'));

elsif (clk' event and clk='1') then

if wr_en='1' then

array_reg(to_integer(unsigned(w_ptr_reg))) <= w_data;

end if;

end if;

end process;

-- read port

r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));

-- write enabled only when FIFO is not full

wr_en <= wr and (not full_reg);

--===================

--FIFO Control Logic

--===================

--register for read and write pointers

process (clk, rst)

begin

if (rst='1') then



w_ptr_reg <= (others => '0');

r_ptr_reg <= (others => '0');

full_reg <= '0';

empty_reg <= '1';


w_ptr_reg <= w_ptr_next ;

r_ptr_reg <= r_ptr_next ;

full_reg <= full_next;

empty_reg <= empty_next ;

end if;

end process ;

--===========================

-- Successive pointer Values

--===========================

w_ptr_succ <= std_logic_vector (unsigned(w_ptr_reg)+1);

r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);

--=============================================

--Next state logic for read and write pointers

--=============================================

wr_op <= wr & rd;

process (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg)



begin

w_ptr_next <= w_ptr_reg;

r_ptr_next <= r_ptr_reg;

full_next <= full_reg;

empty_next <= empty_reg;

case wr_op is

when "00" => -- no op

when "01" => -- read

if (empty_reg /= '1') then -- not empty

r_ptr_next <= r_ptr_succ;

full_next <= '0';

if (r_ptr_succ = w_ptr_reg) then

empty_next <= '1';

end if ;

end if ;

when "10" => -- write

if (full_reg /= '1') then -- not full

w_ptr_next <= w_ptr_succ;

empty_next <= '0';

if (w_ptr_succ = r_ptr_reg) then

full_next <= '1';

end if ;

end if ;

when others => -- write/read ;

w_ptr_next <= w_ptr_succ ;



r_ptr_next <= r_ptr_succ ;

end case ;

end process ;

--=========

--Output

--=========

full <= full_reg;

empty <= empty_reg;

end arch;

TRANSMITTER FIFO

library ieee;



entity fifo is

generic(



B: natural:= 8; -- number of bits

W: natural:= 4 -- number of address bits

) ;

port(


rd, wr: in std_logic;

w_data: in std_logic_vector (B-1 downto 0) ;

empty, full : out std_logic;

r_data: out std_logic_vector (B-1 downto 0)

);

end fifo;

architecture arch of fifo is

type reg_file_type is array (2**W-1 downto 0) of std_logic_vector (B-1 downto 0) ;

signal array_reg : reg_file_type ;

signal w_ptr_reg, w_ptr_next, w_ptr_succ : std_logic_vector (W-1 downto 0) ;

signal r_ptr_reg, r_ptr_next, r_ptr_succ : std_logic_vector (W-1 downto 0) ;

signal full_reg, empty_reg, full_next, empty_next : std_logic;

signal wr_op: std_logic_vector(1 downto 0) ;

signal wr_en : std_logic ;

begin



--=====================

--Register File

--=====================

process (clk, rst)

begin

if (rst = '1') then

array_reg <= (others => (others => '0'));


if wr_en='1' then

array_reg(to_integer(unsigned(w_ptr_reg))) <= w_data;

end if;

end if;

end process;

-- read port

r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));

-- write enabled only when FIFO is not full

wr_en <= wr and (not full_reg);

--===================

--FIFO Control Logic

--===================

--register for read and write pointers



process (clk, rst)

begin

if (rst='1') then

w_ptr_reg <= (others => '0');

r_ptr_reg <= (others => '0');

full_reg <= '0';

empty_reg <= '1';


w_ptr_reg <= w_ptr_next ;

r_ptr_reg <= r_ptr_next ;

full_reg <= full_next;

empty_reg <= empty_next ;

end if;

end process ;

--===========================

-- Successive pointer Values

--===========================

w_ptr_succ <= std_logic_vector (unsigned(w_ptr_reg)+1);

r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);

--=============================================

--Next state logic for read and write pointers

--=============================================



wr_op <= wr & rd;

process (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg)

begin

w_ptr_next <= w_ptr_reg;

r_ptr_next <= r_ptr_reg;

full_next <= full_reg;

empty_next <= empty_reg;

case wr_op is

when "00" => -- no op

when "01" => -- read

if (empty_reg /= '1') then -- not empty

r_ptr_next <= r_ptr_succ;

full_next <= '0';

if (r_ptr_succ = w_ptr_reg) then

empty_next <= '1';

end if ;

end if ;

when "10" => -- write

if (full_reg /= '1') then -- not full

w_ptr_next <= w_ptr_succ;

empty_next <= '0';

if (w_ptr_succ = r_ptr_reg) then

full_next <= '1';

end if ;



end if ;

when others => -- write/read ;

w_ptr_next <= w_ptr_succ ;

r_ptr_next <= r_ptr_succ ;

end case ;

end process ;

--=========

--Output

--=========

full <= full_reg;

empty <= empty_reg;

end arch;

BAUD GENERATOR

library ieee;




use ieee.numeric_std.all ;

entity baud_gen is

generic (

N : integer := 8; -- log 163/log2

M : integer := 163 -- mod 163 counter

);

port(

clk, rst: in std_logic;

baud_tick: out std_logic;

count: out std_logic_vector (N-1 downto 0)

);

end baud_gen ;

architecture arch of baud_gen is

signal r_reg, r_next : unsigned (N-1 downto 0) ;

begin

process (clk, rst)

begin

if (rst='1') then

r_reg <= (others => '0');


r_reg <= r_next;

end if ;



end process;

r_next <= (others => '0') when r_reg = (M-1) else r_reg + 1;

count <= std_logic_vector(r_reg);

baud_tick <= '1' when r_reg = (M-1) else '0';

end arch;

UART TOP MODULE

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 02:00:28 12/11/2011

-- Design Name:

-- Module Name: uart_test - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:



-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;


-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity uart_test is

port(


btn : std_logic_vector(2 downto 0);

rx : in std_logic;

tx : out std_logic;



led : out std_logic_vector(7 downto 0)

);

end uart_test;

architecture arch of uart_test is

signal tx_full, rx_empty : std_logic;

signal rec_data, rec_data1: std_logic_vector (7 downto 0);

signal btn_tick : std_logic;

begin

uart_unit : entity work.uart(top)

port map(clk=>clk, rst=>rst, rd_uart=>btn_tick, wr_uart=>btn_tick, rx=>rx, w_data=>rec_data1,

tx_full=>tx_full, rx_empty=>rx_empty, r_data=>rec_data, tx=>tx);

btn_db_unit : entity work.debounce(fsmd_arch)

port map(clk=>clk,rst=>rst,sw=>btn(0),

db_level=>open, db_tick=>btn_tick);

rec_data1 <= std_logic_vector(unsigned(rec_data)+1);



led<=rec_data;

end arch;


ece 524 final project report

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