ECE 7366 Advanced Process Integration

High k Dielectrics, HK/MG, Channel Engineering

Dr. Wanda Wosik

Text Book: B. El-Karek, “Silicon Devices and Process Integration”, Chapter 71

2

Gate Stack

Gate dielectrics in MOSFETs:

•SiO2

•High K with interfacial SiO2 on Si channels

• High K with interfacial SiO2 Si channels

• High K with interfacial SiO2 on GeSi and Ge channels

•High K without interfacial SiO2 on GeSi and Ge channels

Gate Electrodes in MOSFETs: •metal gate Al – not self aligned•polysilicon n+ type• dual poly-gates• silicides poly-gates• fully silicidedpoly-gates• metal gates – midgap• metal gates – dual

Result in:

lower gate oxide leakage

lower switching power

higher drive current

lower source-drain leakage

Intel

3Iwai, 2009

4

Gate Stack ModuleGate-stack transition from polysilicides=silicided doped poly-Si on SiO2 to metal gates on high-K dielectric

Gates scaling movie

•Poly-Si depletion ~1.2 nm CET by ~ 0.4 nm•Poly-Si leaks B to the channel (dielectric and Si)

CET=Capacitance equivalent thickness

Material requirements:• K≈10 to 30 (too large fringe fields @D)• Large band gap >5eV• Large conduction and valence band offsets

(thermionicSchottky) • Interface quality and preparation• Low density of interface traps Dit<1011cm-

1eV-1 charges; Qit would cause m Fermi level pinning problems with

section fms

• Thermodynamic stability (no reaction with poly-Si, metal and/or oxygen diffusion)

• Deposition of high k dielectrics on SiO2 partly solve the interface problems

5

Ultrathin Oxide (K=3.9) and High-K Dielectric

Ultrathin oxide ~ 4nm allows for VG=2.4 V (Eoxmax=6x106V/cm)

Direct tunneling with decreasing oxide thickness

Maintain long channel operation: Leff/xox≅ 45

Ex. for Leff ≅70 nm xox≅ 1.5 nm IG~10A/cm2 huge standby power.

Use high K dielectric to obtain teq=2nm: K=5 2x(5/3.9)=2.56 nmK=18 2x(28/3.9)=9.2 nm

Gate leakage and power dissipation for 1.5 nm SiO2 and high K dielectric of teq=1.5nm

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High-K RequirementsTeq ≤1nm for low gate leakage

*

*

Hsing-Huang Tseng

Gate processing: compatibility with S/D high T

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High K Materials

Oxynitrides K~4-7 (composition, thickness, deposition conditions) ex. RNO (in RTA) 18.-2.8 nm K>5.7 – reduction of interfacial charges by reoxidation

Hafnium Based Dielectrics (FIRST CHOICE): Eg~6.0eV, HfO2, HfSiON, HfSiO charges, roughness mobility degradation below 80% use thin interfacial oxide SiO2 IFO (ox) watch for overall K

Fabrication: reactive co-sputtering (Hf and/or Si in Ar+O2+N2), CVD, ALD. Interface important! IFO: RTO, plasma, in-situ steam generation - 0.6nm

Other High-K Materials: Al203 (K~10-11 – too low), HfO2-Al2O3, ZrO2, TiO2 (50), La2O3, Ta2O5 (K~25, low offset, can be crystalline on Ru electrode-integration?), BST (BaxSry)TiO3 K>100 for Gbit DRAMs (not at high T but @ end of processing – very good for DRAMS stacked capacitors)

K=3.9 7.5 25 25 26 10

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Limitation of k Values Due to lateral E-field

SS decreases

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Hf based also: • Nitrided HfSiOx

• (HfO2)x(SiO2)1-x

High k Dielectrics - Choices

Hauser, IEDM 1999Hubbard and Schlom, 1996

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Selection of High k Dielectrics

Requirements:• Band gap and Energy band offsets• Thermal stability to avoid:

• crystallization • interfacial reactions with Si, SiO2, silicides during

deposition and thermal annealing etc.• diffusion of oxygenformation of increased IL

• Match with SiO2 as interlayer (dipoles)• Good interface with Si to eliminate the need of IL SiO2

• Future similar properties and compatibility with high mobility material channels

Unstable oxides: TiO2, Ta2O5, BST Use barrier layers (Si3N4)– complications in fabrication and device operation (add to dielectric thickness) Stable oxides: HfO2, ZrO2, Al2O3 and their silicates (HfSixOy), oxynitrides (HfSixNyOz) and aluminates (e.g. HfAlxOy)

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T.P.Ma, Plenary talk 2008

Similar interaction may occur at the Metal Gate side.

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Roughness

High k Dielectrics on Si

Add interfacial layer (IL) oxide to:• improve the roughness • improve mobility and decrease

charge trapping• Interfacial dipoles still present

Mobility apparently decreases due to• charge trapping at the Si/dielectric

interface• coulombic scattering due to

trapped charges

TEM cross section shows recrystallized HfO2 and rough interfaces with IL oxide and with Poly-Si gate

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He et al, 2011

The interface dipole formation for (a) O-deficient interface and (b) O-rich interface.

Charges and Dipoles at the Interfaces of HK/MG and HK/Substrate

At high-k/metal interface

At high-k/substrate interface

Pt gate on HfO2 dielectric – possible mechanism

Dipole formation changes the work function EWF

Oxygen vacancies are + charged• Introducing oxygen back to HK

(annealing) shifts VFB (EWF) w/o IL increase

Kawanago, PhD, 2011

Better surface

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Dipole formation @SiO2 depends on material used since oxygen density is different EWF VFB varies

Oxide at the substrate/HK interface: Deposition and/or Reaction

Dipoles and charges EWF changes VFB VT shift

Oxygen vacancies will cause VT roll-off

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Niwa, 110622 SMT Symp.

Possible Oxygen Behavior in HK/MG with IL

Results in strong VT roll –off with decreasing EOT

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Dipole Signs May Depend on Poly-Si Doping

Dipole sign may depend on metallic ions work function changes (EWF)

Tseng, 2010

Housssa et al., 2006

n+ poly-Sigate

p+ poly-Sigate

Barrier height fB for electron injection from poly-Si changes with thicker HfO2 layer and VTH changes (band offsets)

As in PMOS with Al in Metal Aluminum Nitride (MAIN) gate

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Capping layers with RE dopants deposited on HfSiON by MBE or PVD result in dipoles determined by • ionic radius (+Q) at HK/SiO2 IL• electronegativity difference b/w O

and RE Large shifts in EWF shift Vt values

Capping Layers Can Be Used To Control The VFB And VT Shifts

Tseng et al., 2009

RE Capping layers

Stress at the SiO2/Si interface increases this effects – use Stress Relieve Pre-Oxide (SRPO)

Iwai, IEEE, 2011 18

Scaling of Dielectrics

Very challenging

Tests for HK on poly-Si gates later application for metal gates (HK/MG)

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Interlayer Between Channel and High k

Nara, Selete

Interfacial Layer (IL) formation due to deposition (ALD=chemical oxide, PVD etc) and annealing

Presence of IL oxide decreases overall ETO:

7nm HfO2+1nmSiO2=EOT~2nm

8nm HfO2=EOT~1.25nm

Southwick & Knowlton, 2006

End of planar transistors

Scaling continues SOI

Scaling continues; 3D; Si substrate or SOI

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Iwai, 2011

Recrystalliza-tion

EOT Very Thin < 1nm for Scaled Down Devices: Planar, FD SOI, and MG

Thermal Stability and Composition of HK

• Recrystallization of HfO2 ~ 400°C-450 °̧�

• Addition of SiO2 or N increases recrystallization temperatures (k decreases)

He et al, 2011

XRD spectra for the HfO2 and HfOxNy films

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as deposited annealed: 1050°C, 20s

Addition of Si to HfO2 improves the stability

HfxSiOy

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Other modifications of HfO2: addition of Al & Al-O-N increase T of recrystallization and • keeps the dielectric amorphous • k decreases• work function and band offsets change also• charges may be formed and mobility can degrade.

Huang et al, ISBN 978-953-307-086-5,

Thermal Stability and Composition of HK

XRD

This has the best stability i.e. remains amorphousSmaller gate currents, no hysteresis, less traps

Note: IL formationYamoto et al., APL, 2006

Joo, M.S. et al, IEEE, 2003

Adding most stable high k dielectric to HfO2 increases recrystallization even further and maintain high k (>20) HfLaOx. Ex. HfTaO, at 40% of Ta in Ta in HfTaO stability improves from 400°C to ~900°C. k≈17. Less charge trapping!Another promising HK dielectric: La2O3 and stacks with HfO2 etc.

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N2 slows> • Oxidation - tox will not increase• Desorption at the surface• Diffusion though the HfSiON

N2 at the Interface

N incorporation affects mobility for holes mh and for electrons me

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700°C annealing in N2

Interlayer oxide formation during annealing

La2O3 can create direct contact with Si

IL causes decrease of k values i.e. increase of EOT

Lu et al. 2006

Iwai IEEE, 2011,

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IL oxide important in EOT:

7nm HfO2+1nmSiO2=EOT~2nm

8nm HfO2=EOT~1.25nm

Southwick & Knowlton, 2006

Metal gate thickness can be important in IL formation under HKAnd mobility degradation recovery

HK Dielectric La2O3 and MG with no IL

Iwai IEEE, 2011,

Kawanago, PhD 2011

Note: for SiO2 there is no influence – no oxygen vacancies unlike in HK

Smaller IL thickness for thicker W

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High k Dielectrics Affect VT

La2O3 results in the negative shift of VT – EWF decreases

fMS only

Oxygen and/or FG annealing results in compensation of + charges VFB shift

HK/Si interface changes the VFB not the top interface (no pining at HfO2/W?)

VFB stable for top interface VFB - bottom interface

Kalanago, 2011

w/o F-level pinning metal WF controls the VFB

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Iwai IEEE, 2011,

Masking Layer Stacks Used in The Gates Suppress IL Formation

• Metal work function for the VT control is determined by the W gate layer.

• Efficiency of masking by TiN and next by Si is seen in Cox and larger gate leakage in subthreshold regime (thinner oxide).

• TiN barrier efficiency (oxygen diffusion) decreases with thickness – VFB shifts to the right but no IL formation=same capacitance (low T and/or silicate at HK/Si)

• FG annealing only (high T – interface traps removal, bonding) shifts VFB left

• Mobility improves by oxygen annealing (less oxygen vacancies)

TiN is a barrier against W silicidation

Kawanago, 2011

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Mobility Degradation by HK

Metal gates improve mobility by reducing surface phonon scattering

In HK dielectrics1) trapped charges cause carrier loss and mobility underestimation2) surface traps increase scattering mCoul

Chau, 2004

Ma, 2008

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Effective mobility for metal-gated HfO2 devices as a function of the interfacial oxide thickness. Houssa

Fixed charges in HK lead to mobility degradationOxygen vacancies in HK (+ charged) have to be controlled

• annealing for oxygen incorporation• capping layers (VFB shift to the right

~increased EWF)• increase of IL SiO2 (smaller k)

Carrier Mobility Degradation by HK

• Stack HK layers may decrease mobility• Annealing in oxygen and FG (N2+H2) recovers mobility (H

bonding)• Surface phonon scattering is mainly responsible for

mobility degradation in HK materials

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Extra slide

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SiO2/HfO2 stack: (1) the direct tunneling current and (2) the trap-assisted current through defects in the HfO2.

Houssa, 2006

Weir et al. 2000

Robertson, 2004

Gate Leakage Current

4-5 orders of magnitude smaller leakage currents due to HK/MG designs

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Mobility Enhancement

Mean free path between collisions, tIn high fields carriers loose energy to the lattice – optical phonons

To increase velocity (low & high field) reduce effective mass of carriers.

Low temperature operation

Cryogenic electronics – difficult, expensive important in some applications

Use strain engineering in planar transistors to increase carrier mobility in Si. Next, incorporate Ge and other high mobility materials.

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HK/MG cannot deliver as high mobility values as in SiO2

structures. For planar transistor designs uniaxial stress can be used.

R. Arghavani, IEDM 2007

Mobility in HK/MG Structures

• Using strain can enhance mobility of electrons and holes through energy structure changes at C and V bands.

• Also, High mobility materials can be used for channels.

HK /Poly-Si lead to low mobilityRecovery of mobility by • metal gate due to screening the

phonons• Silicate• strained Si substrate

H. Wong et al., 2009

Deleonibus et al., 2009

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Wong, 1994

High m materials may cause unwanted effects: Small Eg larger leakage currents (G-R in DL layers, BTBT)

larger diffusion current S/DSmall m* larger tunneling currents, also b/w S/DHigh k subthreshold slope increase

High Mobility Channels

Low m* • Backscattering will decrease • injection velocity from the source will

increase

H. Wong, Nano-CMOS Dielectric Eng., 2012

Ge the best candidate now• More symmetric and higher carrier motilities (mp the highest)• Easier integration on Si• Lower temperature processing

Material Property

Si Ge GaAs InAs InSb

Electron mobility 1600 3900 9200 40000 77000

Hole mobility 430 1900 400 500 850

Bandgap (eV) 1.12 0.66 1.424 0.36 0.17

Dielectric constant 11.8 16 12.4 14.8 17.7

Right High-µ Material for the Channels

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Ge as a Channel Material

AdvantagesHigh mobility for electrons and holesBetter injection velocity at the sourceMore compatible with VDD scalingLower processing temperatures3D compatible

Disadvantages• Integration with Si necessary - no

Ge substrate availables• No lattice match with Si (defects

misfit dislocation to be avoided)• No native oxide for passivation as

in Si – deposit HK dielectrics• Lower operation temperatures• Higher leakage due to small Eg

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Chui, et al., IEDM 2002; IEEE TED, July, 2006.

Passivation of Ge with GeOxNy, ZrO2 and HfO2

High-k dielectrics reduce leakage by several orders of magnitude Field isolation by GeOxNy + CVD SiO2 1st demo of Ge MOSFETs with metal gate and hi-k

Mobility

Leak

age

@ V

FB1

V (A

/cm

2 )

Equivalent Oxide Thickness (nm)

Leakage

High Mobility p-MOS with High-k Gate Dielectric on Bulk Ge

(100)

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Strain Engineering in CMOS Energy band structure changes with applied stress type (tensile or compressive) and its magnitudeMobility values of carriers change: • Holes – increase under strain (compressive): type and direction in

the channel (complicated). • Electrons – increase under tensile strain

Black mean compressive strainWhite mean tensile strain

|| to <110>

Takagi, Strained-Si CMOS Technology

Synopsys, AMD Corp.

SiC – very difficult material

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Ge, IEDM, 2003

Strain Engineering in CMOS – Orientation

PMOS NMOS

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Hole mobility increases with stress uni-axial compressive and bi-axial tensile stress

Enhancement factors show better mobility improvement for holes that electrons

Strain Induced Modification Of Mobility

Takagi, Strained-Si CMOS Technology

Strain in the MOSFETs can be applied globally or locally. Best performance improvement (still very difficult) for • PMOS is for local strain• NMOS is for global strain

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Uniaxial Strain Silicon Transistors

PMOS NMOS

SiGeSiGe

T. Ghani et. al. IEDM, 2003

SiN stress layer

• SiGe film embedded into source/drain (shape important)

• SiGe film deposited by selective epitaxy• Induces large uniaxial compressive strain in channel • This strain leads to dramatic hole mobility enhancement

Uniaxial tensile stress from high stress Si3N4

Intel first 90nm CMOS

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FETs with S/D having a lattice constant aS/D that is different from that of channel ach. (a) For aS/D > ach, the channel is under compression (S-to-D dir.), e.g. Si UTB p-FET with Ge S/D (b) For aS/D < ach, the channel is under tension, e.g. Si n-channel FinFET with Si:C S/D . S/D stressors may be combined with buried stressors (strain transfer structures).

Yee-Chia Yeo, IEEE 2012

Advanced stressor solutions in CMOS

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45nm High-k + Metal Gate Transistors

Hafnium-based high-k + metal gate transistors are the biggest advancement in transistor

technology since the late 1960s

TEM TEM

65 nm Transistor 45 nm HK + MG

Note the shape of the stressor - important

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SST James

SiGe channel in PMOS

Higher Mobility Than in Si Channels

Tensile stressor

Compressive stressor

SST, James, Dec. 2007

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CMOS With Dual Channels Using Strain Engineering Approach

H. Wong, Nano-CMOS Dielectric Eng

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Various Stress Contributions Leading to Mobility ChangesExtra slide

Mixed orientation in SOI devices - easier integration

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Process Integration of HK with MG for Planar Devices

MG to replace dual poly-Si gates:NMOS VT=0.25~-06VPMOS VT=-0.25~-0.6VDVFB=1.15V

For single midgap workfunction gatePMOS with n+-poly gate VT -1.4~-1.75V too large to adjust by ion implantation Selection of the materials, both HK dielectrics and metal gates, is very challenging

• bandgap and band offsets for HK at Si interface• k-values• compatibility with interlayer and IL formation • mobility degradation• thermal stability: recrystallization and interaction with metal gates

• work-functions for dual gates system• thermal stability and control of EWF• processing integration issues for Si technology and including high mobility materials ex. Ge

49W. Xiong, Sematech Symp., 2010

Instead of dual MG – dual cap scheme to control WF

Gate-first approach

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W. Xiong, Sematech Symp., 2010C.S.Park, IEEE, 2009

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W. Xiong, Sematech Symp., 2010

Instead of dual MG – dual channel layer to improve mobility and LaOx cap to control WF and IL

Gate-first approach

Selective SiGe epi deposition

Single

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W. Xiong, Sematech Symp., 2010

Gate-last approach

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W. Xiong, Sematech Symp., 2010

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Hoffmann, SST, 2010

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Various Design And Processing Approaches In Planar Transistors

Additional technical challenges to be solved for continued scaling processes:• Random Dopant Fluctuation Use low doping in the channel? Change to SOI (UTB) and FINFET designs

• Contacts/junctions formation Shallow and doping, high activation, elevated S/D silicidation Schottky diodes

• Spacers control parasitic capacitance and fringing fields

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Technology Options For CMOS Fabrication