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ECE102: Summary & Highlights

Focusing on Concepts!

MOS i-v Characteristics NMOS* (VOV = vGS – Vtn)

[ ][ ]DSOVoxnDOVDSOV

DSDSOVoxnDOVDSOV

DOV

vVLWCiVvVvvVLWCiVvV

iV

λµ

µ

+=≥≥

−=≤≥

=≤

1 )/(5.0 and 0 :Saturation

2)/(5.0 and 0 :Triode

0 0 :Off-Cut

2

2

*For PMOS replace vGS with vSG and vDS with vSD . Also, VOV = vSG – |Vtp|.

NMOS i-v characteristics is a 3D surface ),( DSGSD vvfi =

F. Najmabadi, ECE102, Fall 2012 (2/21)

Projection

Signal Circuit


Do I

r⋅

≈λ

1

OV

Dm V

Ig ⋅=

2

122>>==

OV

A

OVom V

VV

rgλ

Bias: State of the system when there is no signal. o Bias is constant in time (may vary extremely slowly compared to signal) o Purpose of the bias is to ensure that MOS is in saturation at all times.

Signal: We want the response of the circuit to this input. o Response of the circuit (and its elements) to the signal is different than its

response to the Bias (or to Bias + signal): Signal Circuit

MOS Small signal Model

MOS Fundamental Amplifier Configurations (PMOS circuits are identical)


Common Source with RS oLSm

Lmv rRRg

RgA/1 ′++

′−=

Common Drain/Source Follower

)||(1)||(

Lom

Lomv Rrg

RrgA′+

′=

Common Source )||( Lomv RrgA ′−=

Common Gate )||( Lomv RrgA ′≈

MOS Elementary R Forms (PMOS circuits are identical)


∞

Above configurations are for Small Signal. Typically one or both grounds are connected to bias voltage sources to ensure that MOS is in saturation!

)1()1(Rgr

RRgr

mo

mo

+≈++

ommom

o

rgR

grgRr

+≈++ 1

1

Diode-connected Transistor Always in saturation! m

om g

rg

1||1≈

or

MOS amplifier biasing


Discrete Circuits: Source Degeneration

Two power supplies

DSSSGS IRVV −=

Circuit works as long as Q1 is in saturation

( )( )refref LW

LWII

// 1 1 =

IC Circuits: Current Steering Circuits

Summary of MOS Current Steering Circuit


Bias Model Small Signal Model

Bias current goes through this leg

Signal current goes through this leg (∞ capacitor)

Any circuit that “fixes Iref”

Equivalent circuit

refref

ILWLWI)/()/( 1

1 =

“Intuitive” Model

This “resistor” can be used as the load for the amplifier! Active Load

MOS amplifiers with active load


NMOS CS Amp PMOS CS Amp

NMOS CD Amp PMOS CD Amp

NMOS CG Amp (e.g. Cascode Amp.)

NMOS CG Amp (Stand-alone)

Gain of a Cascode Amplifier


)||(/ 2212 Lomov RrgvvA ′≈=

22

221 1

om

LoiL rg

RrRR+

′+==

)||( )||( / 2212121 Loiommvviov RrRrggAAvvA ′−===

CG stages “reduces” the load seen by the CS stage by gm2ro2

Cascode (signal circuit) CG stage CS stage

Cascode amplifier requires a large load to get a large gain

Cascode amplifier with a cascode current mirror/active load


PMOS Cascode current mirror

Cascode amplifier

Cascode current mirror

1v

4433 )1( oomo rrgr ++

Q3

Q4

Differential Amplifiers


Common-mode and Differential Signal/Gain and CMRR

o Useful in solving symmetric circuits

Concept of half-circuit

o Method to construct differential and common-mode half circuits.

o Half circuits are similar to circuits analyzed before.

o Bias is usually common-mode

Why differential amplifiers are popular o Large CMRR with a slight mis-match o Less difficult biasing

Concept of “Half Circuit”


Common Mode Differential Mode

1. Currents about symmetry line are equal. 2. Voltages about the symmetry line are

equal (e.g., vo1 = vo2) 3. No current crosses the symmetry line.

1. Currents about the symmetry line are equal in value and opposite in sign.

2. Voltages about the symmetry line are equal in value and opposite in sign.

3. Voltage at the summery line is zero

Differential amplifier with current source active load – Bias


Q1 and Q2 are identical & VG2 = VG1

Q3 and Q4 are identical

Parameters of Q5 (i.e., W/L, VG) are chosen such that ID3 = ID4 = 0.5 ID5

54321

2121

5.0

DDDDD

OVOVGSGS

IIIIIVVVV

=====⇒=

Ignoring channel-width modulation:* 1. ID1 = ID3 = 0.5 ID5 sets VOV1 and VGS1 2. VS1 = VGS1 −VG1 3. VD5 = VS1 4. VDS5 = VS1 +VSS 5. We need to include channel-width modulation to

find VDS1 and VDS3 6. Precise biasing of Q1 and Q2 are not necessary to

get correct ID1 (it only affects VDS1 and VDS3 )*

* Similar results are obtained if we do not ignore channel-width modulation: VS =VD5 will adjust to get the correct VGS1 and VOV1 (See problem set)

Differential amplifier with current source active load – Signal analysis


Common Mode

dmdodo

dmdmdo

vrrgvvvrrgvrrgv

)||(5.0 )||(5.0)5.0( )||(

o3o11,1,2

o3o11o3o11,1

−=−=

=−−=

coco

ooom

om

c

co

vvrrrg

rgv

v

,2,1

1351

31,1

/21

=++

−=

Differential Mode

Cascode differential amplifier


Cascode amplifier

Cascode active load

No reason to put a cascode current source here.

Common Mode Differential Mode

Active load for a single-ended output


Works fine but require biasing of Q3 and Q4 (i.e., VG3)

“Popular” active load for single-ended output Q3/Q4 are NOT current sources and do

not require biasing (i.e., VG3) Gets a similar gain and CMRR But, circuit is NOT symmetric (half-circuit

does not work!)

31

53

311

||2

1)||(

ooo

omc

oomd

rrRrg

A

rrgA

=

=

−=

Impact of various capacitors depend on the frequency of interest


f → ∞ All Caps are short. This limit is used to find high-frequency Caps.

f → 0 All Caps are open. This limit is used to find low-frequency Caps

Mid-band: High-f caps are open Low-f caps are short.

Computing fH : High-f caps are included. Low-f caps are short

Computing fL: High-f caps are open. Low-f caps included.

Impendence of capacitors (1/ωC)

MOS high-frequency small signal model


Accurate Model (we use this model here)

Generally, transistor internal capacitances are shown outside the transistor so that we can use results from the mid-band calculations.

High-f capacitors appear between o Input & ground o Output & Ground o Input & Output (For high-gain

amps, this leads to an equivalent large capacitor between input and ground -- Miller’s Theorem)

Miller’s Approximation gives a reasonable approximation to fH, it fails to provide accurate values for each pole and misses the zero.

Miller’s approximation breaks down when gain is close to 1 (See source follower, following slides).

High-frequency response of a CS amplifier – Using Miller’s Theorem


Use Miller’s Theorem to replace capacitor between input & output (Cgd ) with two capacitors at the input and output.

)]||(1[)1(, Lomgdgdigd RrgCACC ′+=−=

*

)]||(/11[)/11(,

gd

Lomgdgdogd

CRrgCACC

≈

′+=−=

)||( Lomg

d RrgvvA ′−==

* Assuming gmR’L >> 1

igdgsin CCC ,+= LogddbL CCCC ++=′ ,

Note: Cgd appears in the input (Cgd,i) as a “much larger” capacitor.

Summary of frequency response


Procedure (low-frequency):

1. Set vsig = 0 2. Consider each capacitor separately, e.g., Cn

(assume others are in mid-band condition)

3. Find the total resistance seen between the terminals of the capacitor, e.g., Rn (treat ground as a regular “node”).

4. The pole associated with that capacitor is

5. Lower-cut-off frequency can be found from

fL ≈ fp1 + fp2 + fp3 + …

nnpn CR

f 21

π=

Procedure (high-frequency)

1. Include internal-capacitances of NMOS and simplify the circuit.

2. Use Miller’s approximation for “Miller” capacitors in configurations with large (and negative) A.

3. Use time-constant method to find fH a. Set vsig = 0 b. Consider each capacitor separately, e.g., Cj

(assume others are in mid-band condition) c. Find the total resistance seen between the

terminals of the capacitor, e.g., Rj (treat ground as a regular “node”).

4. Do not forget about zeros in CS and CD configurations.

jjnj

H

CRbf 11 2

1=Σ==

π

Identify which capacitors contribute to low-f and which to high-f

Some of the circuits we have solved/designed!


You know how to analyze ALL MOS OpAmp circuits of S&S Chapter 12!

ece102: summary & highlightsaries.ucsd.edu/najmabadi/class/ece102/12-f/notes/ece102... ·...

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