ece122 – lab 6 state machines
DESCRIPTION
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering. ECE122 – Lab 6 State Machines. Ritu Bajpai Last revised on October 07, 2009. Introduction. State table gives a time sequence of inputs, outputs and flip flop states. - PowerPoint PPT PresentationTRANSCRIPT
The George Washington UniversitySchool of Engineering and Applied Science
Department of Electrical and Computer Engineering
ECE122 – Lab 6
State Machines
Ritu Bajpai
Last revised on October 07, 2009
Introduction
• State table gives a time sequence of inputs, outputs and flip flop states.
• The information presented in the state table is graphically represented in a state diagram.
• A state equation is an algebraic expression that specifies the conditions for a flip-flop state transition.
Mealy and Moore State Machines
• Mealy state machine has less number of states and the output depends on the input
• Moore state machine, output only depends on the state
Problem for the lab
• Design Mealy and Moore machine to detect the sequence 1010 in a bit pattern.
• Draw state table
• Implement mealy state machine using D flip flops
Mealy state machine
S1
S2
S3
S4Reset/0
1/0
0/0 0/0
1/0
1/00/0 0/11/0
Present State
Next State Output
Input=0 Input=1 Input=0 Input=1
S1 (00) S1 (00) S2(01) 0 0
S2 (01) S3 (10) S2 (01) 0 0
S3 (10) S1 (00) S4 (11) 0 0
S4 (11) S3 (10) S2 (01) 1 0
Moore state machine
S1/0
S2/0S3/0
S4/0Reset
10
0
1
101
S5/1 00
1
Present State
Next State Output
Input=0 Input=1
S1 (000) S1(000) S2(001) 0
S2 (001) S3(010) S2(001) 0
S3 (010) S1(000) S4(011) 0
S4 (011) S3(010) S2(001) 0
S5 (100) S1(000) S4(011) 1
Implementation of Mealy SM using DFF
Inputs of combinational circuit
Output of combinational circuit
Present state Input Next state Flip flop inputs
output
A B x A B DA DB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0
1 1 0 1 0 1 0 1
1 1 1 0 1 0 1 0
State equations
x/AB 00 01 11 10
0 0 1 1 0
1 0 0 0 1
DA=x’B+xAB’
y=ABx’
x/AB 00 01 11 10
0 0 0 0 0
1 1 1 1 1
DB=x
Implementation
Output response
QA
QB
y
nQA
Clear
nQB
Clock
x