ecen 248: introduction to digital systems design dr. shi dept. of electrical and computer...
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![Page 1: ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering](https://reader036.vdocuments.net/reader036/viewer/2022062313/56649d385503460f94a11989/html5/thumbnails/1.jpg)
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS
DESIGN
Dr. Shi
Dept. of Electrical and Computer Engineering
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TIMING ANALYSIS
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Overview Circuits do not respond instantaneously to input
changes Predictable delay in transferring inputs to outputs
Propagation delay Sequential circuits require a periodic clock Goal: analyze clock circuit to determine maximum
clock frequency Requires analysis of paths from flip-flop outputs to flip-
flop inputs Even after inputs change, output signal of circuit
maintains original output for short time
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Sequential Circuits° Sequential circuits can contain both
combinational logic and edge-triggered flip flops
° A clock signal determines when data is stored in flip flops
° Goal: How fast can the circuit operate?• Minimum clock period: Tmin
• Maximum clock frequency: fmax
° Maximum clock frequency is the inverse of the minimum clock period• 1/Tmin = fmax
ClockPeriod
Clock
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Combinational Logic Timing: Inverter
° Combinational logic is made from electronic circuits
• An input change takes time to propagate to the output
° The output remains unchanged for a time period equal to the contamination delay, tcd
° The new output value is guaranteed to valid after a time period equal to the propagation delay, tpd
A Y
A
Y
tpd
tcd
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Combinational Logic Timing: XNOR Gate
A
B C
A
B
C
tpd
tcd
° The output is guaranteed to be stable with old value until the contamination delay
• Unknown values shown in waveforms as Xs
° The output is guaranteed to be stable with the new value after the propagation delay
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Combinational Logic Timing: complex circuits
° Propagation delays are additive • Locate the longest combination of tpd
° Contamination delays may not be additive• Locate the shortest path of tcd
° Find propagation and contamination delay of new, combined circuit
A
B
C A
BC
Circuit X
Circuit X
Tpd = 5nsTcd = 1ns
Tpd = 2nsTcd = 1ns
Tpd = 3nsTcd = 1ns
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Clocked Device: Contamination and Propagation DelayD Q
° Timing parameters for clocked devices are specified in relation to the clock input (rising edge)
° Output unchanged for a time period equal to the contamination delay, tcd after the rising clock edge
° New output guaranteed valid after time equal to the propagation delay, tClk-Q • Follows rising clock edge
Clk
Q
D
tcd
tClk-Q
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Clocked Devices: Setup and Hold Times
D Q ts th
Clk
Q
D
° Timing parameters for clocked devices are specified in relation to the clock input (rising edge)
° D input must be valid at least ts (setup time) before the rising clock edge
° D input must be held steady th (hold time) after rising clock edge
° Setup and hold are input restrictions• Failure to meet restrictions causes circuit to operate
incorrectly
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Edge-Triggered Flip Flop Timing
D
CLK
ts = setup time
th = hold time
° The logic driving the flip flop must ensure that setup and hold requirements are met
° Timing values (tcd tpd tClk-Q ts th)
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Analyzing Sequential Circuits
° What is the minimum time between rising clock edges?
• Tmin = TCLK-Q (FFA) + Tpd (G) + Ts (FFB)
ZComb.Logic
TClk-Q = 5 nsTs = 2 ns
D Q D QYXD
CLK
TClk-Q = 5ns Tpd = 5ns
FFA FFBG
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Analyzing Sequential Circuits
° What is the minimum clock period (Tmin) of this circuit? Hint: evaluate all FF to FF paths
° Maximum clock frequency is 1/Tmin
ZComb.Logic H
TClk-Q = 4 nsTs = 2 ns
D Q D QYX
CLK
TClk-Q = 5ns
Tpd = 5nsFFA FFB
Comb.Logic F
Tpd = 4ns
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Analyzing Sequential Circuits
° Path FFA to FFB • TClk-Q(FFA) + Tpd(H) + Ts(FFB) = 5ns + 5ns + 2ns = 12ns
° Path FFB to FFB• TCLK-Q(FFB) + Tpd(F) + Tpd(H) + Ts(FFB) = 4ns + 4ns + 5ns +
2ns
ZComb.Logic H
TClk-Q = 4 nsTs = 2 ns
D Q D QYX
CLK
TClk-Q = 5ns
Tpd = 5nsFFA FFB
Comb.Logic F
Tpd = 4ns
Fmax = _______
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Analyzing Sequential Circuits: Hold Time Violation
° One more issue: make sure Y remains stable for hold time (Th) after rising clock edge
° Remember: contamination delay ensures signal doesn’t change
° How long before first change arrives at Y?• Tcd(FFA) + Tcd(G) >= Th• 1ns + 2ns > 2ns
ZComb.Logic
Th = 2 ns
D Q D QYXD
CLK
Tcd = 1ns Tcd = 2ns
FFA FFBG
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Analyzing Sequential Circuits: Hold Time Violations
° Path FFA to FFB • TCD(FFA) + TCD(H) > Th(FFB) = 1 ns + 2ns > 2ns
° Path FFB to FFB• TCD(FFB) + TCD(F) + TCd(H) > Th(FFB) = 1ns + 1ns + 2ns > 2ns
ZComb.Logic H
TClD = 1 nsTh = 2 ns
D Q D QYX
CLK
TClD = 1ns
Tcd = 2nsFFA FFB
Comb.Logic F
Tcd = 1ns
All paths must satisfy requirements
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Resolve Setup/Hold Violations Find longest path and reduce the delay
Objective: reduce set up time violation Reduce number of gates on the longest path Increase the gate sizes on the longest path Move gates around …
Find shortest path and increase the delay Objective: reduce hold time violation Reduce the gate size on the shortest path …
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Summary Maximum clock frequency is a fundamental
parameter in sequential computer systems Possible to determined clock frequency
from propagation delays and setup time The longest path determines the clock
frequenct All flip-flop to flip-flop paths must be
checked Hold time are satisfied by examining
contamination delays The shortest contamination delay path
determines if hold times are met