editorial special issue on parallel algorithms for control


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    F. M. F. GASTON

    Digital Systems and Vision Processing, School of Electronic and Electrical Engineering, The University of BirminghamEdgbaston, Birmingham B15 2TT, U.K.

    Within control there is an ever-increasing demand for more and more computation to beperformed in less and less time. Not only are applications faster, but more complex algorithms arebeing used to control them, and recently non-linear control algorithms are becoming morecommonplace. However, if single processors are used, there is a limitation to the amount ofcomputation possible even with modern microprocessor advances. To achieve greater speed-up,parallel hardware must be used. This will be in the form of either application-specic arrayprocessors, such as FPGAs, where VLSI technology enables many simple processors to be put onone chip, which is ne-grained parallelism, or a number of parallel processors, such as the InmosTransputer or Texas Instruments TMS320C40 (C40), connected in a parallel network, which iscoarse-grained parallelism.

    Some of these pieces of hardware have been available for some time now and a number ofsuccessful implementations have been generated. However, many of these implementations havebeen arrived at in a rather ad hoc manner and there is still much work to be done on developinggeneric methods for generating parallel algorithms from rst principles rather than simplyimplementing sequential algorithms on parallel architectures.

    In the computer science literature there are many papers describing how to map algorithmsonto parallel hardware. Their approach is that given a parallel computing platform, how couldone map any algorithm onto it. The approach stems from a general computing perspective.Alternatively, within the digital signal-processing community the approach has been to developapplication-specic hardware implementing relatively simple algorithms for very high data rates.

    However, within control the algorithms are more complex than those used in DSP, although inmany cases they are closely related, and the data rates are much slower, but the requirement isstill for an application-specic architecture: a controller is required, not a general computingplatform running a particular control programme. To meet the needs of the control community,a separate area of research has been developing: parallel processing for control.

    In this special issue we hope to present a number of dierent ideas which will illustrate theproblems and solutions that this area of research is addressing. There are ve papers whichillustrate a number of dierent techniques and perspectives.

    In Reference 1 the authors seek to provide a clear description of the computational processesand associated data ow for the block-regularized parameter estimator, using hierarchical signalow graphs (HSFGs). It describes and develops, and in some ways simplies, some well-knowntechniques for devising parallel algorithms from algebraic descriptions of matrix algorithms. The

    ( 1997 by John Wiley & Sons, Ltd.

  • algorithm used here is a computationally intensive form of robust parameter estimation andtherefore an important algorithm for adaptive control. This papers importance is primarily oneof tutorial value to the broader audience of the adaptive control and signal-processing commun-ity in that it illustrates concepts that have been understood by the specialist community ofparallel processing for a while. However, while it may be tutorial in essence, it does both extendthese ideas and simplify them.

    Adaptive predictive control is computationally intensive and therefore fast algorithms andparallel architectures can have a signicant eect on the processing speed. In Reference 2 new fastalgorithms for three well-known control algorithms are presented: linear quadratic, generalizedpredictive control and stabilizing input/output receding horizon control. These new algorithmsare based on the partial state approach and are approximately half as complex as thosepreviously published. Even greater speed-up is then obtained by using a parallel architecture toimplement them.

    In Reference 3, a parallel algorithm for predictive control is implemented on a two-dimensionaloating-point architecture and then it is modied to use xed-point computation. Fixed-pointnumerical representation is particularly suitable for VLSI implementation. The methodologypresented to convert from oating-point to xed-point is applicable to many other algorithms.

    Reference 4 presents an interesting extension of previously published work so that thetransport delay can be estimated recursively on-line. This requires some algorithm developmentbased on Bayesian probability theory. The result is a highly modular algorithm which can beimplemented on parallel xed-point hardware.

    Lastly, Reference 5 describes a generic approach to developing parallel heterogeneous architec-tures. This is completely dierent from the other papers presented where the algorithms are theprimary concern and the implementation is only considered after the algorithm development. Inthis paper, the algorithm, after being modied to some extent, is mapped onto a parallelarchitecture which can be made up of a number of dierent processors. This approach usesgenetic algorithms to devise a near-optimum network. These ideas are very interesting fordeveloping real control systems that work eciently and eectively in a reasonable amount oftime.

    In this special issue, therefore, a few papers are presented which show how parallel algorithmsand architectures can be developed. It in no way encompasses the many possible approaches, butit illustrates a number of key areas: algorithm representation, algorithm development, xed-pointalgorithms, extension of algorithms and o-the-shelf hardware implementation. There are auto-matic synthesis tools to generate uniform parallel architectures for simple algorithms, but as thesepapers show, there is often a great deal of work to be done on the algorithms themselves beforethey can be successfully mapped onto parallel hardware.


    1. Brown, D. W. and J. G . McWhirter, The design of a block-regularized parameter estimator by algorithm engineering,Int. j. adapt. control signal process., 11, 381393 (1997).

    2. Chisci, L., A. Garulli and G. Zappa, Fast parallel LQ regulator design for adaptive control, Int. j. adapt. control signalprocess., 11, 395413 (1997).

    3. Kadlec, J., F. M. F. Gaston and G. W. Irwin, A parallel xed-point predictive controller, Int. j. adapt. control signalprocess., 11, 415430 (1997).

    4. Schier, J., Estimation of transport delay using parallel recursive modied GramSchmidt algorithm, Int. j. adapt.control signal process., 11, 431442 (1997).

    5. Baxter, M. J., M. O. Tokhi and P. J. Fleming, A generic approach to parallelizing and developing control algorithmsfor heterogeneous architectures, Int. j. adapt. control signal process., 11, 443460 (1997).



    Int. J. Adapt. Control Signal Process., 11, 379380 (1997) ( 1997 by John Wiley & Sons, Ltd.