EDP 2001 Planning MeetingNovember 7, 2001OUTCOMES

Note: Includes several slides from ITRS-2001 Design chapter planning. It would be nice if the EDP community could contribute to the evolution of “Design Process” text in the ITRS. Don Cottrell of SI2 is the contact point for this.

Agenda

• Status Update• Call for Papers, web page

• Charter, Scope, Goals• “niche”, objectives

• Constituencies: EDPS, SI2, CANDE, …

• Special Sessions• invited talks, panels

• Call for Participation

• Action Items / Schedule Going Forward

Misc Action Items/Decisions• OK to have ACM SIGDA “in collaboration” sponsorship; David

should seek this• Sponsorship ideas/contacts ($1500 per): send to David• Registration and paper submission process, plus email based paper

submission option, should be up on the web ASAP• Should investigate other hotels in Monterey (same weekend) in case

Monterey Beach Hotel is “not modern enough”: this is on Rik, David• Agreed to go for an EDP summary of interoperability discussion, at the

Interoperability Workshop before DAC-2001• Jose, Dwight add to program committee (put program committee up

on web/organization chart as well); JohnD add to steering / program committee as well? JohnD, is this okay?

• REWRITE THE CFP AND MISSION, based on discussion at this meeting (this is on Andrew, David)

Charter and Scope - SUMMARY“It’s the Methodology, Stupid”Audience: CAD System Integrators and Methodologists Best practices and war stories “from the trenches” Futures (Methodologies, Tools, Interoperability / Initiatives, Technology Drivers) (Issues: - Metrics: Effort/Cost, Productivity, TAT - Human issues / design team complexities and their management / education and training - Scaling the methodology (from pipecleaner to diskbuster)DOMAINS – FOCUS AREAS Functional Verification *** HW/SW Codesign (?) RTL-Down / Timing Closure *** IP Reuse (maybe not as interesting, if we want to focus on 2-3 areas)DRIVER CLASSES (WHERE IS THE SILICON GOING) – FOCUS AREAS Analog/Mixed-Signal, RF, MEMS SOC

Sample Program – Summary (Incomplete – send suggestions)

Interoperability PanelDAPICFormats and Scripting LanguageseDesignHuman Factors and Design Team ScalingMethodology Development and ScalingMethodologies for SOC IntegrationMethodologies for Back-End Timing ClosureMethodologies for Functional VerificationBreakoutsMeasuring the Methodology

Process for UsSpecific targeted invitations (put them into the Call

for Participation bootstrap)

ITRS-2001 Design and System Drivers Chapters

• Scope of Design Technology• Cost, productivity, quality, and other metrics of Design

Technology• Driver classes and associated emphases

– Analog/RF/MEMS– ASIC = compiled HDL gates – High-volume custom = uP, DSP, embedded memories,

reprogrammable…– SOC: high integration, low cost, low TTM

• Resulting needs (e.g., power, reprogrammability, cost-driven design)

Scenario for SoC Productivity

Year 1999 2002 2005 2008 2011 2014Node 180 nm 130 nm 100 nm 70 nm 50 nm 35 nm

% Area New Logic 64% 32% 16% 8% 4% 2%% Area Reused Logic 16% 16% 13% 9% 6% 4%% Area Memory 20% 52% 71% 83% 90% 94%Transistor Logic Density (Mtrans/cm2) 20 54 133 328 811 2000New Logic Productivity (Mtrans/PY) 1,4 2,1 2,9 4,2 6,0 8,6Reused Logic Productivity (Mtrans/PY) 2,9 4,1 5,9 8,4 12,0 17,1Target Design Resource (PY) 10,0 10,5 10,1 9,9 9,7 9,6

0%

20%

40%

60%

80%

100%

1999

2002

2005

2008

2011

2014

% Area Memory

% Area ReusedLogic

% Area New Logic

Scenario: major increase in memory content

Core ITRS-2001 Figures and Tables

• Table – Metrics of Design Technology• Figure – Evolution of Design System Architecture• Figure – “Business Design Driver” Classes