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TRANSCRIPT
14.1
Unit 14
State Machine Design
14.2
Outcomes
• I can create a state diagram to solve a sequential problem
• I can implement a working state machine given a state diagram
14.3
STATE MACHINES OVERVIEW
14.4
Review of State Machines
• We've implemented state machines in software, now let's see how we can build them in hardware
• State machines are described with state diagrams that show various states, transition arrows between them, and outputs to be generated based on the current state– We use the state to help us know which step of an
algorithm we are currently at
14.5
Hardware State Machines
• Hardware (finite) state machines (aka FSMs) provide the “brains” or control for electronic and electro-mechanical systems– Many custom hardware designs use a hardware-based FSM to control
their operation
• FSMs are required to generate output values at specific times (i.e. when you need time-dependent hardware outputs)– Example 1: Traffic light. The system must automatically transition from
green to yellow to red without any external input stimulus
– Example 2: Sequence detection. Turn an LED on only if a certain code is entered over time (e.g. number lock).
• FSMs require sequential and combinational logic elements– Sequential Logic to remember what step (state) we’re in
• Encodes everything that has happened in the past
– Combinational Logic to produce outputs and find what state to go to next• Generates outputs based on what state we’re in and the input values
14.6
Hardware vs. Software FSM Comparison
Hardware FSMs
• Changes state (makes a transition) every clock cycle
• Uses a register (i.e. flip-flops) to store the current state
• Designer can choose state 'codes' arbitrarily but the choice can greatly affect the size of the circuit
• Uses logic gates (found from a truth table and K-Map or other means) to implement the state transition arrows
• Must implement the initial state value using the RESET signal
Software FSMs
• Changes state (makes a transition) when software pollsthe inputs (which could be very low frequency)
• Uses a variable to store the current state
• Programmer can choose state 'codes' arbitrarily with little implication
• Uses 'if' statements to implement the state transition arrows
• Must implement the initial value of the state variable
14.7
Comparison: FSM in SW and HW
int main()
{
unsigned char state=0; // init state
unsigned char input, output;
while(1)
{
_delay_ms(10); // choose appropriate delay
input = PIND & (1 << PD0);
if(state == 0){
PORTD &= ~(1 << PD7); // output off
if( input ){
state = 1; /* transition */
}
else {
state = 2; /* transition */
}
}
else if(state == 1){
PORTD &= ~(1 << PD7); // output on
if( input ){ state = 2; }
else { state = 0; }
}
else if(state == 2) {
PORTD |= (1 << PD7); // output on
if( !input ) { state = 0; }
}
}
return 0;
}
D Q
Q
D Q
Q
Q0
Q1
D0
D1
X
CLK
F
(Input)(Next State) (Current State)
(Output)
PRE
CLR
0
RESET
PRE
CLR
0
RESETSoftware
Implementation
Hardware
Implementation
State Diagram
state=0: Q1Q0=00
state=1: Q1Q0=01
state=2: Q1Q0=10
14.8
State Machine Example
• Design a sequence detector to check for the combination "101"
• Input, X, provides 1-bit per clock
• Check the sequence of X for "101" in successive clocks
• If "101" detected, output F=1 (F=0 all other times)
"101"
Sequence
Detector
X
CLK
RESET
F
14.9
Another State Diagram Example
• “101” Sequence Detector should output F=1 when the sequence 101 is found in consecutive order
State Diagram for “101”
Sequence Detector
S101S10S1SinitF=1F=0F=0F=0
See the end of this slide set for more detailed solutions
and explanations.
14.10
Correct Specification of State Diagrams
• For HW especially, it is critical that exactly one transition from a state may be true at a time
– We can't go 2 places at once and if we don't tell it explicitly where to go next, it may go to any random state
– If you want to stay in a state, include an explicit loopback arrow• In SW, the state variable will retain its value, but in HW we must be explicit
• On the 2nd example if you want to stay in Q1, include a loopback labeled X=0
Q1
X=1
Q1
X=0
X=1
Q1
NO LABEL =
Unconditional
transition
Incorrect
(No condition
for X = 0)
Correct Correct
Q1
X=1
Incorrect
(2 conditions
true)
X=1
14.11
Correct Specification of State Diagrams 2
• Exactly one transition from a state may be true at a time
– Make sure the conditions you associate with the arrows coming out of a state are mutually exclusive (< 2 true) but all inclusive (> 0 true)
Q1
Incorrect
(More than
one condition
can be true)
Correct
(1 and only 1
condition will
be true at all
times)
X=1
Y = 1
Q1
X=1 and Y=0
Incorrect
(Not all
conditions
covered)
X=0 and Y = 0
Q1
X=1 and Y=1
(X=1 and Y=1)
ALWAYS double check your transitions to ensure they are mutually exclusive.
14.12
State Machines
• The HW for a state machines can be broken into 3 sections of logic
– State Memory (SM)
• Just FF’s to remember the current state
– Next State Logic (NSL)
• Combo logic to determine the next state
• Essentially implements the transition conditions
– Output Function Logic (OFL)
• Combo logic to produce the outputs
14.13
State Machine
CURRENT STATE
The FF outputs
represent the current
state (the state we’re
in right now)
NEXT STATE
The FF inputs will be the value of
the next state logic output. On
the next clock edge the FF
outputs will change based on
these inputs.
Next State Logic State
Memory
(Flip-
Flops)
Output
Function
Logic
inputs
outputsnextstate
currentstate
clock
QiDi
Important: State is always represented and stored by the flip-flop outputs in the system
14.14
State Machines
• Below is a circuit implementing a state machine, notice how it breaks into the 3 sections
SM
NSL
OFLD Q
Q
D Q
Q
Q0
Q1
D0
D1
X
CLK
F
(Input) (Next State) (Current State)
(Output)
14.15
STATE MACHINE DESIGN
14.16
State Diagram vs. State MachineState Diagrams
1. States
2. Transition Conditions
3. Outputs
State Machine
1. State Memory => Flip-Flops (FFs)
– n-FF’s => 2n states
2. Next State Logic (NSL)
– combinational logic
– logic for FF inputs
3. Output Function Logic (OFL)
– MOORE: f(state)
– MEALY: f(state + inputs)
SM
NSL
OFLD Q
Q
D Q
Q
Q0
Q1
D0
D1
X
CLK
F
(Input) (Next State) (Current State)
(Output)
State Diagram for “101”
Sequence Detector
X=1
S101S10S1Sinit
X=0 X=1
X=0
X=1
F=1X=1 X=0
X=0
On Reset
(power on)
F=0F=0F=0
State Machines require sequential logic to
remember the current state
(w/ just combo logic we could only look at the
current value of X, but now we can take 4 separate
actions when X=0)
14.17
State Machine Design
• State machine design involves taking a problem description and coming up with a state diagram and then designing a circuit to implement that operation
Problem
DescriptionState Diagram
Circuit
Implementation
14.18
State Machine Design
• Coming up with a state diagram is non-trivial
• Requires creative solutions
• Designing the circuit from the state diagram is done according to a simple set of steps
• To come up w/ a state diagram to solve a problem
– Write out an algorithm or series of steps to solve the problem
– Each step in your algorithm will usually be one state in your state diagram
– Ask yourself what past inputs need to be remembered and that will usually lead to a state representation
14.19
EXAMPLE 1
14.20
Consecutive 1 Detector
• Given a single-bit input, X, set the output to 1 if the last 2 values of X have been 1
Consecutive 1's
Detector
CLK
RESET
X
X F
14.21
6 Steps of State Machine Design
1. State Diagram
2. Transition/Output Table (Q -> Q*)
3. State Assignment • Determine the # of FF’s required
• Assign binary codes to replace symbolic names
4. Rename Qi* to Di
5. K-Maps for NSL (Di values) and OFL• One K-Map for every FF input
• One K-Map for every output of OFL
6. Draw out the circuit
14.22
Transition Output Table
• Convert state diagram to transition/output table – Show Next State & Output as a function of Current State and Input
Current State
Input (X) Next State
Output (F)
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S0 1
S2 1 S2 1
X=1
S2S1S0
X=0
X=1
X=0
X=0
On Reset
(power on) X=1
F=0 F=0 F=1
14.23
Transition Output Table
• Now assign binary codes to represent states– The order doesn't matter. Use don't cares for unused state codes
Current State
Input Next State Output
Q1 Q0 X Q1* Q0* F
0 0 0 0 0 0
0 0 1 1 1 0
0 1 0 d d d
0 1 1 d d d
1 0 0 0 0 1
1 0 1 1 0 1
1 1 0 0 0 0
1 1 1 1 0 0
Sta
te A
ssig
nm
en
t M
ap
pin
g
State Q1 Q0
S0 0 0
-- 0 1
S1 1 1
S2 1 0
X=1
S2S1S0
X=0
X=1
X=0
X=0
On Reset
(power on) X=1
F=0 F=0 F=1
14.24
Transition Output Table
• Convert state diagram to transition/output table
Current StateNext State
OutputX = 0 X = 1
State Q1 Q0 State Q1* Q0* State Q1* Q0* F
S0 0 0 S0 0 0 S1 1 1 0
-- 0 1 -- d d -- d d d
S1 1 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
Here we have redrawn the 8 row
table from the previous slide into
4 rows & 2 columns. We've also
separated the output F since it
doesn't depend on X but only Q1
and Q0
X=1
S2S1S0
X=0
X=1
X=0
X=0
On Reset
(power on) X=1
F=0 F=0 F=1
No
tic
e w
e u
se
d G
ray C
od
e o
rder.
Th
is w
ill h
elp
in
a f
utu
re s
tep
14.25
Key Idea• So we know the current state value and the desired next state
value for our state flip-flops, but how do we "make" the desired next value
• Key: The D-input of a FF on the current clock will be the value ofQ on the next clock– Analogy: How you prepare and study today will determine your
performance on the exam tomorrow!
• Conclusion: To make Q* = 1 (or 0) next cycle, make D = 1 (or 0) now! (Q* = D)
CLK
Q0
D0
0 1 0 1 0 1 0
TA TB TC TD TE TF TG
1
TH
The D-input of a FF on one clock cycle becomes the Q value on the next.
14.26
D Q
D Q
SM
D0
D1
NSL OFL
Q0
Q1
F
CLK
X
Q1
Q0
CLR
SET
CLR
SET
Current State Feedback
Next State
Rename Q* to D
• The goal is to produce logic for the inputs to the FF’s D1,D0: (aka "excitation equations")
• For D-FF’s Q* will be whatever D is at the edge
Q0*/
Q1*/
14.27
Updated Table
• Find a truth table for the flip-flop inputs (Di) and output (F)
Current StateNext State
OutputX = 0 X = 1
State Q1 Q0 StateQ1*
D1
Q0*
D0State
Q1*
D1
Q0*
D0F
S0 0 0 S0 0 0 S1 1 1 0
-- 0 1 -- d d -- d d d
S1 1 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
X=1
S2S1S0
X=0
X=1
X=0
X=0
On Reset
(power on) X=1
F=0 F=0 F=1
14.28
Karnaugh Maps
• Now need to perform K-Maps for D1, D0, and F
Current StateNext State
OutputX = 0 X = 1
State Q1 Q0 State D1 D0 State D1 D0 F
S0 0 0 S0 0 0 S1 1 1 0
-- 0 1 -- d d -- d d d
S1 1 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
D1 = X
1
0
dd
000
01
11
10
0X
Q1Q0
1
0 1
1
14.29
Karnaugh Maps
• Now need to perform K-Maps for D1, D0, and F
Current StateNext State
OutputX = 0 X = 1
State Q1 Q0 State D1 D0 State D1 D0 F
S0 0 0 S0 0 0 S1 1 1 0
-- 0 1 -- d d -- d d d
S1 1 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
D0 = X•Q1'
1
0
dd
000
01
11
10
0X
Q1Q0
0
0 0
1
D1 = X
1
0
dd
000
01
11
10
0X
Q1Q0
1
0 1
1
14.30
Karnaugh Maps
• Now need to perform K-Maps for D1, D0, and F
Current StateNext State
OutputX = 0 X = 1
State Q1 Q0 State D1 D0 State D1 D0 F
S0 0 0 S0 0 0 S1 1 1 0
-- 0 1 -- d d -- d d d
S1 1 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
1
0d
00
1
0Q1
Q0 1
F = Q1•Q0'
= Q1 XOR Q0
D0 = X•Q1'
1
0
dd
000
01
11
10
0X
Q1Q0
0
0 0
1
D1 = X
1
0
dd
000
01
11
10
0X
Q1Q0
1
0 1
1
14.31
Implementing the Circuit
• Implements the consecutive 1s detector
D Q
Q
D Q
Q
Q0
Q1
D0
D1
X
CLK
F
(Input)(Next State) (Current State)
(Output)
PRE
CLR
0
RESET
PRE
CLR
0
RESET
14.32
Implementing an Initial State
• How can we make the machine start in S0 on reset (or power on?)
• Flip-flops by themselves will initialize to a random state (1 or 0) when power is turned on
X=1
S2S1S0
X=0
X=1
X=0
X=0
On Reset
(power on) X=1
F=0 F=0 F=1
14.33
Implementing an Initial State
• Use the CLEAR and PRESET inputs on our flip-flops in the state memory
– When CLEAR is active the FF initializes Q=0
– When PRESET is active the FF initializes Q=1
D QPRESET
CLR
CLK
14.34
Implementing an Initial State
• We assigned S0 the binary code Q1Q0=00 so we must initialize our flip-flops to Q1Q0=00
X=1
S2S1S0
X=0
X=1
X=0
X=0
On Reset
(power on) X=1
F=0 F=0 F=1
Sta
te A
ssig
nm
en
t M
ap
pin
g
State Q1 Q0
S0 0 0
-- 0 1
S1 1 1
S2 1 0
14.35
Implementing an Initial State
• Use the CLR inputs of your FF’s along with the RESET signal to initialize them to 0’s
• We don't need the PRESET inputs so GND them
D Q
Q
D Q
Q
Q0
Q1
D0
D1
X
CLK
F
(Input)(Next State) (Current State)
(Output)
PRE
CLR
0
RESET
PRE
CLR
0
RESET
14.36
Implementing an Initial State
• When RESET is activated: Q’s initialize to 0
• When RESET is deactivated: Q’s look at the D inputs
Forces Q’s to 0 because it’s
connected to the CLR inputs
Once RESET goes to 0, the FF’s
look at the D inputs
RESET
Q0
Q1
...
...
14.37
Alternate State Assignment
• Important Fact: The codes we assign to our states can have a big impact on the size of the NSL and OFL
• Let us work again with a different set of assignments
Current StateNext State Out
putX = 0 X = 1
State Q1 Q0 State State F
S1 0 0 S0 S2 0
-- 0 1 -- -- d
S2 1 1 S0 S2 1
S0 1 0 S0 S1 0
State Q1 Q0
S0 0 0
-- 0 1
S1 1 1
S2 1 0
Old Assignments
New Assignments
14.38
Alternate State AssignmentCurrent State
Next State Outp
utX = 0 X = 1
State Q1 Q0 StateQ1*
=D1
Q0*
=D0State
Q1*
=D1
Q0*=
D0F
S1 0 0 S0 1 0 S2 1 1 0
-- 0 1 -- d d -- d d d
S2 1 1 S0 1 0 S2 1 1 1
S0 1 0 S0 1 0 S1 0 0 0
0
1d
00
1
0Q1
Q0 1
F = Q1•Q0
= Q0
D0 =
X•Q1'+X•Q0
1
0
dd
000
01
11
10
0X
Q1Q0
1
0 0
1
D1 = X'+Q1'+Q0
1
1
dd
100
01
11
10
0X
Q1Q0
1
1 0
1
14.39
Updated Circuit & Reset Condition
• Consider the initial state implementation S0 = Q1Q0 = 10
D Q
Q
D Q
Q
Q0
Q1
D0
D1
X
CLK
F
(Input)(Next State)
(Current State)
(Output)
PRE
CLR
0
RESET
PRE
CLR
0
RESET
Notice the different state assignment led to larger circuits
(NSL is considerably larger).
We will generally provide you the state assignment!
14.40
EXAMPLE 2
14.41
Traffic Light Controller
• Design the controller for a traffic light at an intersection– Main street has a protected turn while small street does not
• Sensors embedded in the street to detect cars waiting to turn
• Let S = S1 OR S2 to check if any car is waiting
– Simplify and only have Green and Red lights (no yellow)
SSQ1Q0 = 00
MSQ1Q0 = 10
MTQ1Q0 = 11S =
S =
On Reset
(power on)Small Street
Turn
Sensor
S1
Turn
Sensor
S2
Overall sensor
output
S = S1 + S2
Traffic Light
ControllerCLK
RESET
S SSG
MTG
S1
S2
MSG
14.42
State Assignment
• Design of the traffic light controller with main turn arrow
• Represent states with some binary code– Codes: 3 States => 2 bit code: 00=SSG, 10=MSG, 11=MTG
Main Street
Turn
Sensor
S1
Turn
Sensor
S2
Overall sensor
output
S = S1 + S2
State
Diagram
SSQ1Q0 = 00
MSQ1Q0 = 10
MTQ1Q0 = 11S =
S =
On Reset
(power on)
0
1
14.43
K-Maps• Find logic for each FF input by using K-Maps
Current
State
Next StateOutput
S = 0 S = 1
State Q1 Q0 State Q1* Q0* State Q1* Q0* SSG MTG MSG
SS 0 0 MS 1 0 MT 1 1 1 0 0
N/A 0 1 X d d X d d d d d
MT 1 1 MS 1 0 MS 1 0 0 1 0
MS 1 0 SS 0 0 SS 0 0 0 0 1
SSQ1Q0 = 00
MSQ1Q0 = 10
MTQ1Q0 = 11S =
S =
On Reset
(power on)
D1 = Q1’+Q0
1
1
dd
100
01
11
10
0S
Q1Q0
1
0 0
1
D0 = S•Q1’
1
0
dd
000
01
11
10
0S
Q1Q0
0
0 0
1
SSG = Q1’
0
0d
10
1
0Q1
Q0 1
MTG = Q0
0
1d
00
1
0Q1
Q0 1
MSG = Q1•Q0’
1
0d
00
1
0Q1
Q0 1
14.44
EXAMPLE 3
14.45
Water Pump
• Implement the water pump controller using the High and Low sensors as inputs
– Recall the H and L sensor produce 1 when water is covering them and 0 otherwise
Pump
Water Tank
High Sensor
Low Sensor
OFFP=0
ONP=1
H=0H=1L=1
L=0
Notice that in each state, only 1 input matters.
For example, we stay in the OFF state until L=0 regardless of H.
We could write the transition from OFF to ON as:
L=0 and (H=1 OR H=0)
but (H=1 OR H=0) is always True and L=0 and True => L=0, so
we simply drop H's value
14.46
Transition Table
Current State Next StateH L = 0 0 H L = 0 1 H L = 1 1 H L = 1 0
Symbol Q Sym. Q* Sym. Q* Sym. Q* Sym. Q*OFF 0 ON 1 OFF 0 OFF 0 X d
ON 1 ON 1 ON 1 OFF 0 X d
Note: The State Value, Q forms the Pump output (i.e. 1 when we want the pump to be on and 0 othewise)
D = L' + H'Q
1
0
10
100
01
11
10
0Q
H L
0
d d
1
OFFP=0
ONP=1
H’HL
L’
14.47
EXAMPLE 4
Alternating Priority Arbiter
14.48
Problem Description
• Two digital devices (Device 0 and Device 1) can request to use a shared resource via individual request signals: R0 (from Dev0) and R1 (from Dev1)
• An arbiter will examine the requests and issue a grant signal to the appropriate device (G0 to Dev0 and G1 to Dev1).
• Requests are examined during 1 cycle and a grant will be generated on the next, and active for one cycle
• If only one device makes a request during a cycle, it should receive the grant on the next.
• If both devices request on the same cycle, the grant should be given to the device who hasn't received a grant in the longest time.
Alternating
Prioritizing
ArbiterCLK
RESET
R0
R1
G0
G1
Cycle R0 R1 G0 G1
1 1 0 - -
2 1 1 1 0
3 1 1 0 1
4 0 0 1 0
5 1 0 0 0
6 1 1 1 0
7 - - 0 1
14.49
Ex 4: State Diagram Design
• Exercise: Design a state diagram to solve the alternating priority arbiter– Consider how many states you need and what each one helps you
remember or achieve
14.50
EXAMPLE 5
14.51
State Machine Example
• Design a sequence detector to check for the combination "1011"
• Input, X, provides 1-bit per clock
• Check the sequence of X for "1011" in successive clocks
• If "1011" detected, output Z=1 (Z=0 all other times)
"1011"
Sequence
Detector
X
CLK
RESET
Z
14.52
Ex 5: State Diagram Design
• Exercise: Design a state diagram to solve the "1011" sequence detector– Be sure to handle overlapping sequences
Sinit
X=0
Z=0
14.53
Waveform for 1011 Detector
CLOCK
RESET
X
Q0
Q1
Q2
STATE
Z
INITIAL STATE I
14.54
EXAMPLE 4 IMPLEMENTATION
Implementation of our state diagram approach
14.55
Problem Description
• Two digital devices (Device 0 and Device 1) can request to use a shared resource via individual request signals: R0 (from Dev0) and R1 (from Dev1)
• An arbiter will examine the requests and issue a grant signal to the appropriate device (G0 to Dev0 and G1 to Dev1).
• Requests are examined during 1 cycle and a grant will be generated on the next, and active for one cycle
• If only one device makes a request during a cycle, it should receive the grant on the next.
• If both devices request on the same cycle, the grant should be given to the device who hasn't received a grant in the longest time.
Alternating
Prioritizing
ArbiterCLK
RESET
R0
R1
G0
G1
Cycle R0 R1 G0 G1
1 1 0 - -
2 1 1 1 0
3 1 1 0 1
4 0 0 1 0
5 1 0 0 0
6 1 1 1 0
7 - - 0 1
14.56
State Diagram
• Complete the state diagramCycle R0 R1 St. G0 G1
1 1 0 P0W - -
2 1 1 P0G 1 0
3 1 1 P1G 0 1
4 0 0 P0G 1 0
5 1 0 P1W 0 0
6 1 1 P0G 1 0
7 - - P1G 0 1
R0
P0GP0W
R1' R0'
On Reset
(power on)
G0=1
P1W P1G
G1=1
R1' R0
R1' R0'
R1 R0' R1' R0'
R1' R0
R1
R1' R0'
R1 R0'
R1R0
14.57
Transition Table
• Complete the transition table
Current State Next State Output
R1 R0 = 0 0 R1 R0 = 0 1 R1 R0 = 1 1 R1 R0 = 1 0
St. Q1 Q0 St* Q1* Q0* St* Q1* Q0* St* Q1* Q0* St* Q1* Q0* G0 G1
P0W 0 0 P0W 0 0 P0G 1 1 P0G 1 1 P1G 1 0 0 0
P1W 0 1 P1W 0 1 P0G 1 1 P1G 1 0 P1G 1 0 0 0
P0G 1 1 P1W 0 1 P0G 1 1 P1G 1 0 P1G 1 0 1 0
P1G 1 0 P0W 0 0 P0G 1 1 P0G 1 1 P1G 1 0 0 1
R0
P0GP0W
R1' R0'
On Reset
(power on)
G0=1
P1W P1G
G1=1
R1' R0
R1' R0'
R1 R0' R1' R0'
R1' R0
R1
R1' R0'
R1 R0'
R1R0
14.58
Find the NSL and OFLCurrent State Next State Output
R1 R0 = 0 0 R1 R0 = 0 1 R1 R0 = 1 1 R1 R0 = 1 0
St. Q1 Q0 St* Q1* Q0* St* Q1* Q0* St* Q1* Q0* St* Q1* Q0* G0 G1
P0W 0 0 P0W 0 0 P0G 1 1 P0G 1 1 P1G 1 0 0 0
P1W 0 1 P1W 0 1 P0G 1 1 P1G 1 0 P1G 1 0 0 0
P0G 1 1 P1W 0 1 P0G 1 1 P1G 1 0 P1G 1 0 1 0
P1G 1 0 P0W 0 0 P0G 1 1 P0G 1 1 P1G 1 0 0 1
D1 = R1 + R0
1
0
10
000
01
11
10
00R1R0
Q1Q0
1
0 1
01
1
1
1
1
1
1
1
1
11 10
D0 = R1'•Q0 + R0•Q0’
1
1
11
000
01
11
10
00R1R0
Q1Q0
1
0 1
01
1
0
0
1
0
0
0
0
11 10
0
10
00
1
0Q1
Q0 1
G1 = Q1•Q0’
1
00
00
1
0Q1
Q0 1
G0 = Q1•Q0
14.59
Final Circuit
D Q
D Q
SM
D0
D1
NSL OFL
Q0
Q1
CLK
R0
Q1
Q0
CLR
SET
CLR
SET
GND
GND
RESET
RESET
Current State Feedback
Next State
R1G0
G1
14.60
EXAMPLE 5 IMPLEMENTATION
14.61
State Diagram
• Be sure to handle overlapping sequences
X=1
S101S10S1Sinit
X=0 X=1
X=0
X=1
Z=0X=1 X=0
X=0
On Reset
(power on)
Z=0Z=0Z=0
S1011
Z=1
X=1
X=0
14.62
Transition Output Table
• Translate the state diagram into the transition output table
Current StateNext State Outp
utX = 0 X = 1
State Q2 Q1 Q0 State* Q2* Q1* Q0* State* Q2* Q1* Q0* Z
Sinit 0 0 0 Sinit 0 0 0 S1 0 1 1 0
S10 0 0 1 Sinit 0 0 0 S101 0 1 0 0
S1 0 1 1 S10 0 0 1 S1 0 1 1 0
S101 0 1 0 S10 0 0 1 S1011 1 1 0 0
S1011 1 1 0 S10 0 0 1 S1 0 1 1 1
14.63
Transition Output Table
• Translate the state diagram into the transition output table
Current StateNext State Outp
utX = 0 X = 1
State Q2 Q1 Q0 State* D2 D1 D0 State* D2 D1 D0 Z
Sinit 0 0 0 Sinit 0 0 0 S1 0 1 1 0
S10 0 0 1 Sinit 0 0 0 S101 0 1 0 0
S1 0 1 1 S10 0 0 1 S1 0 1 1 0
S101 0 1 0 S10 0 0 1 S1011 1 1 0 0
S1011 1 1 0 S10 0 0 1 S1 0 1 1 1
14.64
NSL & OFL
D2 = X•Q2’•Q1•Q0’
d
0
d0
000
01
11
10
00XQ2
Q1Q0
d
0 0
01
d
d
d
0
0
0
0
1
11 10
d
0
d0
000
01
11
10
00XQ2
Q1Q0
d
0 0
01
d
d
d
1
1
1
1
1
11 10
d
1
d0
000
01
11
10
00XQ2
Q1Q0
d
1 1
01
d
d
d
1
1
0
1
0
11 10
Current StateNext State Out
putX = 0 X = 1
State Q2 Q1 Q0 State* D2 D1 D0 State* D2 D1 D0 Z
Sinit 0 0 0 Sinit 0 0 0 S1 0 1 1 0
S10 0 0 1 Sinit 0 0 0 S101 0 1 0 0
S1 0 1 1 S10 0 0 1 S1 0 1 1 0
S101 0 1 0 S10 0 0 1 S1011 1 1 0 0
S1011 1 1 0 S10 0 0 1 S1 0 1 1 1
D1 = X D0 = Q2 + Q1Q0 + X’Q1 + XQ1’Q0’
d
0
d0
000
01
11
10
0Q2
Q1Q0
d
0 1
1
Z = Q2
14.65
Drawing the Circuit
D0
D1Q
1
Q0
X
NSL
Q2
D2
OFL
Q0
Q1
Z
Q2
SM
14.66
Waveform for 1011 Detector
CLOCK
RESET
X
Q0
Q1
Q2
STATE
Z
INITIAL STATE I
14.67
EXAMPLE 6: ALTERNATING SEQUENCE DETECTOR
14.68
Alternating Detector
• Design a state machine to check if sensor produces two 0’s in a row (i.e. 2 consecutive 0s) or two 1’s in a row (i.e. 2 consecutive 1s)
•G10 = Last cycle we got 1,
two cycles ago we got 0
•G01 = Last cycle we got 0,
two cycles ago we got 1
•G11 = Got 2 consecutive 1’s
•G00 = Got 2 consecutive 0's
G01A=1
G10A=1
G00A=0
G11A=0
S = 0
S = 1
S = 0 S = 1
S = 0
S = 1
S = 1S = 0
On Reset
(power on)
14.69
Transition Output Table
• Convert state diagram to transition/output table – Show Next State & Output as a function of Current State and Input
Current State
Input (S) Next State
Output (A)
G01 0 G00 1
G01 1 G10 1
G11 0 G01 0
G11 1 G11 0
G00 0 G00 0
G00 1 G10 0
G10 0 G01 1
G10 1 G11 1
G01A=1
G10A=1
G00A=0
G11A=0
S = 0
S = 1
S = 0 S = 1
S = 0
S = 1
S = 1S = 0
On Reset
(power on)
14.70
Transition Output Table
• Now assign binary codes to represent states
Current State
Input Next State Output
Q1 Q0 S Q1* Q0* A
0 0 0 1 0 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 0 1 1
Sta
te A
ssig
nm
en
t M
ap
pin
g
State Q1 Q0
G01 0 0
G11 0 1
G00 1 0
G10 1 1
G01A=1
G10A=1
G00A=0
G11A=0
S = 0
S = 1
S = 0 S = 1
S = 0
S = 1
S = 1S = 0
On Reset
(power on)
14.71
Transition Output Table
• Convert state diagram to transition/output table
Current StateNext State
OutputS = 0 S = 1
State Q1 Q0 State State A
G01 0 0 G00 1 0 G10 1 1 1
G11 0 1 G01 0 0 G11 0 1 0
G10 1 1 G01 0 0 G11 0 1 1
G00 1 0 G00 1 0 G10 1 1 0
Here we have redrawn the 8
row table from the previous
slide into 4 rows & 2 columns.
We've also separated the
output A since it doesn't
depend on S but only Q1 and
Q0
G01A=1
G10A=1
G00A=0
G11A=0
S = 0
S = 1
S = 0 S = 1
S = 0
S = 1
S = 1S = 0
On Reset
(power on)
14.72
Excitation Table
• The goal is to produce logic for the inputs to the FF’s (D1,D0)…these are the excitation equations
CLK
D Q
D Q
A
OFL
(Output
Function Logic)SM
(State Memory)
D0 Q0(t)
Q1(t)
Q1(t)
Q0(t)
S
Current State Feedback
CLK
CLK
D1
NSL
(Next State Logic)
14.73
Excitation Table
• Using your transition table you know what you want Q* to be, but how can you make that happen?
• For D-FF’s Q* will be whatever D is at the edge
CLK
D Q
D Q
A
OFL
(Output
Function Logic)SM
(State Memory)
D0 Q0(t)
Q1(t)
Q1(t)
Q0(t)
S
Current State Feedback
CLK
CLK
D1
NSL
(Next State Logic)
14.74
Excitation Table
• In a D-FF Q* will be whatever D is, so if we know what we want Q* to be just make sure that’s what the D input is
Current State
Next State
OutputS = 0 S = 1
State Q1 Q0 State D1 D0 State D1 D0 A
G01 0 0 G00 1 0 G10 1 1 1
G11 0 1 G01 0 0 G11 0 1 0
G10 1 1 G01 0 0 G11 0 1 1
G00 1 0 G00 1 0 G10 1 1 0
14.75
Karnaugh Maps
• Now need to perform K-Maps for D1, D0, and A
Current StateNext State
OutputS = 0 S = 1
State Q1 Q0 State D1 D0 State D1 D0 A
G01 0 0 G00 1 0 G10 1 1 1
G11 0 1 G01 0 0 G11 0 1 0
G10 1 1 G01 0 0 G11 0 1 1
G00 1 0 G00 1 0 G10 1 1 0
D1 = Q0’
1
0
00
100
01
11
10
0S
Q1Q0
0
1 1
1
14.76
Karnaugh Maps
• Now need to perform K-Maps for D1, D0, and A
Current StateNext State
OutputS = 0 S = 1
State Q1 Q0 State D1 D0 State D1 D0 A
G01 0 0 G00 1 0 G10 1 1 1
G11 0 1 G01 0 0 G11 0 1 0
G10 1 1 G01 0 0 G11 0 1 1
G00 1 0 G00 1 0 G10 1 1 0
D1 = Q0’
1
0
00
100
01
11
10
0S
Q1Q0
0
1 1
1
D0 = S
1
0
10
000
01
11
10
0S
Q1Q0
1
0 1
1
14.77
Karnaugh Maps
• Now need to perform K-Maps for D1, D0, and A
Current StateNext State
OutputS = 0 S = 1
State Q1 Q0 State D1 D0 State D1 D0 A
G01 0 0 G00 1 0 G10 1 1 1
G11 0 1 G01 0 0 G11 0 1 0
G10 1 1 G01 0 0 G11 0 1 1
G00 1 0 G00 1 0 G10 1 1 0
D1 = Q0’
1
0
00
100
01
11
10
0S
Q1Q0
0
1 1
1
D0 = S
1
0
10
000
01
11
10
0S
Q1Q0
1
0 1
1
0
10
10
1
0Q1
Q0 1
A = Q1’Q0’ + Q1Q0
= Q1 XNOR Q0
14.78
Implementing the Circuit
• Implements the alternating detector
CLK
D Q
D Q
A
OFL
(Output
Function Logic)SM
(State Memory)
D0 Q0(t)
Q1(t)
Q1(t)
Q0(t)
S
Current State Feedback
CLK
CLK
D1
NSL
(Next State Logic)
unused
14.79
Implementing an Initial State
• How can we make the machine start in G0 on reset (or power on?)
• Flip-flops by themselves will initalize to a random state (1 or 0) when power is turned on
G01A=1
G10A=1
G00A=0
G11A=0
S = 0
S = 1
S = 0 S = 1
S = 0
S = 1
S = 1S = 0
On Reset
(power on)
14.80
Implementing an Initial State
• Use the CLR inputs of your FF’s along with the RESET signal to initialize them to 0’s
CLK
D Q
D Q
A
OFL
(Output
Function Logic)SM
(State Memory)
D0
D1
Q0(t)
Q1(t)
Q1(t)
Q0(t)
S
Current State Feedback
CLK
CLK
PRE
CLR
0
RESET
PRE
CLR
0
RESET
NSL
(Next State Logic)
14.81
Implementing an Initial State
• We don't want to initialize our flip-flops to 1's (only Q1Q0=00) so we just don't use PRE (tie to 'off'='0')
CLK
D Q
D Q
A
OFL
(Output
Function Logic)SM
(State Memory)
D0
D1
Q0(t)
Q1(t)
Q1(t)
Q0(t)
S
Current State Feedback
CLK
CLK
PRE
CLR
0
RESET
PRE
CLR
0
RESET
NSL
(Next State Logic)
14.82
Alternate State Assignment
• Important Fact: The codes we assign to our states can have a big impact on the size of the NSL and OFL
• Let us work again with a different set of assignments
Current StateNext State Out
putS = 0 S = 1
State Q1 Q0 State State A
G01 0 0 G00 G10 1
G10 0 1 G01 G11 1
G00 1 1 G00 G10 0
G11 1 0 G01 G11 0
State Q1 Q0
G01 0 0
G11 0 1
G10 1 1
G00 1 0
Old Assignments
New Assignments
14.83
Alternate State Assignment
Current StateNext State
OutputS = 0 S = 1
State Q1 Q0 StateQ1*=
D1
Q0*=
D0State
Q1*
=D1
Q0*
=D0A
G01 0 0 G00 1 1 G10 0 1 1
G10 0 1 G01 0 0 G11 1 0 1
G00 1 1 G00 1 1 G10 0 1 0
G11 1 0 G01 0 0 G11 1 0 0
D1 = S xor Q1 xor Q0
0
1
10
100
01
11
10
0S
Q1Q0
0
0 1
1
D0 = Q1’Q0’ + Q1Q0
1
1
00
100
01
11
10
0S
Q1Q0
1
0 0
1
0
01
10
1
0Q1
Q0 1
A = Q1’
14.84
SELECTED SOLUTIONS
14.85
Another State Diagram Example
• “101” Sequence Detector should output F=1 when the sequence 101 is found in consecutive order
State Diagram for “101”
Sequence Detector
X=1
S101S10S1Sinit
X=0 X=1
X=0
X=1
F=1X=1 X=0
X=0
On Reset
(power on)
F=0F=0F=0
14.86
Another State Diagram Example
• “101” Sequence Detector should output F=1 when the sequence 101 is found in consecutive order
X=1
S101S10S1Sinit
X=0 X=1
X=0
X=1
F=1X=1 X=0
X=0
On Reset
(power on)
F=0F=0F=0
We have to remember the 1,0,1 along the way
A ‘0’ initially is not
part of the sequence
so stay in Sinit Another ‘1’ in S1 means
you have 11, but that
second ‘1’ can be the
start of the sequence
A ‘0’ in S10 means
you have 100 which
can’t be part of the
sequence