ee141 © digital integrated circuits 2nd manufacturing 1 digital integrated circuits a design...
TRANSCRIPT
EE141© Digital Integrated Circuits2nd Manufacturing1
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
ManufacturingManufacturingProcessProcess
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003
EE141© Digital Integrated Circuits2nd Manufacturing2
Goal of Chapter 2Goal of Chapter 2 Understand the basic CMOS manufacturing steps
Understand layout of transistors
Understand layout rules
EE141© Digital Integrated Circuits2nd Manufacturing3
CMOS n-well ProcessCMOS n-well Process
EE141© Digital Integrated Circuits2nd Manufacturing4
Modern dual-well CMOS ProcessModern dual-well CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
Dual-Well Trench-Isolated CMOS ProcessDual-Well Trench-Isolated CMOS Process
EE141© Digital Integrated Circuits2nd Manufacturing5
Circuit Under DesignCircuit Under Design
VDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
EE141© Digital Integrated Circuits2nd Manufacturing6
Its Layout ViewIts Layout View
EE141© Digital Integrated Circuits2nd Manufacturing7
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
Photo-Lithographic ProcessPhoto-Lithographic Process
EE141© Digital Integrated Circuits2nd Manufacturing8
Patterning of SiO2: create isolationPatterning of SiO2: create isolation
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-light
Patternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
EE141© Digital Integrated Circuits2nd Manufacturing9
CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
EE141© Digital Integrated Circuits2nd Manufacturing10
CMOS Process Walk-ThroughCMOS Process Walk-Through
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epiSiO2
3SiN
4
(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
EE141© Digital Integrated Circuits2nd Manufacturing11
CMOS Process Walk-ThroughCMOS Process Walk-ThroughSiO2
(d) After trench filling, CMP planarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
EE141© Digital Integrated Circuits2nd Manufacturing12
CMOS Process Walk-ThroughCMOS Process Walk-Through
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+ source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
Nwell Pwell
EE141© Digital Integrated Circuits2nd Manufacturing13
CMOS Process Walk-ThroughCMOS Process Walk-Through
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO2insulator, etching of via’s,
deposition and patterning ofsecond layer of Al.
AlSiO2
EE141© Digital Integrated Circuits2nd Manufacturing14
Advanced MetallizationAdvanced Metallization
EE141© Digital Integrated Circuits2nd Manufacturing15
The Manufacturing ProcessThe Manufacturing Process
For a great tour through the IC manufacturing process and its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.html
EE141© Digital Integrated Circuits2nd Manufacturing16
Design RulesDesign Rules
EE141© Digital Integrated Circuits2nd Manufacturing17
3D Perspective3D Perspective
Polysilicon Aluminum
EE141© Digital Integrated Circuits2nd Manufacturing18
Design RulesDesign Rules Interface between designer and process
engineer
Guidelines for constructing process masks
Unit dimension: Minimum length scalable design rules: lambda parameter
(SCMOS SUBMICRON Design Rules)
Technology=2 lambda absolute dimensions (micron rules)
EE141© Digital Integrated Circuits2nd Manufacturing19
Layers in 0.25 Layers in 0.25 m CMOS processm CMOS process
EE141© Digital Integrated Circuits2nd Manufacturing20
CMOS Process Layers (an example)CMOS Process Layers (an example)
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
EE141© Digital Integrated Circuits2nd Manufacturing21
Intra-Layer Design RulesIntra-Layer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
EE141© Digital Integrated Circuits2nd Manufacturing22
Transistor LayoutTransistor Layout
1
2
5
3
Tra
nsis
tor
EE141© Digital Integrated Circuits2nd Manufacturing23
Vias and ContactsVias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
EE141© Digital Integrated Circuits2nd Manufacturing24
CMOS Inverter LayoutCMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
EE141© Digital Integrated Circuits2nd Manufacturing25
Layout EditorLayout Editor
EE141© Digital Integrated Circuits2nd Manufacturing26
Design Rule CheckDesign Rule Check
poly_not_fet to all_diff minimum spacing = 0.14 um.
EE141© Digital Integrated Circuits2nd Manufacturing27
Sticks DiagramSticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities •Only topology is important
• Final layout generated by “compaction” program
EE141© Digital Integrated Circuits2nd Manufacturing28