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EE141EE141-- Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuits

Lecture 25Lecture 25Oscillators and BiOscillators and Bi--stablesstables

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Administrative StuffAdministrative StuffHomework 8 posted – Due on FrLast software lab THIS weekProject on web-site!No class on Th – Make-up lecture probably next week Fr

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Class MaterialClass Material

Today’s lectureOscillators and multivibratorsTiming

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Other Sequential CircuitsOther Sequential Circuits

Schmitt TriggerMonostable MultivibratorsAstable Multivibrators

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Schmitt TriggerSchmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

•VTC with hysteresis

•Restores signal slopes

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Noise Suppression usingNoise Suppression usingSchmitt TriggerSchmitt Trigger

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CMOS Schmitt TriggerCMOS Schmitt Trigger

Moves switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3

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Schmitt TriggerSchmitt TriggerSimulated VTCSimulated VTC

2.5

V

X

(V)

VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4. The width is k* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

V

x

(V)

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

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CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)

VDD

VDD

OutIn

M1

M5

M2

X

M3

M4

M6

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MultivibratorMultivibrator CircuitsCircuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

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TransitionTransition--Triggered Triggered MonostableMonostable

DELAY

td

In

Outtd

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MonostableMonostable Trigger (RCTrigger (RC--based)based)

VDD

InOutA B

C

R

In

B

Outt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.

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AstableAstable MultivibratorsMultivibrators (Oscillators)(Oscillators)0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

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Relaxation OscillatorRelaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC

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Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vco ntr (V)

0.0

2

4

6

t pH

L (

nsec

)

propagation delay as a functionof control voltage

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Timing Timing DefinitionsDefinitions

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Synchronous TimingSynchronous Timing

CombinationalLogic

R1 R2Cin Cout Out

In

CLK

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Latch ParametersLatch Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

PWmtsu

td-q

Delays can be different for rising and falling data transitions

T

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Register ParametersRegister Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

T

tsu

Delays can be different for rising and falling data transitions

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Clock UncertaintiesClock Uncertainties

Sources of clock uncertainty

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

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Clock Clock NonidealitiesNonidealities

Clock skewSpatial variation in temporally equivalent clock edges; deterministic + random, tSK

Clock jitterTemporal variations in consecutive edges of the clock signal; modulation + random noiseCycle-to-cycle (short-term) tJS

Long term tJL

Variation of the pulse width Important for level sensitive clocking

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Clock Skew and JitterClock Skew and Jitter

Both skew and jitter affect the effective cycle timeOnly skew affects the race margin

Clk

Clk

tSK

tJS

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Clock SkewClock Skew# of registers

Clk delayInsertion delay

Max Clk skew

Earliest occurrenceof Clk edgeNominal – δ/2

Latest occurrenceof Clk edge

Nominal + δ /2

δ

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Positive and Negative SkewPositive and Negative Skew

R1In

(a) Positive skew

CombinationalLogicD Q

tCLK1CLK

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogicD Q

tCLK1

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay CLK

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Positive SkewPositive Skew

Launching edge arrives before the receiving edge

CLK1

CLK2

TCLK

δ

TCLK + δ

+ thδ

2

1

4

3

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Negative SkewNegative Skew

Receiving edge arrives before the launching edge

CLK1

CLK2

TCLK

δ

TCLK + δ

2

1

4

3

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Timing ConstraintsTiming Constraints

Minimum cycle time:T + δ = tc-q + tlogic + tsu

Worst case is when receiving edge arrives early (negative δ)

R1

D Q CombinationalLogic

In

CLK tCLK1

R2

D Q

tCLK2

tc − qtc − q, cdtsu, thold

tlogictlogic, cd

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Timing ConstraintsTiming Constraints

Hold time constraint:t(c-q, cd) + t(logic, cd) > thold + δ

Worst case is when receiving edge arrives late (positive δ )Race between data and clock

R1

D Q CombinationalLogic

In

CLK tCLK1

R2

D Q

tCLK2

tc − qtc − q, cdtsu, thold

tlogictlogic, cd

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Impact of JitterImpact of Jitter

CLK

-tji tter

TC LK

t j itter

CLK

InCombinational

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter

1

2

3 4

5

6

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Longest Logic Path in Longest Logic Path in EdgeEdge--Triggered SystemsTriggered Systems

Clk

T

TSU

TClk-QTLM

Latest point of launching

Earliest arrivalof next cycle

TJI + δ

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Clock Constraints in Clock Constraints in EdgeEdge--Triggered SystemsTriggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU < T – TJI,1 – TJI,2 - δ

Tc-q + TLM + TSU + δ + 2 TJI < T

Skew can be either positive or negative

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Shortest PathShortest Path

ClkTClk-Q TLm

Earliest point of launching

Data must not arrivebefore this time

ClkTH

Nominalclock edge

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Clock Constraints Clock Constraints in Edgein Edge--Triggered SystemsTriggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < TH + TJI,2 + δ

Tc-q + TLM < TH + 2TJI+ δ

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How to counter Clock Skew?How to counter Clock Skew?

RE

G

φ

RE

G

φ

RE

G

φ

.

RE

G

φ

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing

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Clock DistributionClock Distribution

Clock is distributed in a tree-like fashion

H-tree

CLK

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More realistic HMore realistic H--treetree

[Restle98]

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The Grid SystemThe Grid SystemDriver

Driver

Dri

ver

Driv

er

GCLK GCLK

GCLK

GCLK

•No rc-matching•Large power

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Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million Transistors

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)

Uses Two Level Clock Distribution:

• Single 6-stage driver at center of chip

• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4

Total driver size: 58 cm!

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21164 Clocking21164 Clocking2 phase single wire clock, distributed globally2 distributed driver channels

Reduced RC delay/skewImproved thermal distribution

3.75nF clock load58 cm final driver width

Local inverters for latchingConditional clocks in caches to reduce powerMore complex race checkingDevice variation

trise = 0.35ns tskew = 150ps

tcycle= 3.3ns

Clock waveform

Location of clockdriver on die

pre-driver

final drivers

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Clock Drivers

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Clock Skew in Alpha ProcessorClock Skew in Alpha Processor

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2 Phase, with multiple conditional buffered clocks

2.8 nF clock load

40 cm final driver width

Local clocks can be gated “off” to save powerReduced load/skew

Reduced thermal issues

Multiple clocks complicate race checking

trise = 0.35ns tskew = 50ps

tcycle= 1.67ns

EV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz 600 MHz –– 0.35 micron CMOS0.35 micron CMOS

Global clock waveform

PLL

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21264 Clocking21264 Clocking

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EV6 Clock ResultsEV6 Clock Results

GCLK Skew(at Vdd/2 Crossings)

ps5101520253035404550

ps300305310315320325330335340345

GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)

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EV7 Clock HierarchyEV7 Clock Hierarchy

GCLK(CPU Core)L

2L_C

LK

(L2

Cac

he)

L2R

_CL

K(L

2 C

ache

)

NCLK(Mem Ctrl)

DLL

PL

L

SYSCLK

DL

L

DL

L+ widely dispersed

drivers

+ DLLs compensate static and low-frequency variation

+ divides design and verification effort

- DLL design and verification is added work

+ tailored clocks

Active Skew Management and Multiple Clock Domains

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SelfSelf--timed and Asynchronous timed and Asynchronous DesignDesign

Functions of clock in synchronous design

1) Acts as completion signal

2) Ensures the correct ordering of events

Truly asynchronous design

2) Ordering of events is implicit in logic1) Completion is ensured by careful timing analysis

Self-timed design

1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol